CN106663693A - 碳化硅半导体装置 - Google Patents
碳化硅半导体装置 Download PDFInfo
- Publication number
- CN106663693A CN106663693A CN201480080201.5A CN201480080201A CN106663693A CN 106663693 A CN106663693 A CN 106663693A CN 201480080201 A CN201480080201 A CN 201480080201A CN 106663693 A CN106663693 A CN 106663693A
- Authority
- CN
- China
- Prior art keywords
- region
- channel resistance
- resistance adjustment
- silicon carbide
- carbide semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims description 46
- 229910010271 silicon carbide Inorganic materials 0.000 title claims description 46
- 239000004065 semiconductor Substances 0.000 title claims description 31
- 239000010410 layer Substances 0.000 claims abstract description 45
- 239000012535 impurity Substances 0.000 claims abstract description 14
- 239000011229 interlayer Substances 0.000 claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 13
- 150000002500 ions Chemical class 0.000 claims description 4
- 230000009467 reduction Effects 0.000 abstract description 5
- 239000002344 surface layer Substances 0.000 abstract 1
- 238000010276 construction Methods 0.000 description 14
- 230000000694 effects Effects 0.000 description 7
- 230000005684 electric field Effects 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910005883 NiSi Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02378—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0856—Source regions
- H01L29/086—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
- H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/1608—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System further characterised by the doping material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
Abstract
本发明能够一边抑制短路耐量的降低,一边降低导通电阻。本发明具有SiC外延层(2)、阱区域(3)、源极区域(4)、沟道电阻调整区域(6)、栅极电极(7)、层间绝缘膜(9)、源极电极(10)、以及漏极电极(12)。沟道电阻调整区域(6)是在阱区域(3)的表层被源极区域(4)和SiC外延层(2)夹着而形成的。沟道电阻调整区域(6)是,在与由源极区域(4)和SiC外延层(2)夹着沟道电阻调整区域(6)的方向相交叉的方向,间断地形成第1杂质区域的区域。
Description
技术领域
本发明涉及一种逆变器装置等所使用的碳化硅半导体装置。
背景技术
就现有的n沟道型SiC-金属-氧化物-半导体场效应晶体管(metal-oxide-semiconductor field-effect transistor,MOSFET)而言,为了降低沟道电阻(导通电阻),提出了使沟道长度变短、或者在沟道区域的整个面进行n型的离子注入等设计(专利文献1)。
专利文献1:日本特开昭59-149057号公报
发明内容
但是,现有的SiC-MOSFET存在下述问题,即,通过以上述的方法降低沟道电阻,即降低导通电阻,从而饱和电流变大,短路耐量大幅地降低。
本发明就是为了解决上述问题而提出的,其目的在于提供一种能够一边抑制短路耐量的降低、一边降低导通电阻的技术。
本发明的一个方式涉及的碳化硅半导体装置具有:第1导电型的外延层,其形成于碳化硅半导体衬底的上表面;第2导电型的阱区域,其在所述外延层的表层局部地形成;第1导电型的源极区域,其在所述阱区域的表层局部地形成;沟道电阻调整区域,其是在所述阱区域的表层被所述源极区域和所述外延层夹着而形成的;栅极电极,其在所述沟道电阻调整区域的上表面隔着栅极绝缘膜而形成;层间绝缘膜,其形成为将所述栅极电极覆盖;源极电极,其形成于所述层间绝缘膜的上表面以及所述源极区域的上表面;以及漏极电极,其形成于所述碳化硅半导体衬底的下表面,所述沟道电阻调整区域是,在与由所述源极区域和所述外延层夹着所述沟道电阻调整区域的方向相交叉的方向,间断地形成第1导电型的第1杂质区域、或者第2导电型的第2杂质区域的区域,在所述沟道电阻调整区域为间断地形成所述第1杂质区域(6)的区域的情况下,所述第1杂质区域(6)的杂质浓度比所述外延层(2)的杂质浓度高,在所述沟道电阻调整区域为间断地形成所述第2杂质区域(6a)的区域的情况下,所述第2杂质区域(6a)的杂质浓度比所述阱区域(3)的杂质浓度高。
发明的效果
根据本发明的上述方式,能够一边抑制短路耐量的降低,一边降低导通电阻。即,通过在阱区域的表层局部地形成载流子浓度不同的区域(沟道电阻调整区域),从而电流会局部地集中于沟道电阻低的区域。于是,电流集中的部分局部地发热,其电阻变高,因此抑制流过的电流。因而,与沟道部的载流子浓度均匀且导通电阻相同的半导体装置相比,饱和电流得到抑制,因此短路耐量提高。
本发明的目的、特征、技术方案以及优点通过以下的详细说明和附图会变得更加清楚。
附图说明
图1是表示实施方式涉及的碳化硅半导体装置的构造的剖视图。
图2是表示实施方式涉及的碳化硅半导体装置的构造的俯视图。
图3是表示实施方式涉及的碳化硅半导体装置的另一个构造的剖视图。
图4是表示实施方式涉及的碳化硅半导体装置的另一个构造的俯视图。
图5是表示实施方式涉及的碳化硅半导体装置的变形例的构造的俯视图。
图6是表示实施方式涉及的碳化硅半导体装置的变形例的构造的剖视图。
具体实施方式
下面,一边参照附图,一边对实施方式进行说明。此外,附图是示意性地示出的,在不同的附图分别示出的图像的尺寸及位置的相互关系未必记载得准确,可以适当地进行变更。另外,在下面的说明中,对相同的结构要素标注相同的标号而进行图示,它们的名称及功能也相同。因此,有时省略针对它们的详细说明。
另外,在下面的说明中,有时使用“上”、“下”、“侧”、“底”、“表”或者“背”等代表特定的位置及方向的用语,但这些用语是为了使实施方式的内容容易理解,出于方便而使用的,与实际实施时的方向无关。
<第1实施方式>
<结构>
图1是表示本实施方式涉及的碳化硅半导体装置的构造的剖视图。图1是包含沟道电阻调整区域的SiC-MOSFET的芯片剖视图。图2是表示本实施方式涉及的碳化硅半导体装置的构造的俯视图。
半导体衬底使用SiC衬底1,在n+型的SiC衬底1的上表面形成外延生长出的n-型的SiC外延层2。
在SiC外延层2的表层局部地(选择性地)形成p型的阱区域3。在阱区域3的表层局部地(选择性地)形成n型的源极区域4。在源极区域4的表层形成p型的接触区域5。
另外,在阱区域3的表层形成沟道电阻调整区域6,在俯视观察时该沟道电阻调整区域6被源极区域4和iC外延层2夹着。
另外,横跨源极区域4的上表面的一部分、沟道电阻调整区域6的上表面以及SiC外延层2的上表面而形成栅极电极7。栅极电极7例如由多晶硅构成。栅极电极7是隔着栅极绝缘膜8而形成的。栅极绝缘膜8例如由二氧化硅构成。
另外,将栅极绝缘膜8覆盖而形成层间绝缘膜9。层间绝缘膜9例如由正硅酸乙酯(Tetraethyl orthosilicate,TEOS)构成。另外,在层间绝缘膜9的上表面以及源极区域4的上表面形成源极电极10。源极电极10隔着NiSi层11而形成于接触区域5之上以及源极区域4之上。
在SiC衬底1的下表面(背面)形成漏极电极12。
沟道电阻调整区域的形成方法有2种,分别为如图1及图2所示的作为n型的区域而形成的方法、如图3及图4所示的作为高浓度的p型的区域而形成的方法。
在作为n型的区域而形成的情况下,沟道电阻调整区域6是,在与由源极区域4和SiC外延层2夹着沟道电阻调整区域6的方向相交叉的方向,间断地形成第1导电型(n型)的杂质区域(第1杂质区域)的区域。
在作为p型的区域而形成的情况下,沟道电阻调整区域6a是,在与由源极区域4和SiC外延层2夹着沟道电阻调整区域6a的方向相交叉的方向,间断地形成第2导电型(p型)的杂质区域(第2杂质区域)的区域。
在这里,图3是表示本实施方式涉及的碳化硅半导体装置的另一个构造的剖视图。图4是表示本实施方式涉及的碳化硅半导体装置的另一个构造的俯视图。
在如图1及图2所示的作为n型的区域而形成沟道电阻调整区域6的方法中,在MOSFET的单元内局部地形成沟道电阻低的区域。例如,如图2所示,在俯视观察时将源极区域4的四周包围而在将源极区域4包围的边处间断地形成沟道电阻调整区域6。
通过这样地形成沟道电阻调整区域6,从而降低沟道电阻。另外,在短路时流过了大电流的情况下,电流集中于沟道电阻调整区域6,电流集中的部分局部地发热,电阻变高,因此抑制流过的电流。因而,与沟道部的浓度均匀且导通电阻相同的MOSFET相比,饱和电流得到抑制,因此短路耐量提高。
另外,通过规则地且等间隔地形成载流子浓度不同的区域,从而如果作为芯片整体来看,则电流是均匀流过的,能够防止由于局部的电流集中而引起的芯片的破坏。
此外,沟道电阻低的沟道电阻调整区域6形成于各单元的除了所产生的电场变大(即,电场容易集中)的角部(将源极区域4包围的角部)以外的地方,从而在短路时元件不易被破坏。
在图1及图2中例示了排列有四边形的单元的构造,但条带构造的单元也会产生同样的效果。
另外,在图1及图2中示出了如下构造,即,四边形的各单元之间的区域形成为格子状,在该格子的相交叉的位置形成有p型的阱区域3,但也可以在该相交叉的位置不形成阱区域3。
在如图3及图4所示的作为高浓度的p型的区域而形成沟道电阻调整区域6a的方法中,在MOSFET的单元内局部地形成沟道电阻高的区域。例如,如图4所示,在俯视观察时将源极区域4的四周包围而在将源极区域4包围的边处间断地形成沟道电阻调整区域6a。
通过这样地形成沟道电阻调整区域6a,从而在短路时流过大电流的情况下,电流集中于除了沟道电阻调整区域6a以外的地方,电流集中的部分局部地发热,电阻变高,因此抑制流过的电流。因而,与沟道部的浓度均匀且导通电阻相同的MOSFET相比,饱和电流得到抑制,因此短路耐量提高。
另外,通过规则地且等间隔地形成载流子浓度不同的区域,从而如果作为芯片整体来看,则电流是均匀流过的,能够防止由于局部的电流集中而引起的芯片的破坏。
此外,沟道电阻高的沟道电阻调整区域6a形成于各单元的所产生的电场变大(即,电场容易集中)的角部(将源极区域4包围的角部),从而在短路时元件不易被破坏。
在图3及图4中例示了排列有四边形的单元的构造,但条带构造的单元也会产生同样的效果。
另外,在图3及图4中示出了如下构造,即,四边形的各单元之间的区域形成为格子状,在该格子的相交叉的位置形成有p型的阱区域3,但也可以在该相交叉的位置不形成阱区域3。
掺杂于沟道电阻调整区域的材料为Al或者N。关于剂量,在Al的情况下,约为大于或等于1×1012[N/cm2],优选大于或等于1×1014[N/cm2],该剂量是比阱区域3的杂质浓度高的浓度。另外,在N的情况下,约为小于或等于5×1013[N/cm2],但该剂量是比SiC外延层2的杂质浓度高的浓度。
特别地,通过使用Al离子形成高浓度的p型的沟道电阻调整区域6a,从而使得杂质的热扩散得到抑制,明确地形成高浓度的p型区域。这是因为,Al比B扩散系数小,在离子注入后的高温的活化退火处理中几乎不会进行热扩散。
由此,沟道电阻高的区域和低的区域的边界明确,电流容易局部地集中。
因此,在短路时流过大电流的情况下,电流集中于除了沟道电阻调整区域以外的地方,该部分局部地发热,电阻变高,因此抑制流过的电流。因而,与沟道部的浓度均匀且导通电阻相同的MOSFET相比,饱和电流得到抑制,短路耐量提高。
此外,在图1至图4中示出了MOSFET的例子,但如果将n+型的衬底设为p型的衬底,则成为绝缘栅双极晶体管(insulated gate bipolar transistor,IGBT),IGBT也同样会得到本发明的效果。
图5是表示本实施方式涉及的碳化硅半导体装置的变形例的构造的俯视图。图6是表示本实施方式涉及的碳化硅半导体装置的变形例的构造的剖视图。在图5及图6中示出了在条带构造的单元(阱区域3及源极区域4在俯视观察时为条带形状的单元)处作为n型的区域而形成沟道电阻调整区域6b的情况。
在如图5及图6所示的作为n型的区域而形成沟道电阻调整区域6b的方法中,在MOSFET的单元内局部地形成沟道电阻低的区域。例如,如图5所示,在俯视观察时将源极区域4包围而间断地形成沟道电阻调整区域6b。
通过这样地形成沟道电阻调整区域6b,从而降低沟道电阻。另外,在短路时流过大电流的情况下,电流集中于沟道电阻调整区域6b,电流集中的部分局部地发热,电阻变高,因此抑制流过的电流。因而,与沟道部的浓度均匀且导通电阻相同的MOSFET相比,饱和电流得到抑制,因此短路耐量提高。
此外,沟道电阻低的沟道电阻调整区域6b形成于各单元的除了所产生的电场变大的角部以外的区域,从而在短路时元件不易被破坏。
<效果>
下面,例示由本实施方式实现的效果。
根据本实施方式,碳化硅半导体装置具有:第1导电型的SiC外延层2;第2导电型的阱区域3;第1导电型的源极区域4;沟道电阻调整区域6或者沟道电阻调整区域6a;栅极电极7;层间绝缘膜9;源极电极10;以及漏极电极12。
SiC外延层2形成于SiC衬底1的上表面。阱区域3在SiC外延层2的表层局部地形成。源极区域4在阱区域3的表层局部地形成。沟道电阻调整区域6及沟道电阻调整区域6a是在阱区域3的表层被源极区域4和SiC外延层2夹着而形成的。栅极电极7在沟道电阻调整区域6或者沟道电阻调整区域6a的上表面隔着栅极绝缘膜8而形成。层间绝缘膜9形成为将栅极电极7覆盖。源极电极10形成于层间绝缘膜9的上表面以及源极区域4的上表面。漏极电极12形成于SiC衬底1的下表面。
沟道电阻调整区域6是,在与由源极区域4和SiC外延层2夹着沟道电阻调整区域6的方向相交叉的方向,间断地形成第1导电型的第1杂质区域的区域。
沟道电阻调整区域6a是,在与由源极区域4和SiC外延层2夹着沟道电阻调整区域6a的方向相交叉的方向,间断地形成第2导电型的第2杂质区域的区域。
根据这样的结构,能够一边抑制短路耐量的降低,一边降低导通电阻。即,通过在阱区域3的表层局部地形成载流子浓度不同的区域(沟道电阻调整区域6或者沟道电阻调整区域6a),从而电流会局部地集中于沟道电阻低的区域。于是,电流集中的部分局部地发热,其电阻变高,因此抑制流过的电流。因而,与沟道部的载流子浓度均匀且导通电阻相同的半导体装置相比,饱和电流得到抑制,因此短路耐量提高。
另外,沟道电阻调整区域6a的杂质浓度比阱区域3的杂质浓度高,从而各单元的角部处的电场集中得到缓和,因此能够抑制短路耐量的降低。
另外,如果沟道电阻调整区域6设置于各单元的角部,则在电场集中于各单元的角部的情况下会发生电流集中,芯片有可能会被破坏,因此必须设置于各单元的边处。
此外,除了这些结构以外的结构能够适当地进行省略,但在适当追加了本说明书所示的任意结构的情况下,也能够产生上述的效果。
<变形例>
在上述实施方式中,有时对各结构要素的材质、材料、尺寸、形状、相对配置关系或者实施条件等也进行了记载,但这些在全部的方面均为例示,本发明并不限于这里所记载的内容。因此,在本发明的范围内,可以设想出未例示的无数的变形例。包含例如将任意结构要素进行变形的情况、或者进行省略的情况。
标号的说明
1 SiC衬底,2 SiC外延层,3阱区域,4源极区域,5接触区域,6、6a、6b沟道电阻调整区域,7栅极电极,8栅极绝缘膜,9层间绝缘膜,10源极电极,11 NiSi层,12漏极电极。
Claims (6)
1.一种碳化硅半导体装置,其具有:
第1导电型的外延层(2),其形成于碳化硅半导体衬底(1)的上表面;
第2导电型的阱区域(3),其在所述外延层(2)的表层局部地形成;
第1导电型的源极区域(4),其在所述阱区域(3)的表层局部地形成;
沟道电阻调整区域(6、6a),其是在所述阱区域(3)的表层被所述源极区域(4)和所述外延层(2)夹着而形成的;
栅极电极(7),其在所述沟道电阻调整区域(6、6a)的上表面隔着栅极绝缘膜(8)而形成;
层间绝缘膜(9),其形成为将所述栅极电极(7)覆盖;
源极电极(10),其形成于所述层间绝缘膜(9)的上表面以及所述源极区域(4)的上表面;以及
漏极电极(12),其形成于所述碳化硅半导体衬底(1)的下表面,
所述沟道电阻调整区域(6、6a)是,在与由所述源极区域(4)和所述外延层(2)夹着所述沟道电阻调整区域(6、6a)的方向相交叉的方向,间断地形成第1导电型的第1杂质区域(6)、或者第2导电型的第2杂质区域(6a)的区域,
在所述沟道电阻调整区域为间断地形成所述第1杂质区域(6)的区域的情况下,所述第1杂质区域(6)的杂质浓度比所述外延层(2)的杂质浓度高,
在所述沟道电阻调整区域为间断地形成所述第2杂质区域(6a)的区域的情况下,所述第2杂质区域(6a)的杂质浓度比所述阱区域(3)的杂质浓度高。
2.根据权利要求1所述的碳化硅半导体装置,其中,
所述沟道电阻调整区域(6、6a)是在所述阱区域(3)的表层将所述源极区域(4)的四周包围而形成的,
所述沟道电阻调整区域(6、6a)是在将所述源极区域(4)包围的边处间断地形成所述第1杂质区域(6)、或者所述第2杂质区域(6a)的区域。
3.根据权利要求2所述的碳化硅半导体装置,其中,
所述第1杂质区域(6)没有形成在将所述源极区域(4)包围的角部处。
4.根据权利要求2所述的碳化硅半导体装置,其中,
所述第2杂质区域(6a)形成在将所述源极区域(4)包围的角部处。
5.根据权利要求1、3以及4中任一项所述的碳化硅半导体装置,其中,
所述第2杂质区域(6a)是通过注入Al离子而形成的。
6.根据权利要求1所述的碳化硅半导体装置,其中,
所述阱区域(3)及所述源极区域(4)在俯视观察时为条带形状。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2014/067150 WO2015198468A1 (ja) | 2014-06-27 | 2014-06-27 | 炭化珪素半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN106663693A true CN106663693A (zh) | 2017-05-10 |
CN106663693B CN106663693B (zh) | 2019-11-01 |
Family
ID=54937592
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201480080201.5A Active CN106663693B (zh) | 2014-06-27 | 2014-06-27 | 碳化硅半导体装置 |
Country Status (6)
Country | Link |
---|---|
US (1) | US9985124B2 (zh) |
JP (1) | JP6224242B2 (zh) |
KR (1) | KR101870558B1 (zh) |
CN (1) | CN106663693B (zh) |
DE (1) | DE112014006762B4 (zh) |
WO (1) | WO2015198468A1 (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111739930A (zh) * | 2020-06-30 | 2020-10-02 | 电子科技大学 | 一种抗电离辐射加固的mos栅控晶闸管 |
CN114203825A (zh) * | 2021-12-13 | 2022-03-18 | 无锡新洁能股份有限公司 | 一种垂直型碳化硅功率mosfet器件及其制造方法 |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6523887B2 (ja) * | 2015-09-11 | 2019-06-05 | 株式会社東芝 | 半導体装置 |
DE112016005685T5 (de) * | 2015-12-11 | 2018-09-20 | Rohm Co., Ltd. | Halbleiterbauteil |
CN107046059B (zh) * | 2016-02-05 | 2020-04-21 | 瀚薪科技股份有限公司 | 碳化硅半导体元件以及其制造方法 |
JP6687476B2 (ja) * | 2016-07-25 | 2020-04-22 | 株式会社日立製作所 | 半導体装置およびその製造方法 |
KR102185158B1 (ko) * | 2016-08-19 | 2020-12-01 | 로무 가부시키가이샤 | 반도체 장치 |
US10497777B2 (en) * | 2017-09-08 | 2019-12-03 | Hestia Power Inc. | Semiconductor power device |
JP7099369B2 (ja) | 2018-03-20 | 2022-07-12 | 株式会社デンソー | 半導体装置およびその製造方法 |
WO2019198167A1 (ja) * | 2018-04-11 | 2019-10-17 | 新電元工業株式会社 | 半導体装置の製造方法及び半導体装置 |
US10504995B1 (en) | 2018-08-09 | 2019-12-10 | Semiconductor Components Industries, Llc | Short-circuit performance for silicon carbide semiconductor device |
JP2022144217A (ja) * | 2021-03-18 | 2022-10-03 | 株式会社東芝 | 半導体装置、半導体装置の製造方法、インバータ回路、駆動装置、車両、及び、昇降機 |
WO2022244749A1 (ja) | 2021-05-18 | 2022-11-24 | 富士電機株式会社 | 炭化珪素半導体装置 |
CN116013905B (zh) * | 2023-03-27 | 2023-06-23 | 通威微电子有限公司 | 一种半导体器件及其制作方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59149057A (ja) * | 1983-02-15 | 1984-08-25 | Nissan Motor Co Ltd | 縦型mosトランジスタ |
US5952699A (en) * | 1996-08-23 | 1999-09-14 | Semiconductor Energy Laboratory Co., Ltd. | Insulated gate semiconductor device and method of manufacturing the same |
CN1319176C (zh) * | 2000-10-03 | 2007-05-30 | 克里公司 | 短沟道碳化硅功率mosfets及其制造方法 |
US20100314629A1 (en) * | 2008-02-12 | 2010-12-16 | Mitsubishi Electric Corporation | Silicon carbide semiconductor device |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0963983A (ja) | 1995-08-29 | 1997-03-07 | Oki Electric Ind Co Ltd | 不純物拡散領域の形成方法、拡散mosトランジスタの製造方法、ダイオードの製造方法 |
JP3027939B2 (ja) | 1996-04-19 | 2000-04-04 | 日本電気株式会社 | 縦型電界効果トランジスタおよびその製造方法 |
US6703671B1 (en) * | 1996-08-23 | 2004-03-09 | Semiconductor Energy Laboratory Co., Ltd. | Insulated gate semiconductor device and method of manufacturing the same |
DE112011101442B4 (de) | 2010-04-26 | 2022-05-12 | Mitsubishi Electric Corporation | Halbleitervorrichtung |
-
2014
- 2014-06-27 KR KR1020167036267A patent/KR101870558B1/ko active IP Right Grant
- 2014-06-27 JP JP2016528955A patent/JP6224242B2/ja active Active
- 2014-06-27 CN CN201480080201.5A patent/CN106663693B/zh active Active
- 2014-06-27 US US15/307,835 patent/US9985124B2/en active Active
- 2014-06-27 WO PCT/JP2014/067150 patent/WO2015198468A1/ja active Application Filing
- 2014-06-27 DE DE112014006762.8T patent/DE112014006762B4/de active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59149057A (ja) * | 1983-02-15 | 1984-08-25 | Nissan Motor Co Ltd | 縦型mosトランジスタ |
US5952699A (en) * | 1996-08-23 | 1999-09-14 | Semiconductor Energy Laboratory Co., Ltd. | Insulated gate semiconductor device and method of manufacturing the same |
CN1319176C (zh) * | 2000-10-03 | 2007-05-30 | 克里公司 | 短沟道碳化硅功率mosfets及其制造方法 |
US20100314629A1 (en) * | 2008-02-12 | 2010-12-16 | Mitsubishi Electric Corporation | Silicon carbide semiconductor device |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111739930A (zh) * | 2020-06-30 | 2020-10-02 | 电子科技大学 | 一种抗电离辐射加固的mos栅控晶闸管 |
CN111739930B (zh) * | 2020-06-30 | 2021-09-24 | 电子科技大学 | 一种抗电离辐射加固的mos栅控晶闸管 |
CN114203825A (zh) * | 2021-12-13 | 2022-03-18 | 无锡新洁能股份有限公司 | 一种垂直型碳化硅功率mosfet器件及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20170054017A1 (en) | 2017-02-23 |
KR20170005136A (ko) | 2017-01-11 |
US9985124B2 (en) | 2018-05-29 |
WO2015198468A1 (ja) | 2015-12-30 |
JP6224242B2 (ja) | 2017-11-01 |
DE112014006762B4 (de) | 2021-09-30 |
CN106663693B (zh) | 2019-11-01 |
DE112014006762T5 (de) | 2017-04-20 |
JPWO2015198468A1 (ja) | 2017-04-20 |
KR101870558B1 (ko) | 2018-06-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN106663693B (zh) | 碳化硅半导体装置 | |
US11177354B2 (en) | Method of manufacturing silicon carbide semiconductor devices | |
JP5641131B2 (ja) | 半導体装置およびその製造方法 | |
JP5586887B2 (ja) | 半導体装置及びその製造方法 | |
US8575622B2 (en) | Silicon carbide trench MOSFET having reduced on-resistance, increased dielectric withstand voltage, and reduced threshold voltage | |
JP6415749B2 (ja) | 炭化珪素半導体装置 | |
CN105164812B (zh) | 半导体装置以及半导体装置的制造方法 | |
JP5697744B2 (ja) | 半導体装置およびその製造方法 | |
JP6140823B2 (ja) | 炭化珪素半導体装置 | |
US9698217B1 (en) | Semiconductor device | |
JP2017112161A (ja) | 半導体装置 | |
US10068972B2 (en) | Semiconductor device with opposite conductivity-type impurity regions between source and trench gate for reducing leakage | |
JP2012089824A (ja) | 半導体素子およびその製造方法 | |
JP2008060152A (ja) | 半導体装置及びその製造方法 | |
JP5520024B2 (ja) | 半導体装置、及びその製造方法 | |
JP7119922B2 (ja) | 半導体装置の製造方法 | |
JP2007134421A (ja) | パワーmosfet、igbtなどの縦型半導体装置とその製造方法 | |
JP5784860B1 (ja) | 炭化ケイ素半導体装置 | |
CN112956004A (zh) | 半导体装置 | |
CN113140634A (zh) | 一种半导体器件及其制造方法 | |
JP2010186893A (ja) | 半導体装置 | |
JP2003046083A (ja) | 半導体装置 | |
JP2014060345A (ja) | 電力用半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |