CN1004669B - 半导体器件的制造方法 - Google Patents

半导体器件的制造方法 Download PDF

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CN1004669B
CN1004669B CN86105660.4A CN86105660A CN1004669B CN 1004669 B CN1004669 B CN 1004669B CN 86105660 A CN86105660 A CN 86105660A CN 1004669 B CN1004669 B CN 1004669B
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semiconductor
layer
corrosion
thickness
bonding
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CN86105660A (zh
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简·海斯马
西奥多勒斯·马蒂纳斯·米切尔森
简·艾伯塔斯·帕尔斯
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Koninklijke Philips NV
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Philips Gloeilampenfabrieken NV
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Abstract

一种制作至少包括一个支承体（１）和一个单晶半导体基体（６、７）的半导体器件的方法，其中的这两个基体至少是制备在减小体积抛光（镜面抛光）方法得到的平整光滑表面上的，随后在光滑表面上制备一个电隔离层（４），至少对半导体基体上的电隔离层进行赋能键合操作，两个基体（１；６，７）被清洗后，在无尘环境中相互接触，以获得坚固的机械接合面，然后至少在３５０℃进行热处理，再把半导体基体（６、７）腐蚀成一个具有介于０．０５～１００μｍ之间的预定值的薄层（７）。

Description

半导体器件的制造方法
本发明涉及一种制作至少由一个支承体和一个单晶半导体基体组成的半导体器件的方法，其中这两个基体至少由一用减小体积抛光（镜面抛光）法得到一个光学平滑的表面制备的，而半导体基体的光学平滑表面是用一个电学绝缘层制备的，在两个基体平整表面被清洗之后，在无尘环境中相互接触，达到机械连接的目的，而后，再对之进行至少为350℃的热处理。
为此目的，本发明必须获得一个在绝缘体上的半导体层（亦称SOI＝Silicon on Insulator）绝缘体上的半导体层在半导体工艺中正引起人们极大的兴趣。事实上，就SOI而论，为获得高性能的半导体器件，采用薄半导体层是很方便的。这种高性能尤其是由于：例如由外来的辐射在该层下边的支承物中产生的干扰不会影响半导体器件的工作，如果以半导体基体本身作为一个支承物，情况确实如此（SOI对辐射是不敏感的）。对于薄半导体层，也不会围绕制备在这些层上的半导体器件产生环流（封锁）。
在蓝宝石上外延生长薄硅层已是公知技术。因为蓝宝石是六方晶体结构，而硅是立方晶体结构，但是这些层几乎都存在晶体的不规则性，因此其用途是有限的。用氧离子注入到单晶硅中，获得绝缘体上的单晶硅，然后进行热处理（退火），以此得到一个二氧化硅的埋层，这亦是公知技术。实现该工艺的设备是极其复杂，而又昂贵，且该工艺对较大的表面，如直径为φ10cm的表面，也是很耗费时间的。用激光退火，把一个绝缘体上的多晶硅层转变为单晶层，这也是公知技术。该工艺也是很费时间的。在所有上述方法中，要得到一个适当尺寸的均匀同质的单晶层也是很困难的;就激光退火方法来说，所获得的均匀区域，例如只有0.01mm2。
其他再结晶方法是灯光加热和条形加热器。这两种方法均有缺点，即半导体的支承物的温度高达1100℃（或更高）。相反地，这两种方法可形成较大的单晶区域，例如1cm2，但这些区却不是无缺陷的。
在EP-136050中介绍了一种键合工艺，即公知的名为“研合”工艺。该工艺的目的，以确保键合不影响测量的方法来避免一个半导体压力转换器测出一个错误的压力。但是，该出版物的内容没有涉及在一绝缘体上获得一个半导体的方法。
本发明的目的在于提供一种半导体器件，包括在绝缘体上的一个薄半导体层，其中用比较简单的方法可获得一个均匀同质的单晶层，而且其直径很容易达到7.5cm或更大。本发明基于对下述事实的重视，研合工艺本身也可成为在一绝缘体上获得一薄半导体层的辅助方法，以及随后的特殊工艺步骤容许获得绝缘层和半导体层之间的键合是如此之好，以致在半导体工艺中所用的以下各工艺步骤当中，粘接的完好无损。
为了达到上述目的，本文开头一段述的各种方法之特征在于：在两个基体相互接触之前，至少对半导体基体上的电绝缘层施行赋能键合处理;还在于：在两个表面间建立起一个很紧密的键合，以及在于：随后将半导体基体用腐蚀方法减薄到一个预定值，介于0.05～100μm之间。
“赋能键合处理”一词应被理解为一种确保在层的表面上的许多原子变成激活键合的处理方法。由于它增加了键合点的数目，所以可以获得一个很牢的接合面。由于赋能键合处理，至少可使光学平滑表面的50%达到范德瓦尔斯（Vander Waals）键合。被腐蚀减薄的单晶半导体材料层在半导体工艺中所用的后续工艺步骤之后仍保持与支承物的绝缘层间有很牢的粘合。半导体层可用腐蚀方法减薄到一个给定值;並保持其均匀同质单晶的特性，同时其尺寸大小仍与最初的半导体基体尺寸大小相等。
为了实现集成电路，最终层厚最好应处于0.1～1μm之间。
赋能键合处理所包括一种轻表面研磨处理主要是为研平微观上的不平整度。为在此表面形成更多的键合点，一种化学腐蚀处理也是适宜的。再一个可能性是制备一层液状化学旋涂玻璃（把有机溶剂中的二氧化硅，用离心法甩成一薄层），该有机物质可在大约200℃温度下从中分解出来，並且至少在800℃的温度下，整个增密为玻璃。
所用各向同性腐蚀处理法进行腐蚀减薄操作，但是在半导体基体上已生长一层外延半导体层时，则可用电化学腐蚀处理法来完成。对后一种情况，腐蚀进程停止在非导电层上，因而用腐蚀法可减薄到任何所要求的厚度。
按照本发明的方法可很方便地用于制作二维的半导体器件。该发明还可用于AⅢ-BⅤ材料，如砷化镓制作MOSFET。本发明还提供了制作三维叠层IC的可能性。在这些叠层的IC中不但可形成电学元件，而且还可形成其他元件，如磁性元件和光学元件。下面参照附图的介绍，将对本发明的这些实施例如进一步的实施例做更详细的解释。
在附图中：
图1示出相互键合前的一个支承体和一个半导体基体。
图2示出键合后的图1的两个基体。
图3示出由图2的组合件形成的半导体薄层。
图4示出按第二实施例的相互键合前的一个支承体和一个半导体基体。
图5示出键合操作后的图4的两个基体。
图6示出由图5的组合件形成的薄层。
图7表明了在薄半导体基体内形成了隔离区的图3或图6的组合件。
图8表示在隔离区上带有热生长氧化物的图7的组合件。
图9表示在图8的组合件上又淀积了氧化物。
图10表示许多相互隔离的区取平后形成的组合件。
图11和图12表示可用AⅢ～BⅤ族材料制作MOSFET的一个实施例。
图13到17给出了形成一个三维叠层IC的各步骤。
图18表明了该叠层IC内的几种导电连线方式，其中也指出了光学元件。
图19是一种可能的寄存器的平面图，其中包括光学元件。
图1到图3表明了在绝缘支承物上获得一个薄半导体层的第一个实施例。图1示出该支承物1，它可由，例如硅，组成，以及在其上制备的二氧化硅层2。一个半导体基体3也可由硅组成，並制备了一个二氧化硅层4。这两个基体的表面在氧化之前用减小体积抛光处理法磨平和抛光。按这种处理法，至少可去掉10μm。在氧化之后，对半导体基体的氧化层4以及在该情况下还没有支承体的层2进行赋能键合操作。这是一种确保层表面的原子获得更多的键合点的操作。例如该赋能键合操作可包括表面层的轻腐蚀。另一种可能性是对表面进行修平操作，可使微观不平整度大体上平滑。再一种可能性是在该表面上旋涂一薄层液状化学玻璃，使溶剂从液状化学玻璃中挥发出来，並在800℃以上的温度下使玻璃增密。
这两个基体在无尘环境中被清洗后，把层2和层4相互接触（图2）。于是出现了被称为“研合”的一种自身粘合的作用。由于层2和层4表面的键合点是由赋能键合操作的，所以这里的粘合很牢固。至少对50%的光学平滑表面施加了范德瓦尔键合。
为了在绝缘体上获得一半导体薄层，对半导体基体3需施加腐蚀处理。在图1～3所示的实施例中，该半导体材料是均匀掺杂的，或者可以是本征的。然后用一种公知的各向同性腐蚀处理。各向同性腐蚀有许多优点，可得到一个很平滑的腐蚀表面，但对较大的表面，则几乎无法精确控制其厚度值不变。
按绝缘方法在一支承物上制备而获得的，如图3所示的薄半导体层具有连续而完整的粘合。下一步半导体工艺中用于薄半导体层5的工艺步骤不会造成这种粘合力的降低。用本发明的方法，在所获得的绝缘层上的薄半导体层5的单晶半导体材料是均匀同质的。层的横向尺寸可以等于原始材料，即半导体基体3的尺寸。因而，可在尺寸特别大的绝缘层上获得单晶半导体材料的薄层。例如，直径为7.5cm以及更大的尺寸。
在所述的实施例中，基体1和3由硅构成，但，这是不必要的。例如，半导体基体3也可以由砷化镓及其类似材料构成。不同的半导体材料的组合而成也是可以的。支承体，例如可由石英玻璃构成，也可由不同材料合成。就硅的情况而论，可简单地用热法制备其氧化层。对其他支承体材料，例如可用热解法提供二氧化硅。
图4～6大致表示了与图1～3所示的相同的工艺。但是，在此情况下的第一半导体薄层7是在半导体基体6上外延生长的。例如，半导体由重掺杂n型硅组成，而外延层可由本征硅构成。至此，包括腐蚀减薄步骤在内，此法是与图1～3所示的方法一致的。在研合和接着的热处理之后，进行电化学腐蚀步骤。重掺杂n型硅被完全腐蚀掉。腐蚀进程在外延硅层起始处自动停止。因此，图6的薄半导体层7的厚度，在此种情况下，是由在半导体基体6上外延生长层的厚度确定的。
按上法可进行高精度的腐蚀减薄步骤，针对更多的应用，该厚度介于0.05～100μm之间。当用来制作集成电路时，其厚度大多数选取在0.1～1μm之间。再如，当用于功率晶体管时，其厚度在1～20μm之间是适宜的。
图7～10表示了其他的操作，用“绝缘体上的薄硅”获得具有同一平整表面的，相互隔离的半导体区域的二维图形。
图7表示在涂上感光胶、形成掩膜、显影，及随后进行腐蚀各步骤之后，在薄半导体层内形成隔离的半导体区8的组合件。图8表示在区域8之上已经制备了热氧化层9之后的组合件。现在，已把二氧化硅层10，例如热解的二氧化硅淀积在区域8之间的空隙和区域8之上（图9）。如果本实施例中的空隙已被生长的热氧化层9完全填满，则不再需要淀积SiO2步骤来填充沟槽。按公知方法将层10整平。在此步操作中，所有的二氧化硅均被腐蚀掉，至少达到区域8的顶面。最终，形成一个元件（图10），包括一个支承物及按电绝缘要求淀积在支承物上而被留下来的二氧化硅9、10使区域8相互隔开的若干区域8，且其所有的顶面构成了一个平整的表面。现在，在每一个区域8中，可制备隔离的半导体元件，诸如二极管和三极晶体管等，这些元件的组合可构成一个集成电路。
本发明还特别适用于AⅢ～BⅤ族材料，如砷化镓，镓铝砷及其类似的材料等，形成MOSFET。用这些材料制作的MOSFET具有极大的优点，因带电载流子的迁移率高，电路能快速开关。但是，在这些材料上制备具有良好电绝缘品质的氧化层是困难的。形成氧化层的最典型的方法，即热氧化法，对AⅢ～BⅤ族材料是不可行的。尽管如此，本发明还是提供了获得MOSFET的这种良好的结构的可能方式。在图11中，支承体1由AⅢ～BⅤ族材料，如砷化镓构成。参照图1～3或图4～6所述的方法，在此用研合的方法制备一个半导体基体。在硅基体上生长一层热二氧化硅层4。用研合的方法，在砷化镓基体上已形成一层特别适于热生长二氧化硅层的4。将该薄硅层4腐蚀，以形成隔离区8a，图11和图12只显示出其中的一个区，构成MOSFET的源和漏的n型掺杂区20和21是在支承物1上形成的。
图12表示一个MOSFET的一种可能的最终结构。除去了源20和漏21表明的二氧化硅，並制备了接触电极22、23。原来为本征硅的8a，在图12的情况下，已变成为导电硅，例如用离子注入法或用硅化物。现在区域8a形成了MOSFET的栅极。
图13～17表示用所述的方法如何形成三维叠层IC。图13表示薄半导体层11，它是依照图1～3或图4～6所描述的方法制备在支承物的一层绝缘层上。例如，在硅的单晶半导体11内，形成了IC结构，而且所要求的工艺操作导致在层11上局部地形成了凸起部分。
图14表示一层二氧化硅层12，例如是用热解法淀积在硅层11上。图15表明了按公知方法整平之后，在半导体结构的层11之上面获得了具有平整表面的二氧化硅层12。例如，层12可有0.5μm的厚度。
现在，图15所示的组合件可用来作为一个支承体，在其上再按图1～3和图4～6所述的隔离法制备一薄半导体层。用层11的半导体结构形成的电路，为明确起见，指定为第一寄存器。
图16表示经过腐蚀减薄的半导体层13和电隔离层14，如二氧化硅的，层14研合在层12上。在层13内再次形成IC结构，因此其上表面呈图17所示的形状。在层13内的这些结构形成了第二寄存器。按所述的方法，薄半导体层配置在绝缘层上，形成了三维叠层IC。根据要求，在该叠层上还可增加几层寄存器。
对如图17所示的结构紧密的叠层IC，应对散热问题予以特殊的关注。强制冷却的可能性之一，在于用一个或一个以上的珀尔帖（Peltier）元件作为制冷体，至少做在一层寄存器内。当元件占有较大的空间，例如包括较大的电容时，对寄存器的封装密度是不利的。所以至少采用一层寄存器主要用于容纳这类占据较大面积的元件是值得的。
图18表示由三层寄存器组成的三维叠层IC，表明了取得各层寄存器间电连接的另一种可能性。例如，首先在要制作连线的地方形成孔，例如，用反应等离子腐蚀方法，然后用导电材料填充这些孔，而得到连线15和16。本实施例中所表示的连线15形成了第三（上）层和第二（中）层的寄存器间的电接触。连线16一直延伸到第一寄存器。
图18还表示了获得各寄存器间的电接触的另一种形式。在叠层IC的周围，可在所要求的区域形成电导体17。
图19是一种可能的寄存器的平面图，其中包括光学元件。
寄存器25包括一个激光器或一个发光二极管26，经过一个二氧化硅的光电导体27通向周围介质。通过图中所示的光导纤维28传输光能。光在弱散射、无吸收的介质中传输的优点是：大体上不存在损耗，因而也不发生热的消耗。所以，通过光传输寄存器信息是有效的。
第二种可能的情况，以图解表示于图19，一个激光器或一个发光二极管29，通过一个二氧化硅的光电导体30连接到一个探测器上，在此把光能转换成电能。
还可能把光电导体沿叠层IC的垂直方向延伸到叠层的上层，在此，信号光能可从上层传送到一个所希望的寄存器，或从一个寄存器传到外面。
二氧化硅通道，诸如通道27和30，不仅能作为一个光电导体，而且能在寄存器中的半导体元件间作为一种电绝缘体。
支承体可由非晶、多晶或单晶形式的单一材料构成。支承体也可由各层组合件组成，其中有用的一层是异质外延生长在基片上。
支承体除了起钝化电绝缘作用外，还可具有激励体的性能，如磁的性能（如在钇-铁-柘榴石）、压电性能（如在铅-锆酸盐-钛酸盐），折光性能（如在Bi12GeO20或Bi12SiO20）以及电光性能（如在铌酸锂或铌酸钾）。
支承体还有层状方式激励性能，由声学表面波产生的（例如，铌酸锂）以及产生静磁表面波的性能（例如，异质外延生长在钆-镓-柘榴石上的钇-铁-柘榴石）。
在支承体和寄存器中可含有电传导的和光传输的两种作用，如铟锡氧化物。

Claims (6)

1、一制作至少由一支承体和一单晶半导体基体组成的半导体器件的方法，其中这两个基体至少由减小体积抛光（镜面抛光）方法制备而获得一个光学平滑的表面，所述半导体基体的光学平滑表面具有一电绝缘层，在所述两个基体的平整表面被清洗之后，在无尘环境中相互接触，以达到机械联接的目的，并随后经过至少为350℃的热处理，其特征是：在所述两个基体相互接触之前的瞬间，将其需联接的镜面抛光表面施行赋能键合操作，所述操作是由轻机械表面平滑操作或轻腐蚀表面操作组成，然后在所述两表面间通过自然接触形成一很紧密的键合，随后所述半导体基体用腐蚀方法减薄到介于0.05～100μm间的一预定值。
2、一根据权利要求1所述的方法，其特征在于采用一各向同性腐蚀处理而腐蚀减薄本征或掺杂半导体基体的。
3、一根据权利要求1或2所述的方法，其特征在于：所述半导体基体含一重掺杂的支承体和一在其上外延生长的轻掺杂层，且用电化学腐蚀处理法实现腐蚀减薄操作，其中重掺杂部分被蚀刻剥除，而腐蚀进程停止于本征的或轻掺杂半导体层。
4、一根据权利要求1或2所述的方法，其特征在于：对所述半导体材料薄层进行腐蚀，以形成若干隔离区，所述隔离区之间的空隙由热氧化物封闭，或者将一隔离槽的填料淀积在所述隔离区的空隙和顶部，其厚度超过了原来的半导体材料薄层的厚度，在至少与半导体层的上表面取平之后，形成了具有半导体区的支承物，其整个上表面是一个平整的表面。
5、一根据权利要求3所述的方法，其特征在：对所述半导体材料薄层进行腐蚀，以形成若干隔离区，所述隔离区之间的空隙由热氧化物封闭，或者将一隔离槽的填料淀积在所述隔离区的空隙和顶部，其厚度超过了原来的半导体材料薄层的厚度，在至少与半导体层的上表面取平之后，形成了具有半导体区的支承物，其整个上表面是一个平整的表面。
6、一根据上述任一权利要求所述的方法，其特征在于：IC结构是制备在所述薄半导体层内的，因而表面呈现凸起部分，二氧化硅被淀积在表面上，将二氧化硅一直修平到在所述半导体结构的上面只有厚度很小的绝缘层为止，这个组合件是构成所述支承体的第一寄存器，在其上再按权利要求1所指出的方法制备一具有绝缘层的半导体基体，IC结构制成的所述薄半导体层构成一第二寄存器，并可进一步实行类似的步骤，以形成一个三维叠层IC。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11979132B2 (en) 2018-03-29 2024-05-07 Soitec Method for manufacturing a substrate for a radiofrequency filter

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JP2608548B2 (ja) 1997-05-07
CA1245776A (en) 1988-11-29
AU5885486A (en) 1986-12-24
CN86105660A (zh) 1987-02-25
DE3676367D1 (de) 1991-02-07
ES8707023A1 (es) 1987-07-01
EP0209173A1 (en) 1987-01-21
ES556144A0 (es) 1987-07-01
AU585355B2 (en) 1989-06-15
US4983251A (en) 1991-01-08
JPS61294846A (ja) 1986-12-25
NL8501773A (nl) 1987-01-16
EP0209173B1 (en) 1991-01-02

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