JP5726796B2 - 絶縁体上の半導体タイプの基板のためのベース基板を製造する方法 - Google Patents
絶縁体上の半導体タイプの基板のためのベース基板を製造する方法 Download PDFInfo
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 20
- 229910052710 silicon Inorganic materials 0.000 claims description 20
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- 238000000151 deposition Methods 0.000 claims description 8
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 239000002019 doping agent Substances 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- 239000011261 inert gas Substances 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 55
- 230000015572 biosynthetic process Effects 0.000 description 7
- 239000000356 contaminant Substances 0.000 description 7
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- 229910052786 argon Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76262—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using selective deposition of single crystal silicon, i.e. SEG techniques
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
Description
(a)500Ω.cmより大きい電気抵抗を有するシリコン基盤を提供する、
(b)基板表面に存在する、在来の酸化物および/またはドーパントを除去するために、上述の基板の表面を洗浄する、
(c)上述の基板上に、誘電材料の層を形成する、
(d)上述の層上に、多結晶シリコンの層を形成する、
上述の方法は、ステップ(b)(c)および(d)が同一のエンクロージャ内で順番に実施されることで特徴つけられる。
−シリコン基板に接触し、取り入れ、誘電体の層および多結晶シリコンの層を上に形成した基板を取り出す手段、
−外部に対して密封されるように上記接触を遮断するための、閉じる手段、
−洗浄および誘電体と多結晶シリコン層の形成の間基板を支える手段、
−それぞれのステップにおいて、雰囲気および/または基板を所望の温度に熱するための、熱する手段、
−適した組成のガスおよび/または試薬を、洗浄、酸化または誘電体の堆積、および多結晶シリコンの堆積のために導入する手段、
−方法のそれぞれのステップの最後に、余剰のガスおよび/または試薬を取り出す手段。
Claims (5)
- 絶縁体上の高抵抗半導体タイプ基板の製造のためのベース基板を製造する方法であって、
(a)500Ω.cmより大きい電気抵抗を有するシリコン基板(1)を提供するステップと、
(b)前記基板(1)の表面上に存在する在来の酸化物およびドーパントを除去するために、前記基板(1)の前記表面を洗浄するステップと、
(c)前記基板(1)上に、誘電体層(2)を形成するステップと、
(d)前記層(2)上に、多結晶シリコン層(3)を形成するステップと
を備え、ステップ(b)(c)および(d)は、同一のエンクロージャ(10)内で連続的に実施され、
ステップ(c)は酸化雰囲気内での前記基板(1)の熱処理を含み、前記誘電体は酸化シリコンであり、前記酸化雰囲気は、不活性ガスおよび酸素を含み、前記酸素の含有量は100から5000ppmの間の値を有することを特徴とする方法。 - ステップ(b)の洗浄は、還元性雰囲気内での熱処理を含むことを特徴とする請求項1に記載の方法。
- ステップ(d)は900℃以下の温度における多結晶シリコンの堆積を含むことを特徴とする請求項1または2に記載の方法。
- 前記エンクロージャ(10)は、ステップ(b)の実施のための第1チャンバ(10A)と、ステップ(c)の実施のための第2チャンバ(10B)と、ステップ(d)の実施のための第3チャンバ(10C)とを含み、前記第1、第2、および第3のチャンバは外部から隔離されて、エアロック(11A、11B)を介して接続されていることを特徴とする請求項1乃至3のいずれか1項に記載の方法。
- ステップ(d)において得られる基板(1、2、3)は、絶縁体上の半導体タイプ基板の前記製造のベース基板として使用されることを特徴とする請求項1乃至4のいずれか1項に記載の方法。
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Application Number | Priority Date | Filing Date | Title |
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FR1152353 | 2011-03-22 | ||
FR1152353A FR2973159B1 (fr) | 2011-03-22 | 2011-03-22 | Procede de fabrication d'un substrat de base |
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JP2012199550A JP2012199550A (ja) | 2012-10-18 |
JP5726796B2 true JP5726796B2 (ja) | 2015-06-03 |
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US (1) | US8765571B2 (ja) |
EP (1) | EP2503592A1 (ja) |
JP (1) | JP5726796B2 (ja) |
KR (1) | KR101379885B1 (ja) |
CN (1) | CN102693933B (ja) |
FR (1) | FR2973159B1 (ja) |
SG (1) | SG184651A1 (ja) |
TW (1) | TWI458020B (ja) |
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- 2012-03-19 KR KR1020120027527A patent/KR101379885B1/ko active IP Right Grant
- 2012-03-20 CN CN201210074558.5A patent/CN102693933B/zh active Active
- 2012-03-21 US US13/426,190 patent/US8765571B2/en active Active
- 2012-03-21 JP JP2012064056A patent/JP5726796B2/ja active Active
- 2012-03-22 EP EP12160793A patent/EP2503592A1/en not_active Withdrawn
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CN102693933B (zh) | 2016-12-14 |
TW201239990A (en) | 2012-10-01 |
US8765571B2 (en) | 2014-07-01 |
SG184651A1 (en) | 2012-10-30 |
TWI458020B (zh) | 2014-10-21 |
KR20120107863A (ko) | 2012-10-04 |
FR2973159A1 (fr) | 2012-09-28 |
EP2503592A1 (en) | 2012-09-26 |
FR2973159B1 (fr) | 2013-04-19 |
US20120244687A1 (en) | 2012-09-27 |
CN102693933A (zh) | 2012-09-26 |
JP2012199550A (ja) | 2012-10-18 |
KR101379885B1 (ko) | 2014-04-01 |
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