WO2011093473A1 - 半導体装置 - Google Patents
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- WO2011093473A1 WO2011093473A1 PCT/JP2011/051831 JP2011051831W WO2011093473A1 WO 2011093473 A1 WO2011093473 A1 WO 2011093473A1 JP 2011051831 W JP2011051831 W JP 2011051831W WO 2011093473 A1 WO2011093473 A1 WO 2011093473A1
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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Definitions
- the present invention relates to a semiconductor device.
- a semiconductor device is classified into a horizontal element in which electrodes are formed on one side of a semiconductor substrate and a vertical element having electrodes on both sides of a semiconductor substrate.
- the direction in which the drift current flows in the on state and the direction in which the depletion layer due to the reverse bias voltage extends in the off state are the same.
- MOSFET Metal Oxide Field Effect Transistor: MOS type field effect transistor
- the portion of the high resistance n ⁇ drift layer has a drift current in the vertical direction when it is in the ON state. It works as an area to flow. Therefore, if the current path of the n ⁇ drift layer is shortened, the drift resistance is lowered, so that an effect that the substantial on-resistance of the MOSFET can be lowered is obtained.
- the portion of the high resistance n ⁇ drift layer is depleted in the off state to increase the breakdown voltage. Therefore, when the n ⁇ drift layer is thinned, the width of the drain-base depletion layer extending from the pn junction between the p base region and the n ⁇ drift layer becomes narrow, and the breakdown voltage decreases. On the contrary, in a semiconductor device with a high breakdown voltage, since the n ⁇ drift layer is thick, the on-resistance is increased and the conduction loss is increased. Thus, there is a trade-off relationship between on-resistance and breakdown voltage.
- FIG. 39 is a cross-sectional view showing a conventional superjunction semiconductor device.
- the superjunction in which the drift layer is a parallel pn layer 120 in which the n-type region 101 and the p-type region 102 with increased impurity concentration are alternately and repeatedly joined is used.
- SJ Semiconductor devices are known.
- the element active portion includes a p base region 103, an n-type surface region 104, a p + contact region 105, an n + source region 106, a gate insulating film 107, a gate electrode 108, an interlayer insulating film 109 and a source as the surface structure of the element.
- An electrode 110 is provided.
- a drain electrode 112 in contact with the n + drain region 111 is provided on the second main surface (see, for example, Patent Document 1, Patent Document 2, and Patent Document 3 below).
- the parallel pn layer 120 is provided between the surface structure of the element and the n + drain region 111.
- FIG. 40 is a characteristic diagram showing an impurity concentration distribution of the superjunction semiconductor device shown in FIG.
- FIG. 40 shows an n-type impurity concentration distribution (cutting) from the end (hereinafter referred to as the upper end) of the n-type surface region 104 on the first main surface side to the second main surface side (hereinafter referred to as the depth direction).
- a line AA-AA ′) and a p-type impurity concentration distribution (cut line BB-BB ′) in the depth direction from the upper end of the p + contact region 105 are shown.
- the first depth d 0 is the depth from the upper end of the p base region 103 to the end portion (hereinafter referred to as the lower end) of the p base region 103 on the second main surface side.
- the second depth d 10 is a depth from the lower end of the p base region 103 to the lower end of the p-type region 102.
- the impurity concentrations of the n-type region 101 and the p-type region 102 are uniform in the depth direction.
- the depletion layer spreads laterally from each pn junction extending in the vertical direction of the parallel pn layer in the off state, and the entire drift layer Therefore, a high breakdown voltage can be achieved.
- the following devices have been proposed as another super-junction semiconductor device that has improved breakdown voltage and reduced on-resistance.
- On the n + -type drain layer there is a super junction structure in which the first n-type pillar layer, the p-type pillar layer, and the second n-type pillar layer are alternately arranged.
- the p-type pillar layer and the second n-type pillar layer have a higher impurity concentration on the source electrode side than on the drain electrode side (see, for example, Patent Document 4 below).
- the carrier concentration in the upper region of the first to third semiconductor pillar layers is set higher than the carrier concentration in the lower region (see, for example, Patent Document 5 below).
- n-type drift regions and p-type partition regions are alternately arranged on the n + drain region, and a p base region is formed on the p-type partition region, and the surface of the p base region
- An n + source region and a p + contact region are selectively formed in the layer.
- a surface n-type drift region having a high impurity concentration is formed above the n-type drift region.
- a gate electrode is provided on the surface of the p base region sandwiched between the surface n-type drift region and the n + source region via a gate insulating film.
- a source electrode is provided in common contact with the surfaces of the n + source region and the p + contact region, and a drain electrode is provided in contact with the back surface of the n + drain region.
- An insulating film is provided to insulate the gate electrode from the source electrode (see, for example, Patent Document 6 below).
- a vertical power MOSFET a) a drain contact provided on one surface of the MOSFET, comprising a first conductivity type highly doped substrate on the drain contact; b) A blocking layer provided on the substrate opposite the drain contact, wherein i) each of the first plurality of vertical sections is a parallelepiped having six rectangular faces, A plurality of first vertical sections having a horizontal thickness shorter than a thickness in a direction, wherein ii) a P conductivity type vertical section and an N conductivity type vertical section are alternately arranged; A blocking layer comprising a plurality of vertical sections, and c) opposite to the first conductivity type provided on one surface of the blocking layer opposite the substrate A second plurality of well regions of the second conductivity type; and d) a third plurality of highly doped source regions of the first conductivity type, two of the source regions being the second A third plurality of highly doped source regions disposed in each of the plurality of well regions; and e) the first conductivity type
- a fourth plurality of regions of the first conductivity type each of the regions extending between two well regions of the second plurality of well regions, and f )
- a fifth plurality of gate poly regions each of the gate poly regions covering one source region in each of two adjacent well regions and one of the fourth plurality of regions.
- a plurality of gate poly regions (for example, the following patent documents) 7 reference.).
- the first semiconductor layer has a distribution in which an impurity concentration increases in a vertical direction from the second main electrode toward the first main electrode, and the second semiconductor layer includes the second main electrode.
- the impurity concentration is constant in the vertical direction from 1 to the first main electrode (see, for example, Patent Document 8 below).
- the following device has been proposed.
- the impurity concentration of the second conductivity type region on the first main surface side is greater than the impurity concentration of the adjacent first conductivity type region.
- the impurity concentration of the second conductivity type region on the second main surface side is higher than the impurity concentration of the adjacent first conductivity type region.
- the impurity concentration of the second conductivity type region is uniform in the thickness direction, and the impurity concentration of the first conductivity type region on the first main surface side is the impurity concentration of the first conductivity type region on the second main surface side. It is lower (for example, see Patent Document 9 below).
- the apparatus has a first conductivity type second semiconductor layer and a second conductivity type third semiconductor layer alternately disposed on the first conductivity type first semiconductor layer.
- the device further includes a second conductivity type fourth semiconductor layer disposed in contact with the upper portion of the third semiconductor layer between the second semiconductor layers, and a first conductivity type formed on a surface of the fourth semiconductor layer, respectively.
- a fifth semiconductor layer disposed in contact with the upper portion of the third semiconductor layer between the second semiconductor layers, and a first conductivity type formed on a surface of the fourth semiconductor layer, respectively.
- a fifth semiconductor layer is provided.
- the first semiconductor layer has a lower concentration of impurities of the first conductivity type than the second semiconductor layer.
- the third semiconductor layer includes a basic portion and a high impurity amount portion locally formed so that the impurity amount is larger than the basic portion in the depth direction (see, for example, Patent Document 10 below).
- the power MOSFET Since the power MOSFET is used as a switching device, it is required to reduce the switching loss that occurs during switching, in addition to reducing the conduction loss that occurs in the on state.
- turn-off loss can be cited.
- the time change rate of the drain voltage at the time of turn-off hereinafter referred to as turn-off dv / dt
- turn-off dv / dt the time change rate of the drain voltage at the time of turn-off
- increasing the turn-off dv / dt causes noise. For this reason, it is desirable that the turn-off dv / dt is low.
- there is a trade-off relationship between turn-off loss and turn-off dv / dt there is a trade-off relationship between turn-off loss and turn-off dv / dt.
- the depletion layer completely spreads in the parallel pn layer with a drain voltage as low as about 50 to 100V.
- the gate-drain capacitance becomes extremely low, and the turn-off dv / dt becomes high.
- the turn-off dv / dt can be lowered by using the gate resistance, it is necessary to use a larger gate resistance than that of the conventional MOSFET because the SJ-MOSFET has a very small gate-drain capacitance.
- the gate resistance is increased, the mirror period becomes longer and the turn-off loss increases.
- FIG. 41 is a characteristic diagram showing electrical characteristics at turn-off in a conventional superjunction semiconductor device.
- FIG. 41 is a simulation result showing a trade-off relationship between the turn-off loss and the turn-off dv / dt.
- the turn-off loss of the conventional SJ-MOSFET is about 0.5 mJ.
- the turn-off loss of the conventional MOSFET is about 0.1 mJ.
- the trade-off relationship between the turn-off loss and the turn-off dv / dt is deteriorated by about 5 times as compared with the conventional semiconductor device. For this reason, for example, even if the on-resistance can be reduced to about 1/5, the effect is impaired.
- the trade-off relationship between on-resistance and breakdown voltage can be improved, but the trade-off relationship between turn-off loss and turn-off dv / dt is deteriorated.
- the drain voltage decreases when the current flowing between the drain and the source increases. That is, a negative resistance is generated when the avalanche enters, and the avalanche resistance is reduced.
- An object of the present invention is to provide a semiconductor device that improves the trade-off relationship between the turn-off loss and the turn-off dv / dt in order to eliminate the above-described problems caused by the prior art. It is another object of the present invention to provide a semiconductor device that improves avalanche resistance.
- the semiconductor device has the following characteristics.
- An element active portion provided on the first main surface side, a low resistance layer provided on the second main surface side, and provided between the element active portion and the low resistance layer;
- a base region provided on the first main surface side of the first conductivity type region, located closer to the second main surface side than an end of the second conductivity type base region on the second main surface side;
- a first conductivity type high concentration region having an impurity concentration higher than the impurity concentration on the second main surface side of the first conductivity type region.
- the semiconductor device is the semiconductor device according to the first aspect, wherein the first conductivity type high concentration region is from an end of the second conductivity type base region on the second main surface side.
- the first conductivity type region located at a depth to the end on the second main surface side of the second conductivity type region, 1.2 times to 3 times the region excluding the first conductivity type high concentration region. It has the following impurity concentration.
- a semiconductor device is the semiconductor device according to the first aspect, wherein the semiconductor device is provided on the first main surface side of the first conductivity type region, and the first conductivity type high concentration region is the first device. It is further characterized by further comprising a first conductivity type surface region in contact with the end portion on the one main surface side.
- the first conductivity type surface region has the same depth as the second conductivity type base region, or the second conductivity type base. It is provided shallower on the first main surface side than the region.
- the first conductivity type surface region has a higher impurity concentration than the first conductivity type high concentration region. To do.
- the semiconductor device is the semiconductor device according to the third aspect, wherein the first conductive type high concentration region includes the first conductive type surface region and the second conductive type base region.
- the first conductivity type high concentration region is The impurity concentration is 1.2 to 3 times that of the excluded region.
- the semiconductor device according to a seventh aspect of the present invention is the semiconductor device according to the first aspect, wherein the first conductivity type high-concentration region is from an end of the second conductivity type base region on the second main surface side.
- the second conductivity type region has a thickness of 1/3 or less of the thickness of the first conductivity type region located at a depth to the end on the second main surface side of the second conductivity type region.
- the semiconductor device is the semiconductor device according to the first aspect, wherein the first conductivity type high-concentration region is from an end of the second conductivity type base region on the second main surface side.
- the second conductivity type region has a thickness not less than 1/8 and not more than 1/4 of the thickness of the first conductivity type region located at a depth to the end on the second main surface side of the second conductivity type region. .
- the semiconductor device according to claim 9 is the semiconductor device according to claim 1, wherein the first conductivity type high concentration region is adjacent to the first conductivity type high concentration region in the second conductivity type region.
- the impurity concentration is 1.2 times or more and 3 times or less that of the region to be formed.
- a semiconductor device is the semiconductor device according to the first aspect, wherein the first conductivity having a higher impurity concentration than the impurity concentration on the second main surface side in the second conductivity type region.
- a second conductivity type high concentration region on the main surface side is further provided.
- the semiconductor device according to an eleventh aspect of the present invention is the semiconductor device according to the tenth aspect, wherein the first conductivity type high-concentration region is from an end of the second conductivity type base region on the second main surface side.
- the first conductivity type region located at a depth to the end on the second main surface side of the second conductivity type region 1.5 times or more and 3 times the region excluding the first conductivity type high concentration region. It has the following impurity concentration.
- the semiconductor device according to a twelfth aspect of the present invention is the semiconductor device according to the tenth aspect, wherein the second conductivity type high-concentration region is ⁇ or more and 1 ⁇ 2 or less of the thickness of the second conductivity type region. It has the thickness of.
- a semiconductor device is the semiconductor device according to the tenth aspect, wherein the second conductivity type high concentration region has the same thickness as the first conductivity type high concentration region. To do.
- the semiconductor device according to a fourteenth aspect of the present invention is the semiconductor device according to the tenth aspect of the present invention, wherein a region excluding the second conductive type high concentration region in the second conductive type region is the first conductive type region.
- the impurity amount is the same as that of the region excluding the first conductivity type high concentration region.
- the region of the second conductivity type region excluding the second conductivity type high concentration region is from the first main surface side.
- the impurity concentration is gradually lowered toward the second main surface side.
- the first conductive type high concentration region and the second conductive type high concentration region are formed on the first main surface side from the first main surface side. 2
- the impurity concentration is gradually lowered toward the principal surface side.
- the semiconductor device according to claim 17 is the semiconductor device according to claim 10, wherein the second conductivity type high concentration region is an end portion of the first conductivity type high concentration region on the second main surface side. It is characterized by being provided deeper on the second main surface side.
- an end of the first conductive type high concentration region on the second main surface side in the second conductive type high concentration region in the semiconductor device according to the seventeenth aspect, an end of the first conductive type high concentration region on the second main surface side in the second conductive type high concentration region.
- the region provided deeper on the second main surface side than the portion has a higher impurity concentration than the first conductivity type region adjacent to the region, and is lower than the second conductivity type high concentration region. It has an impurity concentration.
- an end of the first conductive type high concentration region on the second main surface side in the second conductive type high concentration region in the semiconductor device according to the seventeenth aspect, an end of the first conductive type high concentration region on the second main surface side in the second conductive type high concentration region.
- the region provided deeper on the second main surface side than the portion has an impurity concentration of 1.2 times or more that of the first conductivity type region adjacent to the region.
- a semiconductor device is the semiconductor device according to any one of the first to twentieth aspects, wherein the planar shape of the first conductivity type region and the second conductivity type region is a stripe shape, It is a hexagonal lattice shape or a square shape.
- the first main surface side of the first conductivity type region is more than the second main surface side.
- the n-type impurity amount is large. This makes it difficult for the depletion layer to expand on the first main surface side of the parallel pn layer, and prevents the parallel pn layer from being completely depleted with a low drain voltage. Therefore, the gate / drain capacitance can be prevented from becoming extremely low, and the turn-off dv / dt can be prevented from becoming high. Accordingly, since it is not necessary to increase the gate resistance in order to reduce the turn-off dv / dt, it is possible to prevent an increase in turn-off loss.
- the first main surface of the parallel pn layer is provided.
- the p-type impurity amount on the side is larger than the n-type impurity amount.
- the semiconductor device according to the present invention has an effect that the trade-off relationship between the turn-off loss and the turn-off dv / dt can be improved. In addition, the avalanche resistance can be improved.
- FIG. 1 is a cross-sectional view of the semiconductor device according to the first embodiment.
- FIG. 2 is a characteristic diagram showing an impurity concentration distribution of the semiconductor device according to the first embodiment.
- FIG. 3 is a sectional view of the semiconductor device according to the second embodiment.
- FIG. 4 is a sectional view of the semiconductor device according to the third embodiment.
- FIG. 5 is a characteristic diagram showing the impurity concentration distribution of the semiconductor device according to the third embodiment.
- FIG. 6 is a cross-sectional view of the semiconductor device according to the fourth embodiment.
- FIG. 7 is a characteristic diagram showing an impurity concentration distribution of the semiconductor device according to the fourth embodiment.
- FIG. 8 is a cross-sectional view of the semiconductor device according to the fifth embodiment.
- FIG. 9 is a characteristic diagram showing an impurity concentration distribution of the semiconductor device according to the fifth embodiment.
- FIG. 10 is a cross-sectional view of the semiconductor device according to the sixth embodiment.
- FIG. 11 is a characteristic diagram showing the impurity concentration distribution of the semiconductor device according to the sixth embodiment.
- 12 is a characteristic diagram showing electrical characteristics at turn-off in the semiconductor device of Example 1.
- FIG. 13 is a characteristic diagram illustrating an n-type impurity concentration distribution of the semiconductor device according to the second embodiment.
- FIG. 14 is a characteristic diagram showing electrical characteristics at turn-off in the semiconductor device of Example 2.
- FIG. 15 is a conceptual diagram illustrating the expansion of the depletion layer of the semiconductor device according to the second embodiment.
- FIG. 16 is a conceptual diagram illustrating the expansion of the depletion layer of the semiconductor device according to the second embodiment.
- FIG. 17 is a conceptual diagram illustrating the expansion of the depletion layer of the semiconductor device according to the second embodiment.
- FIG. 18 is a characteristic diagram showing electrical characteristics at turn-off in the semiconductor device according to Example 2.
- FIG. 19 is a characteristic diagram illustrating a relationship between breakdown voltage and on-resistance in the semiconductor device according to the third example.
- FIG. 20 is a characteristic diagram illustrating electrical characteristics of the semiconductor device according to the fourth example.
- FIG. 21 is a characteristic diagram showing electrical characteristics at turn-off in the semiconductor device according to Working Example 4.
- FIG. 22 is a characteristic diagram showing the p-type impurity concentration distribution of the semiconductor device according to Working Example 5.
- FIG. 23 is a characteristic diagram illustrating electrical characteristics of the semiconductor device according to the fifth example.
- FIG. 24 is a characteristic diagram showing electrical characteristics at turn-off in the semiconductor device according to Working Example 5.
- FIG. 25 is a characteristic diagram showing the impurity concentration distribution of the semiconductor device according to Working Example 6.
- FIG. 26 is a characteristic diagram illustrating electrical characteristics of the semiconductor device according to the sixth example.
- FIG. 27A is a characteristic diagram of an electrical characteristic when the semiconductor device according to Example 6 is turned off.
- FIG. 27-2 is a characteristic diagram illustrating electrical characteristics at the time of turn-off of the semiconductor device according to Example 6.
- FIG. 28A is a characteristic diagram of an electrical characteristic of the semiconductor device according to the seventh embodiment.
- FIG. 28-2 is a characteristic diagram illustrating electrical characteristics of the semiconductor device according to the seventh example.
- FIG. 29A is a characteristic diagram illustrating an electrical characteristic when the semiconductor device according to Working Example 7 is turned off.
- FIG. 29-2 is a characteristic diagram illustrating electrical characteristics during turn-off of the semiconductor device according to the seventh embodiment.
- FIG. 30 is a characteristic diagram showing electrical characteristics at turn-off in the semiconductor device according to Working Example 8.
- FIG. 31 is a cross-sectional view illustrating the semiconductor device manufacturing process (No. 1) according to the seventh embodiment.
- FIG. 32 is a cross-sectional view illustrating the manufacturing process (No. 2) of the semiconductor device according to the seventh embodiment.
- FIG. 33 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the eighth embodiment.
- FIG. 34 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the ninth embodiment.
- FIG. 35 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the tenth embodiment.
- FIG. 36 is a cross-sectional view illustrating the semiconductor device manufacturing process (No. 1) according to the eleventh embodiment.
- FIG. 37 is a cross-sectional view illustrating the semiconductor device manufacturing process (No. 2) according to the eleventh embodiment.
- FIG. 38 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the twelfth embodiment.
- FIG. 39 is a cross-sectional view showing a conventional superjunction semiconductor device.
- FIG. 40 is a characteristic diagram showing an impurity concentration distribution of the superjunction semiconductor device shown in FIG.
- FIG. 41 is a characteristic diagram showing electrical characteristics during turn-off in a conventional superjunction semiconductor device.
- FIG. 1 is a cross-sectional view of the semiconductor device according to the first embodiment.
- the semiconductor device shown in FIG. 1 has an element active portion on the first main surface side and an n + drain region (low resistance layer) 11 on the second main surface side.
- the element active portion includes, for example, a p-type base region (second conductivity type base region) 3, an n-type surface region (first conductivity type surface region) 4, a p + contact region 5, n + as a planar MOSFET surface structure.
- a source region 6, a gate insulating film 7, a gate electrode 8, an interlayer insulating film 9, and a source electrode 10 are provided.
- a drain electrode 12 in contact with the n + drain region 11 is provided on the second main surface.
- a parallel pn layer 20 is provided as a drift layer between the element active portion and the n + drain region 11.
- the parallel pn layer 20 is formed by alternately and repeatedly joining n-type regions (first conductivity type regions) 1 and p-type regions (second conductivity type regions) 2.
- the p-type region 2 is provided so as not to reach the n + drain region 11.
- the planar shape of the n-type region 1 and the p-type region 2 is a stripe shape, a hexagonal lattice shape, or a square shape.
- the p base region 3 is provided on the first main surface side of the p-type region 2.
- the p base region 3 has a higher impurity concentration than the p type region 2.
- the n-type surface region 4 is provided on the first main surface side of the n-type region 1. That is, the n-type surface region 4 is provided between the adjacent p base regions 3 and is adjacent to the p base region 3.
- the n-type surface region 4 may have a higher impurity concentration than an n-type high concentration region 21 described later, or may have the same impurity concentration.
- the n-type surface region 4 may be provided at the same depth as the p base region 3 or may be provided shallower than the p base region 3.
- the impurity concentration in the vicinity of the corner on the second main surface side of the p base region 3 is the same as the impurity concentration on the first main surface side of the p type region 2. Impurity concentration can be achieved. Thereby, it is possible to prevent the electric field from concentrating near the corner on the second main surface side of the p base region 3 and to prevent the breakdown voltage from being reduced.
- the p + contact region 5 and the n + source region 6 are provided in the surface layer of the p base region 3 and are in contact with each other.
- the gate electrode 8 straddles the n + source region 6, the p base region 3, and the n-type region 1 through the gate insulating film 7.
- Source electrode 10 is in contact with p + contact region 5 and n + source region 6.
- the source electrode 10 is insulated from the gate electrode 8 by the interlayer insulating film 9.
- the n-type high concentration region (first conductivity type high concentration region) 21 is provided on the first main surface side of the n-type region 1.
- the n-type high concentration region 21 is in contact with the end (hereinafter referred to as the lower end) of the n-type surface region 4 on the second main surface side.
- the n-type high concentration region 21 is a region excluding the n-type high concentration region 21 in the n-type region 1 located at a depth from the lower end of the p base region 3 to the lower end of the p-type region 2 (hereinafter referred to as n
- the impurity concentration is higher than that of the low-density region 22.
- the n-type high concentration region 21 is a thickness of the n-type region 1 located at a depth from the lower end of the p base region 3 to the lower end of the p-type region 2 (hereinafter, the p-type region of the n-type region 1).
- the n-type high concentration region 21 may have a thickness of 1/8 to 1/4 of the thickness of the n-type region 1 adjacent to the p-type region 2.
- the thickness of the n-type high concentration region 21 may be, for example, 5.5 ⁇ m.
- the thickness of the p-type region 2 may be 40 ⁇ m, for example.
- the thickness of the region adjacent to the p-type region 2 in the n-type region 1 is, for example, 40 ⁇ m.
- FIG. 2 is a characteristic diagram showing an impurity concentration distribution of the semiconductor device according to the first embodiment.
- FIG. 2 shows an n-type impurity concentration distribution along the cutting line AA ′ in FIG. 1 and a p-type impurity concentration distribution along the cutting line BB ′ in FIG.
- the n-type impurity concentration distribution is such that the n-type region 1 in the n-type surface region 4 from the end on the first main surface side (hereinafter referred to as the upper end) to the second main surface side direction (hereinafter referred to as the depth direction).
- the p-type impurity concentration distribution is an impurity concentration distribution of the p-type region 2 in the depth direction from the upper end of the p + contact region 5 (hereinafter the same as in the second to sixth embodiments).
- the first depth d 0 is the depth from the upper end to the lower end of the p base region 3.
- the second depth d 1 is the depth from the lower end of the p base region 3 to the lower end of the n-type high concentration region 21.
- the third depth d 2 is a depth from the lower end of the n-type high concentration region 21 to the lower end of the p-type region 2.
- the n-type impurity concentration distribution shown in FIG. 2 has an n-type high concentration region 21 (second depth d 1 ) and a p-type base region 3 (first depth d 0 ) extending from the lower end to the second main surface side.
- the n-type low concentration region 22 shows the impurity concentration distribution in which this exists.
- the p-type impurity concentration distribution shown in FIG. 2 is an impurity in which the p-type region 2 (second depth d 1 + third depth d 2 ) exists from the lower end of the p base region 3 to the second main surface side. The concentration distribution is shown.
- the n-type region 1 is a region on the second main surface side from the lower end of the p base region 3, and includes two different stages of impurities composed of an n-type high concentration region 21 and an n-type low concentration region 22. It has a concentration distribution.
- the n-type high concentration region 21 may have an impurity concentration that is 1.2 to 3 times, preferably 2.5 times or less, that of the n-type low concentration region 22. That is, the n-type region 1 is configured to have a large amount of n-type impurities on the first main surface side.
- the impurity concentration of the n-type high concentration region 21 may be, for example, 4.8 ⁇ 10 15 / cm 3 .
- the impurity concentration of the n-type low concentration region 22 may be, for example, 3.0 ⁇ 10 15 / cm 3 .
- the n-type region 1 may have different three-stage impurity concentration distributions including the n-type surface region 4, the n-type high concentration region 21, and the n-type low concentration region 22. That is, in the n-type impurity concentration distribution shown in FIG. 2, the n-type surface region 4 (first depth d 0 ), the n-type high concentration region 21 (second depth) from the first main surface side to the second main surface side. , D 1 ) and the n-type low concentration region 22 (third depth d 2 ) may be a three-stage impurity concentration distribution in this order.
- the n-type high concentration region 21 including the n-type surface region 4 has an impurity concentration that is 1.2 to 3 times, preferably 2.5 times or less, that of the n-type low concentration region 22. Also good.
- the p-type region 2 has a uniform impurity concentration distribution. That is, the impurity concentration of the n-type high concentration region 21 has an impurity concentration of 1.2 times to 3 times, preferably 2.5 times or less that of the p-type region 2 adjacent to the n-type high concentration region 21. .
- the first main surface side of the n-type region 1 is set to the second main surface side.
- the n-type impurity amount is larger than that on the main surface side.
- FIG. 3 is a sectional view of the semiconductor device according to the second embodiment.
- a trench structure may be applied.
- a trench structure in which a gate electrode 18 is provided inside the trench via a gate insulating film 17 is formed on the upper end side of the n-type region 1.
- P base region 3 and n + source region 6 are in contact with gate insulating film 17 provided on the sidewall of the trench.
- the source electrode 10 is insulated from the gate electrode 18 by the interlayer insulating film 19. No n-type surface region is provided.
- the n-type impurity concentration distribution in the n-type region 1 at the cutting line CC ′ in FIG. 3 is the same as the n-type impurity concentration distribution in the n-type region 1 at the cutting line AA ′ in the first embodiment (FIG. 1, see FIG. In the semiconductor device shown in FIG. 3, since the n-type surface region is not provided, the n-type impurity concentration distribution is only the second depth d 1 and the third depth d 2 . Further, the p-type impurity concentration distribution of the p-type region 2 in the cutting line DD ′ is the same as the p-type impurity concentration distribution of the p-type region 2 in the cutting line BB ′ of the first embodiment. Other configurations are the same as those in the first embodiment.
- the same effect as that of the first embodiment can be obtained even in the semiconductor device having the trench gate structure.
- FIG. 4 is a sectional view of the semiconductor device according to the third embodiment.
- FIG. 4 shows only one pn junction in the parallel pn layer 20 (hereinafter the same applies to FIGS. 6 and 8).
- the impurity concentration on the first main surface side of p-type region 2 may be higher than the impurity concentration on the second main surface side of p-type region 2.
- the p-type high concentration region (second conductivity type high concentration region) 23 is provided on the first main surface side of the p-type region 2.
- the p-type high concentration region 23 is in contact with the lower end of the p base region 3.
- the p-type high concentration region 23 has a higher impurity concentration than a region (hereinafter referred to as a p-type low concentration region) 24 excluding the p-type high concentration region 23 in the p-type region 2.
- the p-type high concentration region 23 has the same thickness as the n-type high concentration region 21. Desirably, the p-type high concentration region 23 has a thickness of 1/8 or more and 1/2 or less of the thickness of the p-type region 2. The thickness of the p-type high concentration region 23 may be 11 ⁇ m, for example. The thickness of the p-type region 2 may be 37 ⁇ m, for example.
- the n-type high concentration region 21 desirably has an impurity concentration that is 1.5 times or more and 3 times or less, preferably 2.5 times or less that of the n-type low concentration region 22.
- FIG. 5 is a characteristic diagram showing the impurity concentration distribution of the semiconductor device according to the third embodiment.
- FIG. 5 shows the n-type impurity concentration distribution at the cutting line EE ′ in FIG. 4 from the lower end of the first depth d 0 to the second main surface side, and the p-type at the cutting line FF ′ in FIG. An impurity concentration distribution is shown.
- the n-type impurity concentration distribution of the n-type region 1 at the cutting line EE ′ is the same as that in the first embodiment (see FIG. 2).
- the p-type region 2 has two different impurity concentration distributions composed of a p-type high concentration region 23 and a p-type low concentration region 24. That is, the p-type region 2 is configured to have a large amount of p-type impurities on the first main surface side.
- the p-type high concentration region 23 has substantially the same impurity concentration at substantially the same depth as the n-type high concentration region 21.
- the p-type low concentration region 24 has substantially the same impurity concentration at substantially the same depth as the n-type low concentration region 22. That is, the p-type impurity concentration distribution in the p-type region 2 has the same distribution shape as the n-type impurity concentration distribution in the n-type region 1.
- the impurity concentration of the p-type high concentration region 23 may be 4.7 ⁇ 10 15 / cm 3 , for example.
- the impurity concentration of the p-type low concentration region 24 may be, for example, 2.7 ⁇ 10 15 / cm 3 .
- Other configurations are the same as those in the first embodiment.
- the same effect as in the first embodiment can be obtained. Further, by providing the p-type high concentration region 23 on the first main surface side of the p-type region 2, the first main surface side of the p-type region 2 has a larger amount of p-type impurities than the second main surface side. Yes. Further, the p-type high concentration region 23 is provided with substantially the same depth as that of the n-type high concentration region 21 and substantially the same impurity concentration as that of the n-type high concentration region 21. For this reason, it is possible to avoid charge imbalance at the joint surface of the parallel pn layer 20 on the first main surface side. Thereby, it can prevent that a proof pressure falls.
- FIG. 6 is a cross-sectional view of the semiconductor device according to the fourth embodiment.
- the p-type high concentration region 23 may be provided deeper on the second main surface side than the lower end of the n-type high concentration region 21.
- the p-type high concentration region 23 has the same impurity concentration as that of the n-type high concentration region 21 and is provided deeper on the second main surface side than the lower end of the n-type high concentration region 21. Therefore, the p-type impurity amount on the first main surface side can be made larger than the n-type impurity amount by the difference between the thickness of the p-type high concentration region 23 and the thickness of the n-type high concentration region 21.
- the thickness of the n-type high concentration region 21 may be 9 ⁇ m, for example.
- the thickness of the p-type high concentration region 23 may be 16 ⁇ m, for example.
- the thickness of the p-type region 2 may be 37 ⁇ m, for example.
- FIG. 7 is a characteristic diagram showing an impurity concentration distribution of the semiconductor device according to the fourth embodiment.
- FIG. 7 shows the n-type impurity concentration distribution at the cutting line GG ′ in FIG. 6 from the lower end of the first depth d 0 to the second main surface side, and the p-type at the cutting line HH ′ in FIG. The impurity concentration distribution is shown.
- the n-type impurity concentration distribution of the n-type region 1 at the cutting line GG ′ is the same as that in the first embodiment (see FIG. 2).
- the fourth depth d 3 is a depth from the lower end of the n-type high concentration region 21 to the lower end of the p-type high concentration region 23.
- the fifth depth d 4 is a depth from the lower end of the p-type high concentration region 23 to the lower end of the p-type region 2.
- the p-type region 2 has a p-type high concentration region 23 (second depth d 1 + fourth depth) provided deep from the lower end of the n-type high concentration region 21 by the fourth depth d 3.
- a is a d 3
- the impurity concentration distribution of the p-type low concentration region 24 (the fifth depth d 4) consisting of different two stages. That is, the p-type impurity concentration distribution in the p-type region 2 has a different distribution shape from the n-type impurity concentration distribution in the n-type region 1.
- the impurity concentration of the p-type high concentration region 23 may be, for example, 5.0 ⁇ 10 15 / cm 3 .
- the impurity concentration of the p-type low concentration region 24 may be, for example, 3.0 ⁇ 10 15 / cm 3 .
- the p-type high concentration region 23 has substantially the same impurity concentration as the n-type high concentration region 21.
- the p-type low concentration region 24 has substantially the same impurity concentration as the n-type low concentration region 22.
- Other configurations are the same as those in the third embodiment.
- the same effect as in the third embodiment can be obtained. Further, by providing the p-type high concentration region 23 deeper than the n-type high concentration region 21 on the second main surface side, the p-type impurity amount on the first main surface side of the parallel pn layer 20 is larger than the n-type impurity amount. The structure is also increased. Thereby, it is possible to make it difficult for negative resistance during avalanche to occur, and to improve avalanche resistance. Therefore, it is possible to prevent the drain voltage from decreasing when the current flowing between the drain and the source increases.
- FIG. 8 is a cross-sectional view of the semiconductor device according to the fifth embodiment.
- a region of the p-type high concentration region 23 that is provided deeper on the second main surface side than the lower end of the n-type high concentration region 21 is the first main region than the lower end of the n-type high concentration region 21.
- the impurity concentration may be lower than that of the p-type high concentration region 23 on the surface side.
- the impurity concentration between the p-type high concentration region 23 and the p-type low concentration region 24 is lower than that of the p-type high concentration region 23 and higher than that of the n-type low concentration region 22.
- a region (hereinafter referred to as a p-type medium concentration region) 25 having a thickness of 25 is provided.
- the p-type medium concentration region 25 is adjacent to the n-type low concentration region 22 on the first main surface side of the n-type low concentration region 22.
- the p-type high concentration region 23 is provided with the same thickness as the n-type high concentration region 21.
- the thickness of the p-type high concentration region 23 may be 9 ⁇ m, for example.
- the thickness of the p-type medium concentration region 25 may be 7 ⁇ m, for example.
- FIG. 9 is a characteristic diagram showing an impurity concentration distribution of the semiconductor device according to the fifth embodiment.
- FIG. 9 shows the n-type impurity concentration distribution at the cutting line II ′ in FIG. 8 from the lower end of the first depth d 0 to the second main surface side, and the p-type at the cutting line JJ ′ in FIG. The impurity concentration distribution is shown.
- the n-type impurity concentration distribution of the n-type region 1 at the cutting line II ′ is the same as that of the first embodiment (see FIG. 2).
- the fifth depth d 4 is a depth from the lower end of the p-type medium concentration region 25 to the lower end of the p-type region 2.
- the p-type region 2 includes a p-type high concentration region 23 (second depth d 1 ), a p-type medium concentration region 25 (fourth depth d 3 ), and a p-type low concentration region 24 ( It has different three-stage impurity concentration distributions of the fifth depth d 4 ). That is, the p-type impurity concentration distribution in the p-type region 2 has a different distribution shape from the n-type impurity concentration distribution in the n-type region 1. Further, the p-type medium concentration region 25 preferably has an impurity concentration of 1.2 times or more of the n-type region 1 adjacent to the p-type medium concentration region 25.
- the impurity concentration of the p-type intermediate concentration region 25 may be 4.0 ⁇ 10 15 / cm 3 , for example. Other configurations are the same as those in the fourth embodiment.
- FIG. 10 is a cross-sectional view of the semiconductor device according to the sixth embodiment.
- the p-type low concentration region 24 may have an impurity concentration distribution that gradually decreases from the first main surface side to the second main surface side.
- the parallel pn layer 20 has a configuration in which, for example, epitaxial layers are stacked.
- the n-type region 1 and the p-type region 2 have a wave-type impurity concentration distribution (hereinafter referred to as a wave type) formed by laminating parallel pn layers 20 having, for example, a substantially arc-shaped pn junction surface formed by diffusing introduced impurities. Type impurity concentration distribution).
- the p-type low concentration region 24 has an impurity concentration distribution that gradually decreases from the first main surface side to the second main surface side.
- the total impurity amount of the p-type low concentration region 24 is the same as the total impurity amount of the n-type low concentration region 22.
- FIG. 11 is a characteristic diagram showing the impurity concentration distribution of the semiconductor device according to the sixth embodiment.
- FIG. 11 shows the n-type impurity concentration distribution along the cutting line K-K ′ in FIG. 10 and the p-type impurity concentration distribution along the cutting line L-L ′ in FIG. 10.
- the n-type impurity concentration distribution of the n-type region 1 at the cutting line K-K ′ is the same as that of the first embodiment except that it has a wave-shaped impurity concentration distribution shape.
- the n-type region 1 has different two-stage impurity concentration distributions composed of the n-type high concentration region 21 and the n-type low concentration region 22.
- the p-type region 2 includes two different stages of p-type high-concentration regions 23 and p-type low-concentration regions 24 having an impurity concentration distribution that gradually decreases from the first main surface side to the second main surface side. It has an impurity concentration distribution.
- n-type epitaxial layer is stacked.
- n-type impurities are introduced into the entire epitaxial layer to perform thermal diffusion.
- a mask in which the formation region of the p-type region 2 is opened is formed.
- p-type impurities are introduced into the formation region of the p-type region 2 and thermal diffusion is performed. Thereby, p-type region 2 is formed.
- the region where the p-type impurity is not introduced becomes the n-type region 1.
- an n-type impurity is introduced into the epitaxial layer to be the n-type high concentration region 21 so that the n-type impurity concentration is higher than that of the second main surface side.
- Each epitaxial layer contains p-type impurities so that the impurity concentration of the p-type low concentration region 24 formed in the epitaxial layer gradually increases from the second main surface side to the first main surface side. be introduced.
- a p-type impurity is introduced into the epitaxial layer forming the p-type high concentration region 23 so as to have a higher p-type impurity concentration than the second main surface side.
- Other configurations are the same as those in the third embodiment.
- the thermal diffusion may be performed for each epitaxial layer, or the thermal diffusion may be performed by finally annealing the epitaxial layer and introducing impurities, and finally annealing.
- Example 1 12 is a characteristic diagram showing electrical characteristics at turn-off in the semiconductor device of Example 1.
- FIG. FIG. 12 is a simulation result showing a trade-off relationship between the turn-off loss and the turn-off dv / dt (hereinafter, FIG. 14, FIG. 21, FIG. 24, FIG. 27-1, FIG. 27-2, FIG. 29-1, FIG. 29-2 and FIG. 30).
- a planar type MOSFET was prepared in which the impurity concentration of the n-type high concentration region 21 was 1.2 times the impurity concentration of the n-type low concentration region 22 (hereinafter referred to as the first example).
- a planar MOSFET was prepared in which the impurity concentration of the n-type high concentration region 21 was 1.6 times the impurity concentration of the n-type low concentration region 22 (hereinafter referred to as a second embodiment).
- the thickness and surface impurity concentration of the p base region 3 were 3.0 ⁇ m and 3.0 ⁇ 10 17 cm ⁇ 3 , respectively.
- the thickness and surface impurity concentration of the n-type surface region 4 were 2.5 ⁇ m and 2.0 ⁇ 10 16 cm ⁇ 3 , respectively.
- the thickness of n + source region 6 and the surface impurity concentration were 0.5 ⁇ m and 3.0 ⁇ 10 20 cm ⁇ 3 , respectively.
- the thickness of n + drain region 11 and the surface impurity concentration were 300 ⁇ m and 2.0 ⁇ 10 18 cm ⁇ 3 , respectively.
- the thickness of the drift layer was 53.0 ⁇ m.
- the width of the n-type region 1 was 6.0 ⁇ m.
- the thickness and impurity concentration of the n-type high concentration region 21 were set to 5.5 ⁇ m and 3.6 ⁇ 10 15 cm ⁇ 3 , respectively.
- the impurity concentration of the n-type low concentration region 22 was set to 3.0 ⁇ 10 15 cm ⁇ 3 .
- the width, height, and impurity concentration of the p-type region 2 were 6.0 ⁇ m, 40.0 ⁇ m, and 3.0 ⁇ 10 15 cm ⁇ 3 , respectively.
- the breakdown voltage class was set to 600V.
- the impurity concentration of the n-type high concentration region 21 is 4.8 ⁇ 10 15 cm ⁇ 3 .
- the other configuration is the same as that of the first embodiment.
- a planar type MOSFET was prepared in which the impurity concentration of the n-type high concentration region 21 was one time the impurity concentration of the n-type low concentration region 22 (hereinafter referred to as a conventional example). That is, the conventional n-type region 1 has a uniform impurity concentration distribution. Other configurations of the conventional example are the same as those of the first embodiment. In each sample, turn-off loss and turn-off dv / dt were measured.
- the indicators for determining the performance of the semiconductor device are low turn-off loss and low turn-off dv / dt.
- the closer to the origin (lower left) of the graph the higher the performance of the semiconductor device, and the trade-off relationship between turn-off loss and turn-off dv / dt is improved.
- the lower the turn-off loss the better the trade-off relationship between the turn-off loss and the turn-off dv / dt.
- the turn-off loss is compared when the turn-off dv / dt satisfies the power supply harmonic regulation, for example, 10 kV / ⁇ s.
- the measured value when the turn-off dv / dt is 10 kV / ⁇ s is not shown.
- the other measured values of the second embodiment are assumed to be on an extension of the approximate value line connecting the illustrated measured values of the second embodiment (hereinafter, FIG. 14, FIG. 21, FIG. 24, FIG. 27-1, FIG. 27-2, FIG. 29-1, FIG. 29-2 and FIG. 30).
- the turn-off loss decreases as the impurity concentration of the n-type high concentration region 21 with respect to the n-type low concentration region 22 increases. That is, it can be seen that the trade-off relationship between the turn-off loss and the turn-off dv / dt is most improved in the second embodiment. Further, it was found that the turn-off loss can be reduced to 1 ⁇ 2 or less of the conventional example by setting the impurity concentration of the n-type high concentration region 21 to 1.2 times or more of the impurity concentration of the n-type low concentration region 22. .
- FIG. 13 is a characteristic diagram illustrating an n-type impurity concentration distribution of the semiconductor device according to the second embodiment.
- FIG. 14 is a characteristic diagram showing electrical characteristics at turn-off in the semiconductor device of Example 2.
- a planar type MOSFET was prepared according to the third embodiment (hereinafter referred to as a third example).
- the thickness and impurity concentration of the n-type high concentration region 21 were set to 8.0 ⁇ m and 4.7 ⁇ 10 15 cm ⁇ 3 , respectively.
- the impurity concentration of the n-type low concentration region 22 is, for example, 2.7 ⁇ 10 15 / cm 3 .
- the thickness of the p-type region 2 was 37 ⁇ m.
- the thickness and impurity concentration of the p-type high concentration region 23 are the same as those of the n-type high concentration region 21.
- the impurity concentration of the p-type low concentration region 24 is the same as that of the n-type low concentration region 22.
- a conventional example was prepared in the same manner as in Example 1.
- a planar MOSFET having an n-type impurity concentration gradually lowered from the first main surface side to the second main surface side of the n-type region 1 was prepared (hereinafter referred to as an inclined embodiment).
- the total impurity amount of the n-type region 1 is the same. In each sample, turn-off loss and turn-off dv / dt were measured.
- the results shown in FIG. 14 show that the turn-off loss is the lowest in the third example and the highest in the conventional example, when the turn-off dv / dt is 10 kV / ⁇ s, for example.
- the turn-off loss of the third embodiment is about 1.7 mJ.
- the turn-off loss of the conventional example is about 5.0 mJ (not shown). That is, in the third example, it can be seen that the turn-off loss can be reduced to about 1/3 of the conventional example.
- the third example best improved the trade-off relationship between the turn-off loss and the turn-off dv / dt as compared with the conventional example.
- the reason is as follows.
- the trade-off relationship between the turn-off loss and the turn-off dv / dt is also improved in the tilted example as compared with the conventional example.
- 15 to 17 are conceptual diagrams showing the spread of the depletion layer of the semiconductor device according to the second embodiment.
- FIG. 18 is a characteristic diagram showing electrical characteristics at turn-off in the semiconductor device according to the second embodiment.
- 15 to 17 show the expansion of the depletion layer 31 in the third embodiment, the expansion of the depletion layer 32 in the conventional example, and the expansion of the depletion layer 33 in the inclined embodiment when the drain voltage is increased.
- FIG. 18 is a simulation result showing the turn-off dv / dt of the third example, the conventional example, and the inclined example when the drain voltage is increased.
- the depletion layer 32 in the conventional example extends in parallel with the junction surface between the n-type region 1 and the p-type region 2.
- the parallel pn layer is completely depleted.
- the depletion layer 33 in the inclined embodiment spreads quickly on the second main surface side of the parallel pn layer having a low impurity concentration when a drain voltage is applied, and the parallel pn layer having a high impurity concentration. It spreads slowly on the first main surface side.
- the parallel pn layer is completely depleted at a drain voltage of 100V.
- the second main surface side (n-type) of the parallel pn layer having a low impurity concentration is applied as in the tilted embodiment. It spreads quickly in the low-concentration region 22 and the p-type low-concentration region 24), and slowly spreads on the first main surface side (the n-type high-concentration region 21 and the p-type high-concentration region 23) of the parallel pn layer having a high impurity concentration.
- a region that is not depleted hereinafter referred to as a neutral region remains on the first main surface side of the parallel pn layer even when the drain voltage becomes 100V.
- the drain voltage suddenly rises and the turn-off dv / dt suddenly increases accordingly.
- the parallel pn layer is easily depleted (see FIG. 16).
- the time from when the drain voltage is applied until the drain voltage starts to rise is slower than in the conventional example.
- the drain voltage rises slowly as a whole, and the turn-off dv / dt also rises slowly.
- the impurity concentration in the n-type region 1 and the p-type region 2 is gradually increased from the second main surface side to the first main surface side, so that the depletion layer is This is because it gradually expands from the second principal surface side to the first principal surface side (see FIG. 17).
- the time from when the drain voltage is applied to when the drain voltage starts to rise is earlier than in the gradient embodiment.
- the turn-off dv / dt is lower than that in the inclined embodiment. The reason is that in the third embodiment, there is a portion where the impurity concentration changes abruptly in the n-type region 1 and the p-type region 2, so that the first main surface side of the parallel pn layer is compared with the inclined embodiment. This is because the depletion layer is difficult to expand (see FIG. 15), and the drain voltage is difficult to increase.
- the third embodiment and the tilted embodiment can reduce the turn-off loss almost in the same manner as the conventional example (see FIG. 14).
- the turn-off dv / dt can be reduced as compared with the inclined example (see FIG. 18).
- the third example can improve the trade-off relationship between the turn-off loss and the turn-off dv / dt as compared with the conventional example.
- FIG. 19 is a characteristic diagram illustrating a relationship between breakdown voltage and on-resistance in the semiconductor device according to the third example.
- FIG. 19 is a simulation result showing a trade-off relationship between breakdown voltage and on-resistance.
- a third example was prepared.
- a conventional example was prepared in the same manner as in Example 1.
- an inclined example was prepared.
- the breakdown voltage and on-resistance were measured.
- the index that determines the performance of the semiconductor device is that the breakdown voltage is high and the on-resistance is low. That is, the closer to the lower right of the graph, the higher the performance of the semiconductor device and the better the trade-off relationship between on-resistance and breakdown voltage (the same applies to FIGS. 26 and 28-1 below).
- the breakdown voltages of the third example, the conventional example, and the inclined example were almost the same value.
- the on-resistance is the lowest in the conventional example. This is because the impurity concentration distribution in the n-type region 1 is uniform. For this reason, the trade-off relationship between on-resistance and breakdown voltage is most improved in the conventional example.
- the third embodiment is compared with the inclined embodiment, the on-resistance of the third embodiment is lower than the on-resistance with the inclined embodiment. The reason is estimated as follows.
- the on-resistance is determined by the impurity concentration of the n-type region 1.
- the impurity concentration on the second main surface side is low, a depletion layer spreads in the n-type region 1 due to a voltage drop due to a current flowing through the n-type region 1 and a resistance of the n-type region 1, and the current path is narrowed. As a result, the on-resistance is increased.
- the third example, and the inclined example decreases in the order of the conventional example, the third example, and the inclined example, the on-resistance of the conventional example Is the lowest, and the tilted example results in the highest. Further, since the difference in on-resistance between the third embodiment and the conventional example is about 5%, the third embodiment can improve the trade-off relationship between the withstand voltage and the on-resistance almost similarly to the conventional example. It can be said. Furthermore, as described above, the third embodiment can reduce the turn-off loss (see the second embodiment). Therefore, it can be seen that the third example has higher performance than the conventional example.
- FIG. 20 is a characteristic diagram illustrating electrical characteristics of the semiconductor device according to the fourth example.
- FIG. 21 is a characteristic diagram showing electrical characteristics when the semiconductor device according to Working Example 4 is turned off.
- FIG. 20 is a simulation result showing current-voltage characteristics after entering an avalanche (hereinafter, the same applies to FIG. 23).
- a third example was prepared.
- a planar MOSFET was prepared according to the fourth embodiment (hereinafter referred to as a fourth example).
- the thickness of the n-type high concentration region 21 is 9 ⁇ m.
- the thickness of the p-type high concentration region 23 was 16 ⁇ m.
- the impurity concentration of the n-type high concentration region 21 and the p-type high concentration region 23 was set to 5.0 ⁇ 10 15 / cm 3 .
- the impurity concentration of the n-type low concentration region 22 and the p-type low concentration region 24 was set to 3.0 ⁇ 10 15 / cm 3 .
- the other configuration is the same as that of the third embodiment.
- the current-voltage waveform after entering the avalanche was observed. In each sample, turn-off loss and turn-off dv / dt were measured.
- the drain voltage decreased when the current flowing between the drain and the source increased.
- the n-type region 1 and the p-type region 2 have substantially the same impurity concentration distribution in the depth direction, and thus negative resistance is generated after entering the avalanche.
- the drain voltage increased when the current flowing between the drain and the source increased.
- the p-type impurity amount is larger than the n-type impurity amount in the portion of the p-type high concentration region 23 that is deeper than the n-type high concentration region 21 on the second main surface side. This is because negative resistance is less likely to occur.
- the trade-off relationship between the turn-off loss and the turn-off dv / dt in the fourth embodiment can be considerably improved as compared with the conventional example, as in the third embodiment. It was. Specifically, the turn-off loss of the fourth embodiment can be reduced to about half as compared with the turn-off loss of the conventional example (not shown) when the turn-off dv / dt is, for example, 10 kV / ⁇ s. That is, in the fourth example, it was found that the trade-off relationship between the turn-off loss and the turn-off dv / dt can be improved as compared with the conventional example, and the avalanche resistance can be improved.
- FIG. 22 is a characteristic diagram showing the p-type impurity concentration distribution of the semiconductor device according to Working Example 5.
- FIG. 23 is a characteristic diagram showing electrical characteristics of the semiconductor device according to Working Example 5.
- FIG. 24 is a characteristic diagram showing electrical characteristics at turn-off in the semiconductor device according to Working Example 5.
- fifth to ninth embodiments Five planar MOSFETs were prepared (hereinafter referred to as fifth to ninth embodiments).
- the thickness (second depth d 1 ) of the p-type high concentration region 23 is 9 ⁇ m.
- the thickness (fourth depth d 3 ) of the p-type medium concentration region 25 was 7 ⁇ m.
- the other configuration is the same as that of the fourth embodiment.
- a conventional example was prepared in the same manner as in Example 1.
- the current-voltage waveform after the avalanche rush was observed.
- turn-off loss and turn-off dv / dt were measured.
- the impurity concentration of the p-type medium concentration region 25 be about 3.5 ⁇ 10 15 / cm 3 (sixth embodiment) ). Therefore, it is desirable that the impurity concentration of the p-type medium concentration region 25 is 1.2 times or more the impurity concentration of the n-type low concentration region 22 adjacent to the p-type medium concentration region 25.
- the trade-off relationship between the turn-off loss and the turn-off dv / dt deteriorates as the impurity concentration in the p-type medium concentration region 25 increases.
- the turn-off loss in the fifth to ninth embodiments can be suppressed to an increase of about 10% of the turn-off loss in the third embodiment (not shown). For this reason, it was found that the trade-off relationship between the turn-off loss and the turn-off dv / dt can be improved in the fifth to ninth embodiments as in the third embodiment.
- the impurity concentration distribution in the p-type region 2 is gradually changed from the first main surface side to the second main surface side. be able to. For this reason, it is presumed that the time from when the drain voltage is applied until the drain voltage starts to rise can be delayed (see the tilting example in FIG. 18). As a result, the depletion layer is less likely to expand and the drain voltage is less likely to increase, and it is assumed that the turn-off dv / dt can be further reduced.
- FIG. 25 is a characteristic diagram showing the impurity concentration distribution of the semiconductor device according to Working Example 6.
- FIG. 26 is a characteristic diagram showing electrical characteristics of the semiconductor device according to Working Example 6.
- FIGS. 27A and 27B are characteristic diagrams showing electrical characteristics at turn-off in the semiconductor device according to Working Example 6.
- FIGS. First as shown in FIG. 25, according to the sixth embodiment, a planar type MOSFET is prepared in which the impurity concentration of the p-type low concentration region 24 is gradually lowered from the first main surface side to the second main surface side (hereinafter referred to as “the p-type low concentration region 24”). The tenth embodiment).
- the impurity concentration of the n-type high concentration region 21 is set to 7.5 ⁇ 10 15 / cm 3 .
- the impurity concentration of the n-type low concentration region 22 was set to 3.0 ⁇ 10 15 / cm 3 . That is, the impurity concentration of the n-type high concentration region 21 is set to 2.5 times the impurity concentration of the n-type low concentration region 22.
- the impurity concentration of the p-type high concentration region 23 was 1.5 ⁇ 10 16 / cm 3 .
- the impurity concentration of the p-type low concentration region 24 is set to 6.6 ⁇ 10 15 / cm 3 on the first main surface side, and 5.4 ⁇ 10 15 / cm 3 on the second main surface side, and from the first main surface side.
- the impurity concentration distribution was decreased by 0.3 ⁇ 10 15 / cm 3 toward the second main surface side.
- the depth from the upper end of the p-type region 2 for changing the impurity concentration in the p-type region 2 (hereinafter referred to as the concentration change depth), that is, the thickness of the p-type high concentration region 23 was set to 5 ⁇ m.
- the impurity concentration of the p-type low concentration region 24 is set to 7.2 ⁇ 10 15 / cm 3 on the first main surface side and 4.8 ⁇ 10 15 / cm 3 on the second main surface side, and the first main surface An impurity concentration distribution that decreases by 0.6 ⁇ 10 15 / cm 3 from the side to the second main surface side was used, and the other example 10-1 was prepared in the same manner as the tenth example. Further, the n-type high concentration region 21 has an impurity concentration of 3.6 ⁇ 10 15 / cm 3 and the n-type low concentration region 22 has an impurity concentration of 3.0 ⁇ 10 15 / cm 3.
- the impurity concentration of the p-type low concentration region 24 is 1.2 times the impurity concentration of the n-type low concentration region 22 and the impurity concentration of the p-type high concentration region 23 is 7.2 ⁇ 10 15 / cm 3.
- the concentration is 6.0 ⁇ 10 15 / cm 3
- the impurity concentration of the p-type high concentration region 23 is 1.2 times the impurity concentration of the p-type low concentration region 24, and the others are the same as in the tenth embodiment.
- Example 10-2 was also prepared. For comparison, a conventional example was prepared in the same manner as in Example 1.
- a planar MOSFET having a uniform impurity concentration distribution in the p-type low concentration region 24 was prepared (hereinafter referred to as a first comparative example).
- the impurity concentration of the p-type low concentration region 24 is 6.0 ⁇ 10 15 / cm 3 .
- the other configuration is the same as that of the tenth embodiment.
- the breakdown voltage and on-resistance were measured.
- turn-off loss and turn-off dv / dt were measured.
- net doping net carrier concentration
- net doping of the p-type region in FIG. 25 subtracts the phosphorus concentration from the boron concentration. Value.
- the tenth and tenth embodiments have lower on-resistance than the conventional example.
- the tenth embodiment and the tenth embodiment have a higher breakdown voltage than the first comparative example.
- the trade-off relationship between on-resistance and breakdown voltage is most improved in the tenth embodiment.
- the turn-off loss is reduced in the tenth embodiment, the tenth embodiment, and the tenth embodiment as compared with the conventional example.
- the turn-off dv / dt is, for example, 10 kV / ⁇ s
- the turn-off loss of the tenth embodiment is about 0.1 mJ.
- the turn-off loss of the conventional example is about 0.4 mJ. That is, in the tenth embodiment, the turn-off loss can be reduced to about 1 ⁇ 4 of the conventional example. As a result, in the tenth example, it was found that both the trade-off relationship between the on-resistance and the withstand voltage and the trade-off relationship between the turn-off loss and the turn-off dv / dt can be improved better than the conventional example. . Further, the turn-off loss is reduced in the 10-1 and 10-2 embodiments as compared with the conventional example, and the trade-off relationship between the on-resistance and the breakdown voltage and the trade-off relationship between the turn-off loss and the turn-off dv / dt. It has been found that both can be improved better than the conventional example.
- FIG. 27-2 shows the trade-off between the turn-off loss and the turn-off dv / dt when the point of the depth y changing from the high concentration region of both p-type and n-type to the low concentration region is changed between 5 ⁇ m and 12 ⁇ m. It is the characteristic view which showed the relationship.
- y is deeper than 5 ⁇ m, the trade-off relationship between the turn-off loss and the turn-off dv / dt is improved, but in the case of 12 ⁇ m, the trade-off relationship is not as good as 10 ⁇ m.
- Example 7 28A and 28B are characteristic diagrams illustrating electrical characteristics of the semiconductor device according to Working Example 7.
- FIG. FIGS. 29A and 29B are characteristic diagrams showing electrical characteristics at turn-off in the semiconductor device according to Working Example 7.
- FIGS. First according to the sixth embodiment, seven planar MOSFETs were prepared in which the concentration change depth (thickness of the n-type high concentration region 21) was 1 ⁇ m, 5 ⁇ m, 10 ⁇ m, 15 ⁇ m, 20 ⁇ m, 25 ⁇ m, and 30 ⁇ m (hereinafter, referred to as the following). The eleventh embodiment to the seventeenth embodiment).
- the thickness of the p-type high concentration region 23 is the same as that of each n-type high concentration region 21.
- the impurity concentration of the n-type high concentration region 21 was set to 4.5 ⁇ 10 15 / cm 3 .
- the impurity concentration on the first main surface side of the n-type region 1 was set to 3.0 ⁇ 10 15 / cm 3 .
- the impurity concentration of the p-type high concentration region 23 was set to 9.0 ⁇ 10 15 / cm 3, and the impurity concentration of the p-type low concentration region 24 was set to 6.0 ⁇ 10 15 / cm 3 .
- Other configurations are the same as those in the sixth embodiment.
- the concentration change depth is set to 1 ⁇ m, 5 ⁇ m, 10 ⁇ m, 15 ⁇ m, 20 ⁇ m, 25 ⁇ m, and 30 ⁇ m.
- the impurity concentration of the concentration region 21 is 7.5 ⁇ 10 15 / cm 3
- the impurity concentration on the first main surface side of the n-type region 1 is 3.0 ⁇ 10 15 / cm 3
- the p-type high concentration region 23 Seven planar MOSFETs having double the concentration difference were prepared, in which the impurity concentration was 1.5 ⁇ 10 16 / cm 3 and the impurity concentration of the p-type low concentration region 24 was 6.0 ⁇ 10 15 / cm 3 (hereinafter referred to as “concentration difference”). 11-11 embodiment to 17-1 embodiment).
- a conventional example was prepared in the same manner as in Example 1. In each sample, the breakdown voltage and on-resistance were measured. In each sample, turn-off loss and turn-off dv / dt were measured.
- the on-resistance is reduced in the eleventh embodiment to the seventeenth embodiment and the eleventh embodiment to the seventeenth embodiment in comparison with the conventional example. I found out that I could do it. It was also found that the on-resistance can be lowered as the concentration change depth is increased. In contrast, in the eleventh embodiment to the seventeenth embodiment and the eleventh embodiment to the seventeenth embodiment, it was found that the withstand voltage was reduced as compared with the conventional example. It was also found that the breakdown voltage decreases as the concentration change depth increases. Further, from the results shown in FIGS.
- the trade-off relationship between the turn-off loss and the turn-off dv / dt can be improved as the concentration change depth is increased.
- the concentration change depth is too deep, the trade-off relationship between the turn-off loss and the turn-off dv / dt is worse than in the conventional example.
- the trade-off relationship between the turn-off loss and the turn-off dv / dt should be realized to the same extent as in the conventional example and not worse than that in the conventional example. I understand. For this reason, it has been found that the concentration change depth needs to be 1 ⁇ 2 or less of the thickness of the p-type region 2.
- the twelfth embodiment, the twelfth embodiment, the thirteenth embodiment, and the thirteenth embodiment are compared.
- the concentration change depth is 1/3 or less of the thickness of the p-type region 2 (see the thirteenth and thirteenth embodiments).
- the thickness of the p-type region 2 is not less than 1/8 and not more than 1/4 (see the twelfth embodiment and the twelfth embodiment).
- FIG. 30 is a characteristic diagram showing electrical characteristics at turn-off in the semiconductor device according to Working Example 8.
- the impurity concentration of the n-type high concentration region 21 is set to 1.33 times, 1.67 times, 2 times, and 2.33 times the impurity concentration of the n-type low concentration region 22.
- Planar MOSFETs were prepared (hereinafter referred to as 18th to 21st examples).
- the tenth example was prepared in which the impurity concentration of the n-type high concentration region 21 was 2.5 times the impurity concentration of the n-type low concentration region 22.
- turn-off loss and turn-off dv / dt were measured. From the result shown in FIG.
- the trade-off relationship between the turn-off loss and the turn-off dv / dt can be improved as the ratio of the impurity concentration of the n-type high concentration region 21 to the impurity concentration of the n-type low concentration region 22 increases. I knew it was possible. In the eighteenth to twenty-first embodiments, the trade-off relationship between the turn-off loss and the turn-off dv / dt can be improved almost similarly. In the tenth embodiment, the impurity concentration ratio is tripled, and the impurity concentration of the p-type low concentration region 24 is decreased by 0.45 ⁇ 10 15 / cm 3 from the first main surface side to the second main surface side.
- the ratio of the impurity concentration of the n-type high concentration region 21 to the impurity concentration of the n-type low concentration region 22 is preferably 1.2 times or more and 3 times or less, and preferably 2.5 times or less.
- the main methods for manufacturing the SJ-MOSFET include a multi-stage epi method and a trench filling method.
- the trench embedding method is simpler than the multi-stage epi method because a parallel pn structure can be formed by forming a deep trench once in the n epi layer and embedding the p-type epi layer.
- the avalanche resistance is weak because the current-voltage characteristics during avalanche are negative under charge balance conditions where the withstand voltage reaches a peak.
- a device capable of improving the Eoff-dv / dt trade-off can be manufactured by a trench filling method that is simpler than the multi-stage epi method.
- FIG. 31 and 32 are cross-sectional views sequentially showing the manufacturing process of the semiconductor device according to the seventh embodiment.
- an n-type low concentration region 42 and a high concentration n-type surface region 43 are sequentially deposited in an n + drain region 41, and a resist 45 is patterned on the mask oxide film 44 on the surface.
- the mask oxide film 44 is etched to open the surface of the n-type surface region 43, and then deep trench etching is performed as shown in FIG. A trench 46 is formed.
- FIG. 31D a low-concentration p-epi layer 47 is epitaxially grown and buried in the deep trench 46.
- the surface of the low concentration p-epi layer 47 is etched back by plasma etching or the like so that the height of the low concentration p-epi layer 47 and the n-type low concentration region 42 are substantially equal.
- a high concentration p layer 48 is buried in the deep trench 46 by epitaxial growth, and a high concentration p layer 48 is formed on the surface of the low concentration p epi layer 47.
- the surface is flattened by chemical mechanical polishing (CMP) or the like.
- FIG. 32D which is a subsequent process, follows the same process as the process for forming the planar MOS structure of the first embodiment, and a final device shape is obtained.
- 49 is a p base region
- 50 is an n + source region
- 51 is a gate insulating film
- 52 is a gate electrode
- 53 is an interlayer insulating film
- 54 is a source electrode.
- the low-concentration p-epi layer 47 and the n-type low-concentration region 42 are generally in charge balance
- the n-type surface region 43 and high-concentration p-layer 48 are generally in charge balance.
- the depths of the n-type surface region 43 and the high-concentration p layer 48 are not less than 1/8 and not more than 1/2 of the depth of all parallel pn layer portions with respect to the first main surface.
- the seventh embodiment since a device capable of improving the Eoff-dv / dt trade-off can be manufactured by the embedded epi method, compared with the case where a similar device is manufactured in the multi-stage epi method.
- the process can be simplified.
- FIG. 33 is a cross-sectional view sequentially illustrating manufacturing steps of the semiconductor device according to the eighth embodiment.
- manufacturing is performed in the same procedure as in FIGS. 31 (a) to 31 (d).
- the surface of the low-concentration p-epi layer 47 is not etched back, and the high-concentration p-epi layer 47 is buried on the low-concentration p-epi layer 47 buried in the deep trench 46 as shown in FIG. Layer 55 is formed.
- the surface is planarized by chemical mechanical polishing (CMP) or the like.
- CMP chemical mechanical polishing
- the eighth embodiment is a manufacturing method that omits the etch-back of the low-concentration p-epi layer 47 shown in FIG. 32A in the seventh embodiment, the process is simpler than the seventh embodiment. be able to.
- the low-concentration p-epi layer 47 and the n-type low-concentration region 42 are substantially in charge balance, and the n-type surface region 43 and high-concentration p-layer 55 are in general charge balance.
- the depths of the n-type surface region 43 and the high-concentration p layer 55 are 1 / or more and 1 ⁇ 2 or less of the depth of all parallel pn layer portions with respect to the first main surface.
- the eighth embodiment since a device capable of improving the Eoff-dv / dt trade-off can be produced by the embedded epi method, compared to the case where a similar device is manufactured in the multi-stage epi method.
- the process can be simplified.
- the depths of the n-type surface region 43 and the high-concentration p layers 48 and 55 are substantially equal.
- the high-concentration p-layers 48 and 55 are formed on the n-type surface. What is necessary is just to form so that it may become deeper than the area
- FIG. 34 is a cross-sectional view sequentially illustrating manufacturing steps of the semiconductor device according to the ninth embodiment.
- the manufacturing is performed in the same procedure as that shown in FIGS.
- a low-concentration p-epi layer 47 is buried in the deep trench 46 by epitaxial growth. It is desirable that the low-concentration p-epi layer 47 has a smaller amount of filling than that in FIG. This is because the amount of etch back in the subsequent process can be reduced.
- FIG. 34B the surface of the low-concentration p-epi layer 47 is etched back by plasma etching or the like.
- the low-concentration p-epi layer 47 is etched back deeply so that the height is lower than the lower end of the n-type surface region 43. .
- the high-concentration p layer 48 is buried in the deep trench 46 by epitaxial growth, and the high-concentration p layer 48 is formed on the surface of the low-concentration p epi layer 47.
- the surface is planarized by CMP or the like.
- the structure shown in FIG. 34E is obtained as the final device shape.
- the low-concentration p-epi layer 47 and the n-type low-concentration region 42 are substantially in charge balance, and the high-concentration p-layer 48 facing the n-type surface region 43 is substantially charge-balanced. It has become.
- the lower end of the high concentration p layer 48 is formed deeper than the lower end of the n type surface region 43, the high concentration p layer 48 and the n type low concentration region 42 face each other. The part which becomes is p rich.
- the depths of the n-type surface region 43 and the high-concentration p layer 48 are not less than 1/8 and not more than 1/2 of the depth of all parallel pn layer portions with respect to the first main surface.
- a device capable of achieving not only the Eoff-dv / dt trade-off improvement similar to the seventh embodiment but also the avalanche resistance improvement by providing the p-rich region can be produced by the embedded epi method.
- a region facing a certain region is a portion located at substantially the same depth as a certain region and adjacent to a certain region (hereinafter, the same applies to Embodiments 10 to 12).
- FIG. 35 is a cross-sectional view of the manufacturing process when the manufacturing process of the semiconductor device according to the ninth embodiment is applied to the manufacturing method of manufacturing the semiconductor device according to the second embodiment.
- FIG. 35 is a cross-sectional view sequentially illustrating the manufacturing steps of the semiconductor device according to the tenth embodiment.
- the manufacturing is performed in the same procedure as that shown in FIGS.
- FIG. 35A as in FIG. 34A, a low-concentration p-epi layer 47 is buried in the deep trench 46 by epitaxial growth.
- FIG. 35A a low-concentration p-epi layer 47 is buried in the deep trench 46 by epitaxial growth.
- the low-concentration p-epi layer 47 is not etched back, and the high-concentration p-layer 55 is formed on the low-concentration p-epi layer 47. Thereafter, as shown in FIG. 35C, the surface is flattened by CMP or the like. The final device shape is as shown in FIG.
- the tenth embodiment is different from the ninth embodiment in that the average concentration of the low-concentration p-epi layer 47 and the high-concentration p-layer 55 facing the n-type surface region 43 on the first main surface side is almost the same.
- the charge balance is the same as in the ninth embodiment.
- the depths of n-type surface region 43 and high-concentration p layer 55 are not less than 1/8 and not more than 1/2 of the depth of all parallel pn layer portions with reference to the first main surface. ing.
- FIG. 36A is cross-sectional views sequentially showing manufacturing steps of the semiconductor device according to the eleventh embodiment.
- the manufacturing is performed in the same procedure as that shown in FIGS.
- FIG. 36B a low-concentration p-epi layer 47 is buried in the deep trench 46 by epitaxial growth.
- the low-concentration p-epi layer 47 is etched back, and then the medium-concentration p-layer 56 is buried by epitaxial growth as shown in FIG.
- FIG. 36B shows that the manufacturing is performed in the same procedure as that shown in FIGS.
- the intermediate concentration p layer 56 is etched back so that the upper surface of the intermediate concentration p layer 56 and the upper surface of the n-type low concentration region 42 have substantially the same height.
- a high concentration p layer 57 is buried in the deep trench 46 by epitaxial growth, and a high concentration p layer 57 is formed on the surface of the intermediate concentration p layer 56.
- the surface is planarized by CMP or the like.
- the final device shape is as shown in FIG.
- the low-concentration p-epi layer 47 and the n-type low-concentration region 42 opposed thereto are almost in charge balance, and the n-type surface region 43 is a high-concentration p-layer on the first main surface side. 57 is almost in charge balance.
- the portion where the medium concentration p layer 56 and the n-type low concentration region 42 opposed to the medium concentration p layer 56 are p-rich so that the avalanche resistance can be improved by avoiding the negative resistance.
- the depth of the n-type surface region 43 is not less than 1/8 and not more than 1/2 of the depth of all parallel pn layer portions with respect to the first main surface.
- the depths of the high-concentration p layer 57 and the medium-concentration p layer 56 are 8 or more and 1 ⁇ 2 or less of the depth of all parallel pn layer portions.
- the portion where the high-concentration p layer 48 and the n-type low concentration region 42 face each other is the portion where the medium concentration p layer 56 and the n-type low concentration region 42 face each other in the eleventh embodiment.
- the degree of p-riching in the eleventh embodiment is lower than that in the ninth embodiment, and the Eoff-dv / dt tradeoff is improved.
- the manufacturing method of the eleventh embodiment it is possible to easily manufacture a device that can simultaneously achieve the Eoff-dv / dt trade-off and the avalanche resistance improvement.
- FIG. 38 is a main cross-sectional view of the manufacturing process when the manufacturing process of the semiconductor device according to the tenth embodiment is used in the manufacturing process of the semiconductor device according to the eighth embodiment.
- FIG. 38 is a cross-sectional view sequentially illustrating the manufacturing steps of the semiconductor device according to the twelfth embodiment.
- the manufacturing is performed in the same procedure as that shown in FIGS.
- FIG. 38A a low concentration p-epi layer 47 is buried in the deep trench 46 by epitaxial growth.
- a medium concentration p layer 58 is buried by epitaxial growth inside the low concentration p epi layer 47.
- FIG. 38C a high concentration p layer 59 is embedded in the low concentration p epi layer 47 by epitaxial growth.
- the surface is flattened by CMP or the like.
- the final device shape is as shown in FIG.
- the present invention is not limited to the above-described embodiment, and various modifications can be made.
- the dimensions and concentrations described in the embodiments are examples, and the present invention is not limited to these values.
- the first conductivity type is n-type and the second conductivity type is p-type.
- the first conductivity type is p-type and the second conductivity type is n-type. It holds.
- the present invention is not limited to MOSFETs but can be applied to IGBTs, bipolar transistors, FWDs (Free Wheeling Diodes), Schottky diodes, and the like.
- a structure having a trench gate structure may be used instead of the planar gate structure.
- the semiconductor device according to the present invention is useful for a high-power semiconductor device, and in particular, has a high breakdown voltage such as a MOSFET, IGBT, bipolar transistor, FWD, or Schottky diode having a parallel pn structure in the drift portion. And suitable for a semiconductor device capable of achieving both a large current capacity.
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Abstract
Description
図1は、実施の形態1にかかる半導体装置を示す断面図である。図1に示す半導体装置は、第1主面側に素子活性部を有し、第2主面側にn+ドレイン領域(低抵抗層)11を有する。素子活性部には、例えばプレーナ型MOSFETの表面構造として、pベース領域(第2導電型ベース領域)3、n型表面領域(第1導電型表面領域)4、p+コンタクト領域5、n+ソース領域6、ゲート絶縁膜7、ゲート電極8、層間絶縁膜9およびソース電極10が設けられている。第2主面には、n+ドレイン領域11に接するドレイン電極12が設けられている。
図3は、実施の形態2にかかる半導体装置を示す断面図である。実施の形態1において、トレンチ構造を適用してもよい。
図4は、実施の形態3にかかる半導体装置を示す断面図である。図4では、並列pn層20のうち、1つのpn接合のみを示す(以下、図6および図8においても同様)。実施の形態1において、p型領域2の第1主面側の不純物濃度を、p型領域2の第2主面側の不純物濃度よりも高くしてもよい。
図6は、実施の形態4にかかる半導体装置を示す断面図である。実施の形態3において、p型高濃度領域23を、n型高濃度領域21の下端よりも第2主面側に深く設けてもよい。
図8は、実施の形態5にかかる半導体装置を示す断面図である。実施の形態4において、p型高濃度領域23のうち、n型高濃度領域21の下端よりも第2主面側に深く設けた領域を、n型高濃度領域21の下端よりも第1主面側のp型高濃度領域23よりも低い不純物濃度としてもよい。
図10は、実施の形態6にかかる半導体装置を示す断面図である。実施の形態3において、p型低濃度領域24は、第1主面側から第2主面側にかけて徐々に低くなる不純物濃度分布を有してもよい。
図12は、実施例1の半導体装置におけるターンオフ時の電気的特性を示す特性図である。図12は、ターンオフ損失とターンオフdv/dtとのトレードオフ関係を示すシミュレーション結果である(以下、図14、図21、図24、図27-1、図27-2、図29-1、図29-2および図30において同様)。実施の形態1に従い、n型高濃度領域21の不純物濃度をn型低濃度領域22の不純物濃度の1.2倍としたプレーナ型MOSFETを準備した(以下、第1実施例とする)。また、n型高濃度領域21の不純物濃度をn型低濃度領域22の不純物濃度の1.6倍としたプレーナ型MOSFETを準備した(以下、第2実施例とする)。
図13は、実施例2にかかる半導体装置のn型不純物濃度分布を示す特性図である。また、図14は、実施例2の半導体装置におけるターンオフ時の電気的特性を示す特性図である。まず、図13に示すように、実施の形態3に従い、プレーナ型MOSFETを準備した(以下、第3実施例とする)。第3実施例では、n型高濃度領域21の厚さおよび不純物濃度を、それぞれ8.0μmおよび4.7×1015cm-3とした。n型低濃度領域22の不純物濃度を、例えば2.7×1015/cm3とした。p型領域2の厚さを、37μmとした。p型高濃度領域23の厚さおよび不純物濃度は、n型高濃度領域21と同様である。p型低濃度領域24の不純物濃度は、n型低濃度領域22と同じである。比較として、実施例1と同様に、従来例を準備した。また、n型領域1の第1主面側から第2主面側にかけて、n型不純物濃度を徐々に低くしたプレーナ型MOSFETを準備した(以下、傾斜実施例とする)。第3実施例、従来例および傾斜実施例ともに、n型領域1の全体の不純物量は同じである。そして、各試料において、ターンオフ損失およびターンオフdv/dtを測定した。
図19は、実施例3にかかる半導体装置における耐圧とオン抵抗との関係を示す特性図である。図19は、耐圧とオン抵抗とのトレードオフ関係を示すシミュレーション結果である。まず、実施例2と同様に、第3実施例を準備した。比較として、実施例1と同様に、従来例を準備した。実施例2と同様に、傾斜実施例を準備した。そして、各試料において、耐圧およびオン抵抗を測定した。図19に示す結果では、半導体装置の性能を決定する指標は、耐圧が高く、かつオン抵抗が低いことである。つまり、グラフの右下に近づくほど、半導体装置の性能は高くなり、オン抵抗と耐圧とのトレードオフ関係が改善されている(以下、図26および図28-1においても同様)。
図20は、実施例4にかかる半導体装置における電気的特性を示す特性図である。また、図21は、実施例4にかかる半導体装置におけるターンオフ時の電気的特性を示す特性図である。図20は、アバランシェ突入後の電流-電圧特性について示すシミュレーション結果である(以下、図23において同様)。まず、実施例2と同様に、第3実施例を準備した。また、実施の形態4に従い、プレーナ型MOSFETを準備した(以下、第4実施例とする)。第4実施例では、n型高濃度領域21の厚さを9μmとした。p型高濃度領域23の厚さを16μmとした。n型高濃度領域21およびp型高濃度領域23の不純物濃度を5.0×1015/cm3とした。n型低濃度領域22およびp型低濃度領域24の不純物濃度を3.0×1015/cm3とした。それ以外の構成は、第3実施例と同様である。そして、第3実施例および第4実施例において、アバランシェ突入後の電流-電圧波形を観測した。また、各試料において、ターンオフ損失およびターンオフdv/dtを測定した。
図22は、実施例5にかかる半導体装置のp型不純物濃度分布を示す特性図である。また、図23は、実施例5にかかる半導体装置における電気的特性を示す特性図である。また、図24は、実施例5にかかる半導体装置におけるターンオフ時の電気的特性を示す特性図である。まず、図22に示すように第1深さd0の下端から第2主面側にかけて、実施の形態5に従い、p型中濃度領域25(第4深さd3)の不純物濃度を、3.0×1015/cm3、3.5×1015/cm3、4.0×1015/cm3、4.5×1015/cm3、5.0×1015/cm3とした、5つのプレーナ型MOSFETを準備した(以下、第5実施例~第9実施例とする)。また、第5実施例~第9実施例では、p型高濃度領域23の厚さ(第2深さd1)を9μmとした。p型中濃度領域25の厚さ(第4深さd3)を7μmとした。それ以外の構成は、第4実施例と同様である。また、比較として、実施例1と同様に、従来例を準備した。そして、第5実施例~第9実施例において、アバランシェ突入後の電流-電圧波形を観測した。また、第5実施例~第9実施例および従来例において、ターンオフ損失およびターンオフdv/dtを測定した。
図25は、実施例6にかかる半導体装置の不純物濃度分布を示す特性図である。また、図26は、実施例6にかかる半導体装置における電気的特性を示す特性図である。また、図27-1、図27-2は、実施例6にかかる半導体装置におけるターンオフ時の電気的特性を示す特性図である。まず、図25に示すように、実施の形態6に従い、p型低濃度領域24の不純物濃度を、第1主面側から第2主面側にかけて徐々に低くしたプレーナ型MOSFETを準備した(以下、第10実施例とする)。第10実施例では、n型高濃度領域21の不純物濃度を7.5×1015/cm3とした。n型低濃度領域22の不純物濃度を3.0×1015/cm3とした。つまり、n型高濃度領域21の不純物濃度を、n型低濃度領域22の不純物濃度の2.5倍とした。p型高濃度領域23の不純物濃度を1.5×1016/cm3とした。p型低濃度領域24の不純物濃度を、第1主面側で6.6×1015/cm3、第2主面側で5.4×1015/cm3とし、第1主面側から第2主面側にかけて0.3×1015/cm3ずつ減少する不純物濃度分布とした。p型領域2内の不純物濃度を変更するp型領域2の上端からの深さ(以下、濃度変更深さとする)、つまり、p型高濃度領域23の厚さを5μmとした。また、p型低濃度領域24の不純物濃度を、第1主面側で7.2×1015/cm3、第2主面側で4.8×1015/cm3とし、第1主面側から第2主面側にかけて0.6×1015/cm3ずつ減少する不純物濃度分布とし、その他は第10実施例と同様である第10-1実施例も準備した。更に、n型高濃度領域21の不純物濃度を3.6×1015/cm3とし、n型低濃度領域22の不純物濃度を3.0×1015/cm3とし、n型高濃度領域21の不純物濃度を、n型低濃度領域22の不純物濃度の1.2倍とし、p型高濃度領域23の不純物濃度を7.2×1015/cm3とし、p型低濃度領域24の不純物濃度を6.0×1015/cm3とし、p型高濃度領域23の不純物濃度をp型低濃度領域24の不純物濃度の1.2倍として、その他は第10実施例と同様である第10-2実施例も準備した。比較として、実施例1と同様に、従来例を準備した。また、p型低濃度領域24の不純物濃度分布が均一なプレーナ型MOSFETを準備した(以下、第1比較例とする)。第1比較例では、p型低濃度領域24の不純物濃度を6.0×1015/cm3とした。それ以外の構成は、第10実施例と同様である。そして、各試料において、耐圧およびオン抵抗を測定した。また、各試料において、ターンオフ損失およびターンオフdv/dtを測定した。なお、図25では、ネットドーピング(正味のキャリア濃度)で示している。つまり、半導体基板の全面にリンでn型領域を形成し、ボロンを導入してp型領域を形成しているので、図25におけるp型領域のネットドーピングは、ボロン濃度からリン濃度を差し引いた値である。
図28-1および図28-2は、実施例7にかかる半導体装置における電気的特性を示す特性図である。また、図29-1および図29-2は、実施例7にかかる半導体装置におけるターンオフ時の電気的特性を示す特性図である。まず、実施の形態6に従い、濃度変更深さ(n型高濃度領域21の厚さ)を1μm、5μm、10μm、15μm、20μm、25μm、30μmとした、7つのプレーナ型MOSFETを準備した(以下、第11実施例~第17実施例とする)。第11実施例~第17実施例では、p型高濃度領域23の厚さは、それぞれのn型高濃度領域21と同様である。n型高濃度領域21の不純物濃度を4.5×1015/cm3とした。n型領域1の第1主面側の不純物濃度を3.0×1015/cm3とした。p型高濃度領域23の不純物濃度を9.0×1015/cm3とし、p型低濃度領域24の不純物濃度を6.0×1015/cm3とした。それ以外の構成は、実施例6と同様である。また、第11実施例~第17実施例の変形例として、濃度変更深さ(n型高濃度領域21の厚さ)を1μm、5μm、10μm、15μm、20μm、25μm、30μmとし、n型高濃度領域21の不純物濃度を7.5×1015/cm3とし、n型領域1の第1主面側の不純物濃度を3.0×1015/cm3とし、p型高濃度領域23の不純物濃度を1.5×1016/cm3とし、p型低濃度領域24の不純物濃度を6.0×1015/cm3とした濃度差2倍の7つのプレーナ型MOSFETを準備した(以下、第11-1実施例~第17-1実施例とする)。比較として、実施例1と同様に、従来例を準備した。そして、各試料において、耐圧およびオン抵抗を測定した。また、各試料において、ターンオフ損失およびターンオフdv/dtを測定した。
図30は、実施例8にかかる半導体装置におけるターンオフ時の電気的特性を示す特性図である。まず、実施の形態6に従い、n型高濃度領域21の不純物濃度をn型低濃度領域22の不純物濃度の1.33倍、1.67倍、2倍、2.33倍とした、4つのプレーナ型MOSFETを準備した(以下、第18実施例~第21実施例とする)。また、実施例6と同様に、n型高濃度領域21の不純物濃度をn型低濃度領域22の不純物濃度の2.5倍とした第10実施例を準備した。そして、各試料において、ターンオフ損失およびターンオフdv/dtを測定した。図30に示す結果より、n型高濃度領域21の不純物濃度の、n型低濃度領域22の不純物濃度に対する割合が高いほど、ターンオフ損失とターンオフdv/dtとのトレードオフ関係を改善することができることがわかった。また、第18実施例~第21実施例では、ターンオフ損失とターンオフdv/dtとのトレードオフ関係をほぼ同様に改善することができる。また、第10実施例において、不純物濃度比を3倍とし、p型低濃度領域24の不純物濃度を、第1主面側から第2主面側にかけて0.45×1015/cm3ずつ減少する不純物濃度分布とした実施例で600Vの耐圧を確認した。これらより、n型高濃度領域21の不純物濃度の、n型低濃度領域22の不純物濃度に対する割合は、1.2倍以上3倍以下好ましくは2.5倍以下とすることがよいことがわかる。
SJ-MOSFETを製造する主な方法としては多段エピ方式とトレンチ埋め込み方式とがある。トレンチ埋め込み方式ではnエピ層に深掘りトレンチを1回形成してp型エピ層を埋め込むだけで並列pn構造をつくることができるので、多段エピ方式よりも簡便である。
図33は、実施の形態8にかかる半導体装置の製造工程を順に示した断面図である。まず、図31(a)~(d)と同様な手順で製造を行う。ただし、続く工程ではまず、低濃度pエピ層47表面はエッチバックせずに、図33(a)に示すように深掘りトレンチ46内部に埋め込んだ低濃度pエピ層47の上に高濃度p層55を形成する。続いて、図33(b)に示すように化学機械研磨(CMP)などで表面の平坦化を行う。これより後の工程である図33(c)は前記実施の形態1のプレーナMOS構造を形成する工程と同じ工程に従い、最終デバイス形状が得られる。つまり、実施の形態8は、実施の形態7において図32(a)に示した低濃度pエピ層47のエッチバックを省いた製造方法であるので、実施の形態7よりも工程を簡便化することができる。
実施の形態7と実施の形態8ではn型表面領域43と高濃度p層48,55の深さが概ね等しかったが、アバランシェ耐量を上げるためには高濃度p層48,55がn型表面領域43よりも深くなるように形成すればよい。
なお、実施の形態9にかかる半導体装置の製造工程を、実施の形態2にかかる半導体装置を作製する製造方法に当てはめた場合の製造工程の断面図は図35のようになる。図35は、実施の形態10にかかる半導体装置の製造工程を順に示した断面図である。まず、図31(a)~(c)と同様な手順で製造を行う。次に、図35(a)では図34(a)と同様に、深掘りトレンチ46内部に低濃度pエピ層47をエピタキシャル成長で埋め込む。続く図35(b)の工程では低濃度pエピ層47のエッチバックは行わず、低濃度pエピ層47の上に高濃度p層55を形成する。その後、図35(c)に示すようにCMPなどで表面の平坦化を行う。最終デバイス形状は図35(d)のようになる。
実施の形態9において高濃度p層48を深くする代わりにn型表面領域43と高濃度p層57の深さが概ね同じになるようにし、高濃度p層57と低濃度pエピ層47との間に中濃度p層56を設けてもかまわない。このような構造としたのが、実施の形態11である。
実施の形態10にかかる半導体装置の製造工程を、実施の形態8にかかる半導体装置の製造工程に用いた場合の製造工程の主要断面図は図38のようになる。図38は、実施の形態12にかかる半導体装置の製造工程を順に示した断面図である。まず、図31(a)~(c)と同様な手順で製造を行う。次に、図38(a)のように深掘りトレンチ46内部に低濃度pエピ層47をエピタキシャル成長で埋め込む。さらに、図38(b)に示すように、低濃度pエピ層47の内部に中濃度p層58をエピタキシャル成長で埋め込む。続いて、図38(c)に示すように、低濃度pエピ層47の内部に高濃度p層59をエピタキシャル成長で埋め込む。その後、図38(d)に示すようにCMPなどで表面の平坦化を行う。最終デバイス形状は図38(e)のようになる。
2 p型領域
3 pベース領域
4 n型表面領域
5 p+コンタクト領域
6 n+ソース領域
7 ゲート絶縁膜
8 ゲート電極
9 層間絶縁膜
10 ソース電極
11 n+ドレイン領域
12 ドレイン電極
20 並列pn層
21 n型高濃度領域
22 n型低濃度領域
Claims (20)
- 第1主面側に設けられた素子活性部と、
第2主面側に設けられた低抵抗層と、
前記素子活性部と前記低抵抗層との間に設けられ、第1導電型領域および第2導電型領域が交互に配置された並列pn層と、
前記第2導電型領域の前記第1主面側に設けられ、当該第2導電型領域よりも高い不純物濃度を有する第2導電型ベース領域と、
前記第1導電型領域の前記第1主面側に設けられ、前記第2導電型ベース領域の前記第2主面側の端部よりも当該第2主面側に位置し、当該第1導電型領域の当該第2主面側の不純物濃度よりも高い不純物濃度を有する第1導電型高濃度領域と、
を備えることを特徴とする半導体装置。 - 前記第1導電型高濃度領域は、前記第2導電型ベース領域の前記第2主面側の端部から前記第2導電型領域の第2主面側の端部までの深さに位置する前記第1導電型領域のうち、当該第1導電型高濃度領域を除く領域の1.2倍以上3倍以下の不純物濃度を有することを特徴とする請求項1に記載の半導体装置。
- 前記第1導電型領域の前記第1主面側に設けられ、前記第1導電型高濃度領域の前記第1主面側の端部に接する第1導電型表面領域を、さらに備えることを特徴とする請求項1に記載の半導体装置。
- 前記第1導電型表面領域は、前記第2導電型ベース領域と同じ深さ、または前記第2導電型ベース領域よりも前記第1主面側に浅く設けられていることを特徴とする請求項3に記載の半導体装置。
- 前記第1導電型表面領域は、前記第1導電型高濃度領域よりも高い不純物濃度を有することを特徴とする請求項3に記載の半導体装置。
- 前記第1導電型高濃度領域は、前記第1導電型表面領域も含めて、前記第2導電型ベース領域の第2主面側の端部から前記第2導電型領域の第2主面側の端部までの深さに位置する前記第1導電型領域のうち、当該第1導電型高濃度領域を除く領域の1.2倍以上3倍以下の不純物濃度を有することを特徴とする請求項3に記載の半導体装置。
- 前記第1導電型高濃度領域は、前記第2導電型ベース領域の前記第2主面側の端部から前記第2導電型領域の第2主面側の端部までの深さに位置する前記第1導電型領域の厚さの1/3以下の厚さを有することを特徴とする請求項1に記載の半導体装置。
- 前記第1導電型高濃度領域は、前記第2導電型ベース領域の前記第2主面側の端部から前記第2導電型領域の第2主面側の端部までの深さに位置する前記第1導電型領域の厚さの1/8以上1/4以下の厚さを有することを特徴とする請求項1に記載の半導体装置。
- 前記第1導電型高濃度領域は、前記第2導電型領域のうち当該第1導電型高濃度領域の隣接する領域の1.2倍以上3倍以下の不純物濃度を有することを特徴とする請求項1に記載の半導体装置。
- 前記第2導電型領域のうち、前記第2主面側の不純物濃度よりも高い不純物濃度を有する前記第1主面側の第2導電型高濃度領域を、さらに備えることを特徴とする請求項1に記載の半導体装置。
- 前記第1導電型高濃度領域は、前記第2導電型ベース領域の前記第2主面側の端部から前記第2導電型領域の第2主面側の端部までの深さに位置する前記第1導電型領域のうち、当該第1導電型高濃度領域を除く領域の1.5倍以上3倍以下の不純物濃度を有することを特徴とする請求項10に記載の半導体装置。
- 前記第2導電型高濃度領域は、前記第2導電型領域の厚さの1/8以上1/2以下の厚さを有することを特徴とする請求項10に記載の半導体装置。
- 前記第2導電型高濃度領域は、前記第1導電型高濃度領域と同じ厚さを有することを特徴とする請求項10に記載の半導体装置。
- 前記第2導電型領域のうち前記第2導電型高濃度領域を除く領域は、前記第1導電型領域のうち前記第1導電型高濃度領域を除く領域と同じ不純物量を有することを特徴とする請求項10に記載の半導体装置。
- 前記第2導電型領域のうち前記第2導電型高濃度領域を除く領域は、前記第1主面側から前記第2主面側にかけて、不純物濃度が徐々に低くなっていることを特徴とする請求項10に記載の半導体装置。
- 前記第1導電型高濃度領域および前記第2導電型高濃度領域が、前記第1主面側から前記第2主面側にかけて、不純物濃度が徐々に低くなっていることを特徴とする請求項10に記載の半導体装置。
- 前記第2導電型高濃度領域は、前記第1導電型高濃度領域の前記第2主面側の端部よりも当該第2主面側に深く設けられていることを特徴とする請求項10に記載の半導体装置。
- 前記第2導電型高濃度領域のうち、前記第1導電型高濃度領域の前記第2主面側の端部よりも当該第2主面側に深く設けられている領域は、当該領域の隣接する前記第1導電型領域よりも高い不純物濃度を有し、かつ当該第2導電型高濃度領域よりも低い不純物濃度を有することを特徴とする請求項17に記載の半導体装置。
- 前記第2導電型高濃度領域のうち、前記第1導電型高濃度領域の前記第2主面側の端部よりも当該第2主面側に深く設けられている領域は、当該領域の隣接する前記第1導電型領域の1.2倍以上の不純物濃度を有することを特徴とする請求項17に記載の半導体装置。
- 前記第1導電型領域および前記第2導電型領域の平面形状は、ストライプ状、六方格子状または正方状であることを特徴とする請求項1~19のいずれか一つに記載の半導体装置。
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US20140110779A1 (en) * | 2012-10-24 | 2014-04-24 | Renesas Electronics Corporation | Vertical power mosfet |
JP2014086569A (ja) * | 2012-10-24 | 2014-05-12 | Renesas Electronics Corp | 縦型パワーmosfet |
JP2014179595A (ja) * | 2013-02-14 | 2014-09-25 | Fuji Electric Co Ltd | 半導体装置およびその製造方法 |
US9035376B2 (en) | 2013-02-14 | 2015-05-19 | Fuji Electric Co., Ltd. | Semiconductor device and method of manufacturing the same |
US9048250B2 (en) | 2013-02-25 | 2015-06-02 | Fuji Electric Co., Ltd. | Method of manufacturing a super-junction semiconductor device |
JP2014165306A (ja) * | 2013-02-25 | 2014-09-08 | Fuji Electric Co Ltd | 超接合半導体装置の製造方法 |
JP2015233089A (ja) * | 2014-06-10 | 2015-12-24 | 株式会社サイオクス | 化合物半導体素子用エピタキシャルウェハ及び化合物半導体素子 |
JP2019054169A (ja) * | 2017-09-15 | 2019-04-04 | 株式会社東芝 | 半導体装置 |
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JPWO2011093473A1 (ja) | 2013-06-06 |
JP5652407B2 (ja) | 2015-01-14 |
EP2530721A1 (en) | 2012-12-05 |
CN102804386A (zh) | 2012-11-28 |
US9087893B2 (en) | 2015-07-21 |
EP2530721A4 (en) | 2017-11-29 |
US20130026560A1 (en) | 2013-01-31 |
CN102804386B (zh) | 2016-07-06 |
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