WO2022062941A1 - 一种功率器件及其制作方法 - Google Patents

一种功率器件及其制作方法 Download PDF

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Publication number
WO2022062941A1
WO2022062941A1 PCT/CN2021/118046 CN2021118046W WO2022062941A1 WO 2022062941 A1 WO2022062941 A1 WO 2022062941A1 CN 2021118046 W CN2021118046 W CN 2021118046W WO 2022062941 A1 WO2022062941 A1 WO 2022062941A1
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layer
trench
photolithography
gate
power device
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PCT/CN2021/118046
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English (en)
French (fr)
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张景超
赵善麒
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江苏宏微科技股份有限公司
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Publication of WO2022062941A1 publication Critical patent/WO2022062941A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the invention relates to the technical field of semiconductors, in particular to a power device and a manufacturing method thereof.
  • SiC material Compared with Si material, SiC material has 10 times the critical breakdown electric field.
  • the thickness of the drift region of the device can be greatly reduced, the doping concentration can also be increased, and the drift region resistance of the device can be greatly reduced. can be reduced by a factor of 1000, making SiC a very attractive semiconductor material for the development of high voltage power MOSFET devices.
  • FIG. 1 and FIG. 2 show the structure of a trench-type MOSFET power device in the prior art, wherein the trench 21' is a polysilicon gate 211' and a gate oxide layer 212', and the N+ regions on both sides of the trench 21'
  • the source is connected, the N-drift region 12' under the P- region is connected to the drain through the N+ substrate 11', and after the gate voltage is applied, the region in the P- region near the sidewall of the trench 21' is inversion, forming Conductive channel, at this time, the conduction between the drain and the source can be achieved, and the channel current I' flows from the drain to the source from bottom to top, but is limited by the width to length ratio of the channel, resulting in a relatively high channel resistance.
  • the thermally grown gate oxide layer 212' and the low surface quality of the SiC surface make the mobility of the inversion layer only 5% of that in the body-
  • the high electric field in the SiC material generates a strong electric field in the gate oxide layer 212', which is easy to cause the gate oxide layer 212' to burn.
  • the present invention provides a power device, which increases the width of the conductive channel and reduces the channel resistance.
  • a power device including:
  • N base N base
  • P- epitaxial layer is formed on the N base, and a groove is provided in the P- epitaxial layer
  • a gate at least a part of the gate is formed in the trench, and the gate extends along the arrangement direction of the first N+ layer and the second N+ layer, when a turn-on voltage is applied to the gate , the P-channel layer between the first N+ layer and the second N+ layer forms a lateral conductive channel.
  • the present invention is provided with a first N+ layer and a second N+ layer in the P- epitaxial layer, and the first N+ layer and the second N+ layer are separated by the P- type semiconductor in the P- epitaxial layer, and at the same time, the first N+ layer and The source is electrically connected, and the second N+ layer is electrically connected to the drain, so that after the gate voltage is applied, an inversion layer appears in the P-channel layer, and current flows laterally between the first N+ layer and the second N+ layer , it is foreseeable that increasing the depth of the trench and simultaneously increasing the depth of the first N+ layer and the second N+ layer is equivalent to increasing the width of the channel, thereby reducing the channel resistance.
  • the on-current flows into the second N+ layer from bottom to top through the drain, then flows through the inversion layer formed by the P-channel layer, flows laterally into the first N+ layer, and then flows out of the source, at the bottom of the trench and the N base
  • a reverse-biased PN junction can be formed, which can protect the gate oxide layer at the bottom of the inner wall of the trench.
  • the P-type semiconductor in the P- epitaxial layer between the trench bottom and the N body does not affect the on-current path.
  • the first N+ layer and the N matrix are separated by a first P+ layer, and at least a part of the first P+ layer is formed in the P- epitaxial layer or at least a part is formed in the N In the substrate, the first P+ layer formed by high doping makes the above-mentioned reverse biased PN junction less likely to break down and better protects the bottom of the gate oxide layer.
  • a first P+ layer is formed between the second N+ layer and the bottom of the trench, and the first P+ layer wraps the bottom and sides of the bottom of the trench.
  • the first P+ layer will pinch off the voltage of the second N+ layer, so that the voltage between the second N+ layer and the gate oxide layer is reduced, and the sidewall of the gate oxide layer is protected.
  • the bottom end of the first N+ layer is higher than the bottom end of the trench, and in the P- epitaxial layer, the regions located at the bottom of the trench and the side of the bottom are formed with the first N+ layer.
  • a P+ layer is
  • a second P+ layer is formed on the outer surfaces of the first N+ layer and the P- channel layer, and the second P+ layer makes it easier to turn off the power device of the present invention.
  • an insulating dielectric layer is further provided on the trench, a third P+ layer is formed between the insulating dielectric layer and the second N+ layer, and the third P+ layer can prevent the second N+ layer and the source electrode Connected.
  • first N+ layers and the second N+ layers are staggered along the arrangement direction of the first N+ layer and the second N+ layer on the outside of the sidewall of the trench, and any two of the first N+ layers and the second N+ layers are alternately arranged.
  • the first N+ layer and the second N+ layer are all isolated by the P-channel layer, and the first N+ layer, the second N+ layer, and the P-channel layers on both sides of the second N+ layer are formed into a group to The group extends in the arrangement direction as a unit.
  • the materials of the N substrate and the P-epitaxial layer are both SiC. Due to the low surface quality of the thermally grown oxide layer and the SiC surface, the mobility of the inversion layer is only 5%-10% of that in the body, making the device channel The channel resistance is very high, and the present invention is applied to power devices made of SiC material, and the effect is more obvious, and the channel resistance and on-resistance can be better reduced. Not limited to SiC, the above-mentioned beneficial effects can also be produced when other materials are used.
  • Another aspect of the present invention provides a method for manufacturing the above power device, comprising the following steps:
  • S2 adopt an etching process to define a trench region in the P-epitaxial layer lithography, and perform etching to form a trench;
  • the area to be implanted is defined by photolithography, and nitrogen ions or phosphorus ions are implanted into the corresponding area of the sidewall of the trench using a specific implantation angle to form the sidewall layer of the first N+ layer.
  • this method forms the sidewall layers of the first P+ layer and the first N+ layer by first etching the channel and then implanting impurities from the channel, which reduces the difficulty of the process and facilitates manufacturing. processing.
  • this method also includes the following steps:
  • S5 adopt a thermal oxidation process, and use thermal oxidation to grow a layer of oxide layer on the inner surface of the trench to form a gate oxide layer;
  • S6 adopt a deposition process, deposit a layer of polysilicon on the gate oxide layer, fill the trench, and form a polysilicon gate;
  • S8 adopt photolithography and ion implantation process, photolithography defines the region to be implanted, and implants nitrogen ions or phosphorus ions into the corresponding regions on the surface of the P- epitaxial layer to form the surface layer of the first N+ layer;
  • photolithography defines the second P+ layer region that needs to be implanted, and utilizes different implantation energies to implant aluminum ions into corresponding regions of different depths to form the second P+ layer;
  • photolithography defines the second N+ layer region to be implanted, and using different implantation energies to implant nitrogen ions or phosphorus ions into corresponding regions of different depths to form the second N+ layer;
  • photolithography defines the third P+ layer region that needs to be implanted, and the third P+ layer is formed by implanting aluminum ions;
  • S12 adopt a deposition process to deposit a layer of insulating dielectric layer on the surface of the polysilicon gate, as the electrical isolation between the polysilicon gate and the metal electrode;
  • S14 adopt a deposition process to deposit a layer of metal on the insulating dielectric layer
  • S15 using an etching process, photolithography defines the source metal layer domain, the drain metal layer domain and the gate metal layer domain, and performs etching to form the source electrode, drain electrode and gate electrode of the power device .
  • Another aspect of the present invention provides another method for manufacturing the above power device, comprising the following steps:
  • the region to be implanted is defined by photolithography, and nitrogen ions or phosphorus ions are implanted into different depths of the corresponding regions by using different implantation energies to form the layer domain along the depth direction in the first N+ layer;
  • photolithography defines the second P+ layer region that needs to be implanted, and utilizes different implantation energies to implant aluminum ions into corresponding regions of different depths to form the second P+ layer;
  • photolithography defines the second N+ layer region to be implanted, and nitrogen ions or phosphorus ions are implanted into corresponding regions of different depths using different implantation energies to form the second N+ layer.
  • the steps S1-S4 can be repeated as many times as needed, which facilitates the injection of corresponding impurities, reduces the difficulty of the process, and facilitates manufacturing and processing.
  • Another kind of preparation method of the present invention also comprises the following steps:
  • S5 adopt an etching process, define a trench region in the P-epitaxial layer lithography, and perform etching to form a trench;
  • S6 adopt the ion implantation process, and utilize the implantation angle to selectively implant aluminum ions into the bottom of the trench and the corresponding regions on the side of the bottom to form a first P+ layer;
  • S7 adopt a thermal oxidation process, and use thermal oxidation to grow a layer of oxide layer on the inner surface of the trench to form a gate oxide layer;
  • S8 adopt a deposition process, deposit a layer of polysilicon on the gate oxide layer, fill the trench, and form a polysilicon gate;
  • photolithography defines the region that needs to be implanted, and implants nitrogen ions or phosphorus ions into the corresponding regions on the surface of the P- epitaxial layer to form the surface layer of the first N+ layer;
  • photolithography defines the third P+ layer region that needs to be implanted, and the third P+ layer is formed by implanting aluminum ions;
  • S12 adopt a deposition process to deposit a layer of insulating dielectric layer on the surface of the polysilicon gate, as the electrical isolation between the polysilicon gate and the metal electrode;
  • S14 adopt a deposition process to deposit a layer of metal on the insulating dielectric layer
  • S15 using an etching process, photolithography defines the source metal layer domain, the drain metal layer domain and the gate metal layer domain, and performs etching to form the source electrode, drain electrode and gate electrode of the power device .
  • a power device with another structure including:
  • an N-epitaxial layer is formed on the P base, and a groove is provided in the N-epitaxial layer;
  • the N- epitaxial layer is formed with mutually isolated P+1 layer and P+2 layer, the P+1 layer is electrically connected to the source located on the surface of the N- epitaxial layer, the P+1 layer is The +2 layer is electrically connected to the drain at the bottom of the P base;
  • a gate at least a part of the gate is formed in the trench, and the gate extends along the arrangement direction of the P+1 layer and the P+2 layer, when a turn-on voltage is applied to the gate , the N-channel layer between the P+1 layer and the P+2 layer forms a lateral conductive channel.
  • a power device provided by the present invention has the following beneficial effects:
  • a first N+ layer and a second N+ layer are provided outside the sidewall of the trench, and the first N+ layer and the second N+ layer are separated by a P-channel layer formed by a P- epitaxial layer, and at the same time , the first N+ layer is connected to the source electrode, and the second N+ layer is connected to the drain electrode.
  • an inversion layer appears in the P-channel layer, and the current flows into the second N+ layer from bottom to top. , laterally flows into the inversion layer, then flows into the first N+ layer, and then flows out of the source.
  • the present invention uses the first P+ layer at the bottom of the trench to protect the gate oxide layer, so that a PN junction is formed by the N base and the first P+ layer, and the high electric field of the drain is equivalent to being applied to the two PN junctions.
  • the reverse voltage at the end, that is, the high electric field is mainly borne by the PN junction, which greatly reduces the electric field strength outside the gate oxide layer, especially at the bottom and bottom corners of the trench, and prevents the gate oxide layer from burning under high electric field strength.
  • FIG. 1 is a front view of a trench MOSFET power device in the prior art
  • FIG. 2 is a cross-sectional view of a trench-type MOSFET power device in the prior art taken along a plane parallel to XY, and simultaneously along the edge of the trench sidewall;
  • FIG. 3 is a cross-sectional view of the power device according to Embodiment 1 when the first N+ layer is cut along a plane parallel to XY and at the same time along the edge of the trench sidewall;
  • Embodiment 4 is a cross-sectional view of the power device according to Embodiment 1 cutting the P-channel layer along a plane parallel to XY, and at the same time cutting along the edge of the trench sidewall;
  • FIG. 5 is a cross-sectional view of the power device according to the first embodiment, which is cut along a plane parallel to XY and cut along the second N+ layer, and at the same time cut along the edge of the sidewall of the trench;
  • Example 6 is a cross-sectional view of a P-channel layer in another implementation manner of the power device of Example 1;
  • FIG. 7 is a cross-sectional view of the second N+ layer in another implementation manner of the power device of the first embodiment
  • FIG. 8 is a cross-sectional view of the power device according to Embodiment 4, in which the first N+ layer is cut along a plane parallel to XY, and at the same time, along the edge of the trench sidewall;
  • FIG. 9 is a cross-sectional view of the power device according to Embodiment 5, in which the first N+ layer is cut along a plane parallel to XY, and at the same time, along the edge of the trench sidewall;
  • FIG. 10 is a cross-sectional view of the power device according to Embodiment 6, in which the first N+ layer is cut along a plane parallel to XY, and at the same time, along the edge of the sidewall of the trench;
  • FIG. 11 is a cross-sectional view of the power device according to Embodiment 7, with the first N+ layer being cut along a plane parallel to XY, and at the same time being cut along the edge of the sidewall of the trench;
  • FIG. 12 is a cross-sectional view of the power device of the embodiment 8 along the plane parallel to XY cutting the first N+ layer, and simultaneously cutting along the edge of the trench sidewall;
  • FIG. 13 is a cross-sectional view of the power device according to the eighth embodiment, where the P-channel layer is cut along a plane parallel to XY, and at the same time, along the edge of the trench sidewall;
  • FIG. 14 is a cross-sectional view of the power device according to Embodiment 8 when the second N+ layer is cut along a plane parallel to XY, and at the same time, along the edge of the sidewall of the trench;
  • FIG. 15 is a cross-sectional view of the power device according to the ninth embodiment, where the P+1 layer is cut along a plane parallel to XY, and at the same time, it is cut along the edge of the sidewall of the trench.
  • N- epitaxial layer 61 P+1 layer 62 , P+2 layer 63 , N- channel layer 64 , N+1 layer 65 , N+2 layer 66 , N+3 layer 67 .
  • orientations indicated by orientation words such as “front, rear, top, bottom, left, right", “horizontal, vertical, vertical, horizontal” and “top, bottom” etc.
  • positional relationship is usually based on the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, and these orientations do not indicate or imply the indicated device or element unless otherwise stated. It must have a specific orientation or be constructed and operated in a specific orientation, so it cannot be construed as a limitation on the protection scope of the present invention; the orientation words “inside and outside” refer to the inside and outside relative to the outline of each component itself.
  • spatially relative terms such as “on”, “over”, “on the surface”, “above”, etc. may be used herein to describe what is shown in the figures.
  • spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “above” or “over” other devices or features would then be oriented “below” or “over” the other devices or features under other devices or constructions”.
  • the exemplary term “above” can encompass both an orientation of “above” and “below.”
  • the device may also be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptions used herein interpreted accordingly.
  • the power device in this embodiment is a MOSFET power device.
  • the power device in this embodiment includes an N base 1 and a P- epitaxial layer 2 extending from the N base 1 , an N base 1 and a P- epitaxial layer 2
  • the materials are all SiC, wherein, the N base 1 includes an N+ substrate 11 and an N-drift region 12, the N+ substrate 11 is connected to the drain 5, the N-drift region 12 extends the above-mentioned P- epitaxial layer 2, P- A trench 21 is provided in the epitaxial layer 2, an insulating dielectric layer 3 and a source electrode 4 are provided above the trench 21, and the whole is formed into a trench type MOSFET power device, but its specific structure is different from the prior art.
  • the outer sidewall of the trench 21 is provided with a first N+ layer 22 and a second N+ layer 23 isolated from each other along the length direction of the trench 21 (Z direction in FIG. 3 ).
  • the first N+ layer 22 and the second N+ layer 23 have a certain distance, and are separated by a P-channel layer 24.
  • FIG. -Semiconductor formation after the gate 211 applies the turn-on voltage, the region of the P-channel layer 24 close to the sidewall of the trench 21 is inversion, forming a lateral (Z direction in FIG. 3) conductive channel, so that the first N+ layer 22 And the second N+ layer 23 is turned on.
  • the first N+ layer 22 is electrically connected to the source electrode 4 located on the upper surface of the P- epitaxial layer 2.
  • the second N+ layer 23 passes through the N- drift region 12 and the N+ liner.
  • the bottom 11 is electrically connected to the drain electrode 5 , so that the conductive paths of the drain electrode 5 , the second N+ layer 23 , the inversion layer formed in the P-channel layer 24 , the first N+ layer 22 , and the source electrode 4 are formed.
  • the thickness of the second N+ layer 23 (the Y direction in FIG. 3 ) is relatively thick. In the prior art, the channel current directly flows in the inversion layer, and the thickness of the inversion layer is very thin.
  • the resistance at the second N+ layer 23 in this embodiment is very small.
  • the first N+ layer 22 in this embodiment also has a certain thickness, so that the resistance of this part is also small compared to the prior art.
  • the width (ie thickness, Y direction in FIG. 3 ) of the conductive channel formed after the inversion of the P-channel layer 24 is the same as that in the prior art, when the trench 21 , the first N+ layer 22 and the second When the N+ layer 23 continues to extend along the X direction in FIG.
  • the depth of the conductive channel is also further extended, which is equivalent to increasing the width of the conductive channel, so that the channel resistance gradually decreases, and the on-resistance of the entire device also gradually increases.
  • the conductive channel length (Z direction in FIG. 3 ) of this embodiment is shorter, so that the channel resistance is further reduced.
  • the first N+ layer 22 and the second N+ layer 23 are provided on the outside of the sidewall of the trench 21 along the length direction of the trench 21, and the first N+ layer 22 and the second N+ layer 23 are composed of The P-channel layer 24 formed by the P-type semiconductor in the P-epitaxial layer 2 is separated.
  • the first N+ layer 22 is connected to the source electrode 4, and the second N+ layer 23 is connected to the drain electrode 5.
  • the P-channel layer 24 is inverted, and the on-current I flows into the second N+ layer 23 from bottom to top, then flows laterally into the inversion layer, then flows into the first N+ layer 22, and then flows out of the source 4 , by increasing the depth of the trench 21, the first N+ layer 22 and the second N+ layer 23, it is equivalent to increasing the width of the conductive channel, thereby reducing the channel resistance.
  • the bottom end of the first N+ layer 22 is higher than the N-drift region 12, so that the two are separated by the P- semiconductor in the P- epitaxial layer 2. If the two are in direct contact, they will Directly form the conduction path of the drain 5, the N+ substrate 11, the N-drift region 12, the first N+ layer 22, and the source 4, then no matter whether the gate 211 has a voltage applied or not, it will be directly turned on, and the power device will be lost. switch function.
  • the first end of the first N+ layer 22 in this embodiment is electrically connected to the source electrode 4 , and the second end, that is, the bottom end, is higher than the bottom end of the trench 21 , which is convenient for the gate
  • the bottom of the oxide layer 212 is protected.
  • the bottom and bottom sides of the trench 21 are both P-semiconductor.
  • the P-semiconductor and the N-drift region 12 are equivalent to forming a reverse bias under the high electric field of the drain 5.
  • the PN junction is placed, and the high electric field generated by the drain 5 is borne by the PN junction, which can protect the bottom and bottom sides of the gate oxide layer 212 .
  • the P-semiconductor located at the bottom and the bottom side of the trench 21 in this embodiment will not affect the path of the on-current I, so it will not affect the path of the on-current I. will affect the on-resistance, and in the prior art, as shown in FIG. 2, the on-current flows up and down, and in the case of the same cross-sectional area (the plane where XY is located) of the device in this embodiment, if the bottom of the trench 21' Adding the same P-semiconductor to the bottom side as in Figure 3 can also protect the gate oxide to a certain extent, but obviously greatly increases the channel resistance.
  • the regions located at the bottom and the side of the bottom of the trench 21 are formed as the first P+ layer 25 , and the highly doped first P+ The layer 25 makes the above-mentioned reverse biased PN junction less likely to break down, and better protects the bottom and bottom sides of the gate oxide layer 212.
  • the N base 1 needs to be deepened at the same time. , and this embodiment adds protection to the gate oxide layer 212, so that the gate oxide layer 212 is not easily broken down, so the depth of the N base 1 (X direction in FIG. 3) can be appropriately reduced, so that the Device size reduction.
  • the N substrate 1 and the P-epitaxial layer 2 in this embodiment are both made of SiC material. Since SiC can withstand an electric field 10 times that of Si, the gate oxide layer is less likely to be broken down, and the depth of the N substrate 1 can be set to be smaller. Device size can be further reduced.
  • a first P+ layer 25 is formed between the second N+ layer 23 and the bottom of the trench 21 , and the first P+ layer 25 wraps the bottom and bottom sides of the trench 21 , and the device is turned off when the device is turned off.
  • the high electric field makes the depletion layer formed around the first P+ layer 25 very wide, which will pinch off the second N+ layer 23, so that the voltage between the second N+ layer 23 and the gate oxide layer in the trench sidewall region decreases.
  • the bottom and sidewalls of the gate oxide layer are protected at the same time, and since the gate oxide layer is isolated and protected, the trench and the first N+ layer in this embodiment can be further extended downward, further reducing the conduction On resistance.
  • a second P+ layer 26 is formed on the outer surfaces of the first N+ layer 22 and the P-channel layer 24 , and the highly doped second P+ layer 26 makes the P-channel layer
  • the residual minority carriers of 24 rapidly move to the first N+ layer 22, so that the MOSFET device of this embodiment is easier to turn off, and the turn-off speed is faster.
  • a source contact groove 41 that contacts the source electrode 4 is provided on the upper surface of the P- epitaxial layer.
  • An isolation region is arranged above the second N+ layer 23.
  • a third P+ layer 27 is arranged between the insulating dielectric layer 3 and the second N+ layer 23.
  • a third P+ layer 27 is also disposed between the insulating dielectric layer 3 and the P-channel layer 24 , and the bottom end of the third P+ layer 27 is lower than the bottom end of the source contact groove 41 .
  • the third P+ layer 27 may not be provided between the insulating dielectric layer 3 and the P-channel layer 24 , and only the insulating dielectric layer 3 and the second N+ A third P+ layer 27 is provided between the layers 23 .
  • a plurality of first N+ layers 22 and second N+ layers 22 and a plurality of second N+ layers 22 and 23 are alternately arranged on the outside of the sidewall of the trench 21 in this embodiment along the arrangement direction of the first N+ layers 22 and the second N+ layers 23 .
  • layer 23, and any two of the first N+ layers 22 and the second N+ layers 23 are isolated by the P-channel layer 24, the first N+ layer 22, the second N+ layer 23 and the second N+ layer 23.
  • the P-channel layers 24 are formed as a group and extend in the arrangement direction in units of the group to form a power device.
  • the materials of the N substrate 1 and the P- epitaxial layer 2 in this embodiment are both SiC, because SiC is not easily broken down, compared with other materials, the depth of the trench can be extended deeper, so that the on-resistance is smaller, but it needs to be Note that the materials of the N substrate 1 and the P- epitaxial layer 2 in this embodiment are not limited to SiC. When other materials are used, certain beneficial effects can also be produced, just because they are used in devices made of SiC materials. More obviously, it can effectively reduce the channel resistance and on-resistance, and solve the technical problem of high channel resistance caused by the low surface quality of SiC.
  • the power device in this embodiment is a U-type MOSFET
  • the device structure of the present invention is also applicable to V-type MOSFET and IGBT.
  • the power device provided by this embodiment increases the width of the conductive channel, reduces the channel resistance, and at the same time can protect the gate oxide layer and prevent the gate oxide layer from burning.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • This embodiment provides a method for manufacturing the power MOSFET device of the first embodiment, including the following steps:
  • the P- epitaxial layer 2 is obtained by epitaxy on the surface of the N base 1, and the N base 1 can be pre-doped to form an N+ substrate 11 and an N-drift region 12 as required;
  • a trench area is defined by photolithography in the P-epitaxial layer, and etching is performed to form a trench 21;
  • the area to be implanted is defined by photolithography, and nitrogen ions or phosphorus ions are implanted into the corresponding area of the sidewall of the trench 21 using a specific implantation angle to form the sidewall layer of the first N+ layer 22,
  • the sidewall layer is the layer region in the first N+ layer 22 close to the sidewall of the trench 21;
  • S6 adopt a deposition process, deposit a layer of polysilicon on the gate oxide layer 212, fill the trench 21, and form a polysilicon gate, where the polysilicon gate is the gate in the first embodiment;
  • the photolithography defines the area to be implanted, and implants nitrogen ions or phosphorus ions into the corresponding area on the surface of the P- epitaxial layer 2 to form the surface layer of the first N+ layer 22, and the surface layer is The layer domain of the above-mentioned sidewall layer is removed in the first N+ layer 22;
  • photolithography defines the second P+ layer region to be implanted, and utilizes different implantation energies to implant aluminum ions into corresponding regions of different depths to form the second P+ layer 26;
  • photolithography defines the second N+ layer region that needs to be implanted, and uses different implantation energies to implant nitrogen ions or phosphorus ions into corresponding regions of different depths to form the second N+ layer 23;
  • photolithography defines the third P+ layer region that needs to be implanted, and forms the third P+ layer 27 by implanting aluminum ions;
  • S12 adopt a deposition process to deposit a layer of insulating dielectric layer 3 on the surface of the polysilicon gate, as the electrical isolation between the polysilicon gate and the metal electrode;
  • the source metal layer domain, the drain metal layer domain and the gate metal layer domain are defined by photolithography, and etching is performed to form the source electrode, drain electrode and gate electrode of the device, which needs to be explained
  • the source electrode is the source electrode 4 in the first embodiment
  • the drain electrode is the drain electrode 5 in the first embodiment, which is formed by depositing metal on the lower surface of the N+ substrate 11
  • the gate electrode can be formed on the Termination in the Z direction in Figure 3.
  • steps S3-S9 can be re-adjusted according to needs.
  • the order of steps S4 and S5 can be changed, but the fabrication of the power device in this embodiment is not affected.
  • the trench 21 is first etched, and then impurities are injected from the trench 21 to form the sidewall layers of the first P+ layer 25 and the first N+ layer 22, which reduces the difficulty of the process and facilitates manufacturing.
  • This embodiment provides another method for manufacturing the MOSFET power device of the first embodiment, including the following steps:
  • the P- epitaxial layer 2 is obtained by epitaxy on the surface of the N base 1, and the N base 1 can be pre-doped to form an N+ substrate 11 and an N-drift region 12 as required;
  • the area to be implanted is defined by photolithography, and nitrogen ions or phosphorus ions are implanted into different depths of the corresponding area by using different implantation energies to form the layer domain along the depth direction in the first N+ layer 22 , where the layer domain along the depth direction is the sidewall layer of the first N+ layer in the second embodiment;
  • photolithography defines the second P+ layer region to be implanted, and utilizes different implantation energies to implant aluminum ions into corresponding regions of different depths to form the second P+ layer 26;
  • photolithography defines the second N+ layer region to be implanted, and nitrogen ions or phosphorus ions are implanted into corresponding regions of different depths using different implantation energies to form the second N+ layer 23;
  • steps S1-S4 can be repeated as many times as needed.
  • the first layer in the P- epitaxial layer 2 can be obtained by epitaxy in step S1 first, and the thickness of the first layer can be P - 1/M of the total thickness of the epitaxial layer 2 (X direction in Figure 3), M is a positive integer, then ion implantation is carried out through steps S2-S4, and then the second layer of the P- epitaxial layer 2 is prepared on the above-mentioned first layer. layer, the thickness of the second layer and each subsequent layer is 1/M of the total thickness of the P-epitaxial layer 2, and then ion implantation is carried out through steps S2-S4, and the cycle is carried out M times.
  • S1-S4 are repeatedly cycled for many times as required, which facilitates the deep implantation of ions, reduces the difficulty of the process, and facilitates manufacturing and processing.
  • a trench area is defined by photolithography in the P-epitaxial layer, and etching is performed to form a trench 21;
  • S8 adopt a deposition process, deposit a layer of polysilicon on the gate oxide layer 212, fill the trench 21, and form a polysilicon gate, where the polysilicon gate is the gate in the first embodiment;
  • photolithography defines the area to be implanted, and implants nitrogen ions or phosphorus ions into the corresponding area on the surface of the P- epitaxial layer to form the surface layer of the first N+ layer 22, where the surface layer and implementation The surface layer of the first N+ layer in Example 2 is the same;
  • S12 adopt a deposition process to deposit a layer of insulating dielectric layer 3 on the surface of the polysilicon gate, as the electrical isolation between the polysilicon gate and the metal electrode;
  • the source metal layer domain, the drain metal layer domain and the gate metal layer domain are defined by photolithography, and etching is performed to form the source electrode, drain electrode and gate electrode of the device, which needs to be explained
  • the source electrode is the source electrode 4 in the first embodiment
  • the drain electrode is the drain electrode 5 in the first embodiment, which is formed by depositing metal on the lower surface of the N+ substrate 11
  • the gate electrode can be formed on the Termination in the Z direction in Figure 3.
  • steps S2-S4 can be re-adjusted according to needs, for example, the order of steps S3 and S4 can be exchanged, but it does not affect the production of power devices; steps S6-S9 can be re-adjusted part of the order according to needs, for example, steps S6 and S7 can be exchanged order, but does not affect the fabrication of power devices.
  • Embodiment 4 is a diagrammatic representation of Embodiment 4:
  • the difference between the power device of this embodiment and the first embodiment is that, in this embodiment, a part of the first P+ layer 25 is formed in the N ⁇ drift region 12 .
  • Embodiment 5 is a diagrammatic representation of Embodiment 5:
  • the difference between the power device in this embodiment and the first embodiment is that, in this embodiment, the bottom end of the first N+ layer 22 is lower than the bottom end of the trench 21 , but higher than the N ⁇ drift region 12 , The first N+ layer 22 completely wraps the sidewalls and bottom of the trench 21 within its length (Z direction in FIG. 9 ).
  • Embodiment 6 is a diagrammatic representation of Embodiment 6
  • the difference between the power device of this embodiment and the fifth embodiment is that, in this embodiment, a part of the first P+ layer 25 may also be formed in the N ⁇ drift region 12 .
  • Embodiment 7 is a diagrammatic representation of Embodiment 7:
  • the difference between the power device in this embodiment and the first embodiment is that the top of the gate 211 in the trench 21 in this embodiment is lower than the upper surface of the P- epitaxial layer 2 , which saves the Instead of the insulating dielectric layer 3 in the first embodiment, the region above the gate electrode 211 in FIG. 11 is used as the insulating dielectric layer, which can save a certain amount of material and process costs.
  • the first N+ layer 22 in this embodiment does not need to be provided with a surface layer.
  • the manufacturing method saves the implantation process of the surface layer of the first N+ layer in the second embodiment, and reduces the source hole. The process difficulty of layer lithography.
  • Embodiment 8 is a diagrammatic representation of Embodiment 8
  • the difference between the power device in this embodiment and the first embodiment is that the top of the gate electrode 211 in the trench 21 in this embodiment exceeds the top of the P- epitaxial layer 2 and extends to both sides (Fig. 12) extending in the Y direction and the opposite direction of the Y direction), and as shown in FIG. 13, the top of the P-channel layer 24 also extends to the outside, as shown in FIG.
  • the P+ layer is isolated from the source electrode 4, which reduces the process cost.
  • the manufacturing method of the power device in this embodiment can not only cancel the implantation step of the third P+ layer, but also need to advance the implantation steps of the second N+ layer 23 and the second P+ layer 26 to Before the polysilicon gate is formed, otherwise, the second N+ layer 23 and the second P+ layer 26 cannot be formed by implantation after the polysilicon gate is formed.
  • the first N+ layer 22 in this embodiment includes two parts, one part is completely separated from the source electrode 4 as shown in FIG. 12 , and the other part is the same as in FIG. extremely contact.
  • the width of the conductive channel is further increased, and the on-resistance can be further reduced.
  • Embodiment 9 is a diagrammatic representation of Embodiment 9:
  • N-MOS trench MOSFETs
  • P-MOS trench MOSFETs
  • the structures of the two are basically the same, but the implanted impurities are different.
  • the power device of the first embodiment is similar to the N-MOS.
  • a P+1 layer 62 and a P+2 layer 63 isolated from each other are formed in the epitaxial layer 61, and the P+1 layer 62 and the P+2 layer 63 are separated by the N- semiconductor in the N- epitaxial layer 61, and the part of the N -
  • the semiconductor is formed as an N-channel layer 64, the P+1 layer 62 is electrically connected to the source electrode 4 located on the surface of the N- epitaxial layer 61, and the P+2 layer 63 is electrically connected to the drain electrode 5 located at the bottom of the P base 6.
  • a trench 21 is also formed in the N- epitaxial layer 61, a gate 211 is formed in the trench 21, and the gate 211 extends along the arrangement direction of the P+1 layer 62 and the P+2 layer 63.
  • the turn-on voltage is applied to the pole 211, the N-channel layer 64 between the P+1 layer 62 and the P+2 layer 63 forms a lateral conductive channel.
  • the on-current i flows from the source 4 through the P+1 layer 62 , and also flows laterally to the P+2 layer 63 in the N- epitaxial layer 61 , and then flows to the drain 5 through the P base 6 .
  • the channel resistance is reduced by deepening the depth of the trench.
  • the N+1 layer, the N+2 layer and the N+3 layer in this embodiment are all N-type highly doped, and the numbers 1, 2 and 3 are only for distinguishing from each other; the P+1 layer and P+2 layers are both P-type highly doped, and the numbers 1 and 2 are only for distinguishing from each other.
  • the top of the gate 211 is flush with the upper surface of the N- epitaxial layer 61 .
  • the top of the gate may be lower than N -
  • the upper surface of the epitaxial layer 61 may also be higher than the upper surface of the N- epitaxial layer 61 and extend to both sides.

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Abstract

本发明涉及半导体技术领域，具体涉及一种功率器件，包括N基体、P-外延层和栅极，所述N基体上形成P-外延层，所述P-外延层内设有沟槽，所述P-外延层内形成有相互隔离的第一N+层和第二N+层,所述第一N+层电连接位于所述P-外延层表面的源极，所述第二N+层电连接位于所述N基体底部的漏极，所述栅极至少一部分形成在所述沟槽内，且所述栅极沿着所述第一N+层和第二N+层的排布方向延伸，当所述栅极施加开启电压时，所述第一N+层和第二N+层之间的P-沟道层形成横向的导电沟道。本发明提供的一种功率器件，增加了导电沟道的宽度，降低了沟道电阻，同时可保护栅氧化层，防止栅氧化层烧毁。

Description

一种功率器件及其制作方法 技术领域
本发明涉及半导体技术领域，具体涉及一种功率器件及其制作方法。
背景技术
由于SiC材料与Si材料相比，具有10倍的临界击穿电场，在设计同等电压等级的MOSFET功率器件时，器件漂移区的厚度可以大大降低，掺杂浓度也可以提高，器件的漂移区电阻可以降低1000倍，因此SiC成为开发高压功率MOSFET器件的非常诱人的半导体材料。
图1和图2示出了现有技术中的沟槽型MOSFET功率器件的结构，其中，沟槽21’内为多晶硅栅211’和栅氧化层212’，沟槽21’两侧的N+区连接源极，P-区下方的N-漂移区12’通过N+衬底11’连接漏极，在栅极施加开启电压后，P-区中靠近沟槽21’侧壁的区域反型，形成导电沟道，此时可实现漏极和源极的导通，沟道电流I’由下往上从漏极流往源极，但是受限于沟道的宽长比，导致沟道电阻较高，在导通电阻中占很高的比重，尤其是在使用SiC作半导体材料时，热生长的栅氧化层212’与SiC表面的低表面质量使得反型层迁移率只有体内的5％-10％，使得器件沟道电阻很高；同时，在使用SiC作半导体材料时，SiC材料内的高电场在栅氧化层212’产生很强的电场，容易引起栅氧化层212’烧毁。
发明内容
本发明为解决现有技术中的MOSFET功率器件沟道电阻很高的技术问题，提供一种功率器件，增加了导电沟道的宽度，降低了沟道电阻。
本发明采用的技术方案：
一种功率器件，包括：
N基体，所述N基体上形成P-外延层，所述P-外延层内设有沟槽；
P-外延层，所述P-外延层内形成有相互隔离的第一N+层和第二N+层,所述第一N+层电连接位于所述P-外延层表面的源极，所述第二N+层电连接位于所述N基体底部的漏极；
栅极，所述栅极至少一部分形成在所述沟槽内，且所述栅极沿着所述第一N+层和第二N+层的排布方向延伸，当所述栅极施加开启电压时，所述第一N+层和第二N+层之间的P-沟道层形成横向的导电沟道。
本发明在P-外延层设有第一N+层和第二N+层，且第一N+层和第二N+层由P-外延层内的P-型半导体隔开，同时，第一N+层和源极电连接，第二N+层和漏极电连接，这样，在栅极施加开启电压后，P-沟道层出现反型层，电流在第一N+层和第二N+层之间横向流动，可以预见的是，增加沟槽深度，同时增加第一N+层和第二N+层的深度，便相当于增加了沟道的宽度，从而降低了沟道电阻。
同时，导通电流从下往上经漏极流入第二N+层后，经过P-沟道层形成的反型层，横向流入第一N+层，然后流出源极，在沟槽底部和N基体之间为P-型半导体，和N基体可形成一个反向偏置的PN结，可对沟槽内壁底部的栅氧化层进行保护。并且，由于导通电流方向从第二N+层横向流向第一N+层，P-外延层中在沟槽底部和N基体之间的P-型半导体不会影响到导通电流的路径。
进一步地，所述第一N+层和所述N基体之间通过第一P+层隔开，且所述第一P+层至少一部分形成在所述P-外延层中或者至少一部分形成在所述N基体中，经过高掺杂形成的第一P+层使得上述反向偏置的PN结更不容易击穿，更好地保护栅氧化层的底部。
进一步地，所述第二N+层和所述沟槽的底部之间形成有第一P+层，所述第一P+层包裹所述沟槽的底部及底部侧边，在器件关断状态下，第一P+层会夹断第二N+层的电压，使得第二N+层和栅氧化层之间的电压减小，保护了栅氧化层的侧壁。
可选地，所述第一N+层的底端高于所述沟槽的底端，且在所述P-外延层中，位于所述沟槽的底部以及底部侧边的区域均形成有第一P+层。
进一步地，所述第一N+层和所述P-沟道层的外表面均形成有第二P+层，第二P+层使得本发明的功率器件更容易关断。
可选地，所述沟槽上还设有绝缘介质层，所述绝缘介质层和所述第二N+层之间形成有第三P+层，第三P+层可防止第二N+层和源极连通。
进一步地，所述沟槽的侧壁外沿所述第一N+层和第二N+层的排布方向交错设置有多个所述第一N+层和第二N+层，且任意两个所述第一N+层和第二N+层之间均由所述P-沟道层隔离，第一N+层、第二N+层和第二N+层两侧的P-沟道层形成为一个组，以该组为一个单位向所述排布方向延伸。
优选地，所述N基体和所述P-外延层的材料均为SiC，由于热生长氧化层与SiC表面的低表面质量使得反型层迁移率只有体内的5％-10％，使器件沟道电阻很高，本发明应用在以SiC为材料制作的功率器件中，效果更加明显，可更好的降低沟道电阻和导通电阻，但是，本发明的N基体和P-外延层的材料并不局限于SiC，在使用其他材料时，也能产生上述有益效果。
本发明的另一方面，提供了一种制作上述功率器件的方法，包括以下步骤：
S1:采用外延工艺，在N基体表面外延制得P-外延层；
S2:采用刻蚀工艺，在所述P-外延层光刻定义出沟槽区域，并进行刻蚀，形成沟槽；
S3:采用离子注入工艺，利用注入角度选择性地将铝离子注入到所述沟槽底部及底部侧边相应区域形成第一P+层；
S4:采用光刻和离子注入工艺，首先光刻定义出需要注入的区域，利用特定注入角度注入氮离子或磷离子到所述沟槽侧壁相应区域,形成第一N+层的侧壁层。
由于离子需要被注入较深的深度，该种方法通过先刻蚀出沟道，然后从沟道内注入杂质形成第一P+层和第一N+层的侧壁层，减小了工艺的难度，便于制造加工。
进一步地，该种方法还包括以下步骤：
S5:采用热氧化工艺，在所述沟槽内表面使用热氧化生长一层氧化层，形成栅氧化层；
S6:采用淀积工艺，在所述栅氧化层上面淀积一层多晶硅，填充所述沟槽，形成多晶硅栅；
S7:采用光刻和刻蚀工艺，光刻定义需要的多晶硅栅层域，并刻蚀掉不需要的多晶硅；
S8:采用光刻和离子注入工艺，光刻定义出需要注入的区域，注入氮离子或磷离子到所述P-外延层表面相应区域，形成所述第一N+层的表面层；
S9:采用光刻和离子注入工艺，光刻定义出需要注入的第二P+层区域，利用不同注入能量将铝离子注入到不同深度相应区域形成所述第二P+层；
S10:采用光刻和离子注入工艺，光刻定义出需要注入的第二N+层区域，利用不同注入能量将氮离子或磷离子注入到不同深度相应区域形成所述第二N+层；
S11:采用光刻和离子注入工艺，光刻定义出需要注入的第三P+层区域，通过注入铝离子形成所述第三P+层；
S12:采用淀积工艺，在所述多晶硅栅表面淀积一层绝缘介质层，作为所述多晶硅栅与金属电极的电隔离；
S13:采用光刻和刻蚀工艺，光刻定义出有源层孔层和所述多晶硅栅上的孔层，并刻蚀掉所述绝缘介质层上不需要的部分；
S14:采用淀积工艺，在所述绝缘介质层上淀积一层金属；
S15:采用刻蚀工艺，光刻定义出源极金属层域、漏极金属层域和栅极金属层域，进行刻蚀，形成所述功率器件的源极电极、漏极电极和栅极电极。
本发明的又一方面，提供了另外一种制作上述功率器件的方法，包括以下步骤：
S1:采用外延工艺，在N基体表面外延制得P-外延层；
S2:采用光刻和离子注入工艺，首先光刻定义出需要注入的区域，利用不同注入能量注入氮离子或磷离子到相应区域的不同深度,形成第一N+层中沿深度方向的层域；
S3:采用光刻和离子注入工艺，光刻定义出需要注入的第二P+层区域，利用不同注入能量将铝离子注入到不同深度相应区域形成所述第二P+层；
S4:采用光刻和离子注入工艺，光刻定义出需要注入的第二N+层区域，利用不同注入能量将氮离子或磷离子注入到不同深度相应区域形成所述第二N+层。
优选地，所述步骤S1-S4可根据需要重复循环进行多次，便于注入相应的杂质，减小了工艺的难度，便于制造加工。
进一步地，本发明的另外一种制作方法还包括以下步骤：
S5:采用刻蚀工艺，在所述P-外延层光刻定义出沟槽区域，并进行刻蚀，形成沟槽；
S6:采用离子注入工艺，利用注入角度选择性地将铝离子注入到所述沟槽底部及底部侧边相应区域形成第一P+层；
S7:采用热氧化工艺，在所述沟槽内表面使用热氧化生长一层氧化层，形成栅氧化层；
S8:采用淀积工艺，在栅氧化层上面淀积一层多晶硅，填充所述沟槽，形成多晶硅栅；
S9:采用光刻和离子注入工艺，光刻定义出需要注入的区域，注入氮离子或磷离子到所述P-外延层表面相应区域，形成所述第一N+层的表面层；
S10:采用光刻和离子注入工艺，光刻定义出需要注入的第三P+层区域，通过注入铝离子形成所述第三P+层；
S11:采用光刻和刻蚀工艺，光刻定义需要的多晶硅栅层域，并刻蚀掉不需要的多晶硅；
S12:采用淀积工艺，在所述多晶硅栅表面淀积一层绝缘介质层，作为所述多晶硅栅与金属电极的电隔离；
S13:采用光刻和刻蚀工艺，光刻定义出有源层孔层和所述多晶硅栅上的孔层，并刻蚀掉所述绝缘介质层上不需要的部分；
S14:采用淀积工艺，在所述绝缘介质层上淀积一层金属；
S15:采用刻蚀工艺，光刻定义出源极金属层域、漏极金属层域和栅极金属层域，进行刻蚀，形成所述功率器件的源极电极、漏极电极和栅极电极。
本发明的再一方面，提供了另外一种结构的功率器件，包括：
P基体，所述P基体上形成N-外延层，所述N-外延层内设有沟槽；
N-外延层，所述N-外延层内形成有相互隔离的P+1层和P+2层,所述P+1层电连接位于所述N-外延层表面的源极，所述P+2层电连接位于所述P基体底部的漏极；
栅极，所述栅极至少一部分形成在所述沟槽内，且所述栅极沿着所述P+1层和P+2层的排布方向延伸，当所述栅极施加开启电压时，所述P+1层和P+2层之间的N-沟道层形成横向的导电沟道。
采用上述技术方案后，本发明提供的一种功率器件，具有以下有益效果：
(1)本发明在沟槽的侧壁外设有第一N+层和第二N+层，且第一N+层和第二N+层由P-外延层形成的P-沟道层隔开，同时，第一N+层和源极连接，第二N+层和漏极连接，这样，在栅极施加开启电压后，P-沟道层出现反型层，电流从下往上流入第二N+层后，横向流入反型层，再流入第一N+层，然后流出源极，通过增加沟槽深度，同时增加第一N+层的深度，便相当于增加了导电沟道的宽度，从而降低沟道电阻；
(2)本发明在沟槽的底部使用第一P+层对栅氧化层进行保护，这样由N基体和第一P+层便形成一个PN结，漏极的高电场相当于施加在该PN结两端的反向电压，即高电场主要由PN结承受，大大降低了栅氧化层外侧尤其是位于沟槽底部和底部转角处的电场强度，避免了栅氧化层在高电场强度下烧毁。
附图说明
图1为现有技术中的沟槽型MOSFET功率器件的主视图；
图2为现有技术中的沟槽型MOSFET功率器件沿平行于XY的平面剖开，并同时沿沟槽侧壁边缘剖开的剖视图；
图3为实施例一的功率器件沿平行于XY的平面剖开第一N+层，并同时沿沟槽侧壁边缘剖开的剖视图；
图4为实施例一的功率器件沿平行于XY的平面剖开P-沟道层，并同时沿沟槽侧壁边缘剖开的剖视图；
图5为实施例一的功率器件沿平行于XY的平面剖开第二N+层，并同时沿沟槽侧壁边缘剖开的剖视图；
图6为实施例一的功率器件的另一实施方式中剖开P-沟道层的剖视图；
图7为实施例一的功率器件的另一实施方式中剖开第二N+层的剖视图；
图8为实施例四的功率器件沿平行于XY的平面剖开第一N+层，并同时沿沟槽侧壁边缘剖开的剖视图；
图9为实施例五的功率器件沿平行于XY的平面剖开第一N+层，并同时沿沟槽侧壁边缘剖开的剖视图；
图10为实施例六的功率器件沿平行于XY的平面剖开第一N+层，并同时沿沟槽侧壁边缘剖开的剖视图；
图11为实施例七的功率器件沿平行于XY的平面剖开第一N+层，并同时沿沟槽侧壁边缘剖开的剖视图；
图12为实施例八的功率器件沿平行于XY的平面剖开第一N+层，并同时沿 沟槽侧壁边缘剖开的剖视图；
图13为实施例八的功率器件沿平行于XY的平面剖开P-沟道层，并同时沿沟槽侧壁边缘剖开的剖视图；
图14为实施例八的功率器件沿平行于XY的平面剖开第二N+层，并同时沿沟槽侧壁边缘剖开的剖视图；
图15为实施例九的功率器件沿平行于XY的平面剖开P+1层，并同时沿沟槽侧壁边缘剖开的剖视图。
其中，
N+衬底11’，N-漂移区12’，沟槽21’，多晶硅栅211’，栅氧化层212’，沟道电流I’；
N基体1，N+衬底11，N-漂移区12，P-外延层2，沟槽21，栅极211，栅氧化层212，第一N+层22，第二N+层23，P-沟道层24，第一P+层25，第二P+层26，第三P+层27，绝缘介质层3，源极4，源极接触槽41，漏极5，导通电流I；
P基体6，N-外延层61，P+1层62，P+2层63，N-沟道层64，N+1层65，N+2层66，N+3层67。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。以下对至少一个示例性实施例的描述实际上仅仅是说明性的，决不作为对本发明及其应用或使用的任何限制。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
需要注意的是，这里所使用的术语仅是为了描述具体实施方式，而非意图限制根据本申请的示例性实施方式。如在这里所使用的，除非上下文另外明确指出，否则单数形式也意图包括复数形式，此外，还应当理解的是，当在本说明书中使用术语“包含”和/或“包括”时，其指明存在特征、步骤、操作、器件、组件和/或它们的组合。
除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不限制本发明的范围。同时，应当明白，为了便于描述，附图中所示出的各个部分的尺寸并不是按照实际的比例关系绘制的。对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为授权说明书的一部分。在这里示出和讨论的所有示例中，任何具体值应被解释为仅仅是示例性的，而不是作为限制。因此，示例性实施例的其它示例可以具有不同的值。应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步讨论。
在本发明的描述中，需要理解的是，方位词如“前、后、上、下、左、右”、“横向、竖向、垂直、水平”和“顶、底”等所指示的方位或位置关系通常是基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，在未作相反说明的情况下，这些方位词并不指示和暗示所指的装置或元件必须具有特定的方位或者以特定的方位构造和操作，因此不能理解为对本发明保护范围的限制；方位词“内、外”是指相对于各部件本身的轮廓的内外。
为了便于描述，在这里可以使用空间相对术语，如“在……之上”、“在…… 上方”、“在……上表面”、“上面的”等，用来描述如在图中所示的一个器件或特征与其他器件或特征的空间位置关系。应当理解的是，空间相对术语旨在包含除了器件在图中所描述的方位之外的在使用或操作中的不同方位。例如，如果附图中的器件被倒置，则描述为“在其他器件或构造上方”或“在其他器件或构造之上”的器件之后将被定位为“在其他器件或构造下方”或“在其他器件或构造之下”。因而，示例性术语“在……上方”可以包括“在……上方”和“在……下方”两种方位。该器件也可以其他不同方式定位(旋转90度或处于其他方位)，并且对这里所使用的空间相对描述作出相应解释。
此外，需要说明的是，使用“第一”、“第二”等词语来限定零部件，仅仅是为了便于对相应零部件进行区别，如没有另行声明，上述词语并没有特殊含义，因此不能理解为对本发明保护范围的限制。
实施例一：
本实施例的功率器件为MOSFET功率器件，如图3所示，本实施例的功率器件包括N基体1和N基体1上延伸出的P-外延层2，N基体1和P-外延层2的材料均为SiC，其中，N基体1包括N+衬底11和N-漂移区12，N+衬底11和漏极5相连，N-漂移区12上延伸出上述P-外延层2，P-外延层2内设有沟槽21，沟槽21上方设有绝缘介质层3和源极4，整体形成为一个沟槽型MOSFET功率器件，但是其具体结构和现有技术不同。
具体地，参见图3，在本实施例中，沟槽21的侧壁外沿沟槽21长度方向(图3中Z方向)设有相互隔离的第一N+层22和第二N+层23，第一N+层22和第二N+层23具有一定间距，两者之间由P-沟道层24隔开，如图4所示，P-沟道层24由P-外延层2内的P-半导体形成，在栅极211施加开启电压后，P-沟道层24贴近沟槽21侧壁的区域反型，形成横向(图3中Z方向)的导电沟道，使得第一N+层22和第二N+层23导通。
进一步地，如图3所示，第一N+层22和位于P-外延层2上表面的源极4电连接，如图5所示，第二N+层23通过N-漂移区12和N+衬底11与漏极5电连接，这样，便形成了漏极5、第二N+层23、P-沟道层24中形成的反型层、第一N+层22、源极4的导电通道。如图5所示，第二N+层23的厚度(图3中Y方向)较厚，在现有技术中，沟道电流是直接在反型层内流动，而反型层的厚度非常薄，远小于本实施例的第二N+层23的厚度，因此相比较于现有技术，本实施例的第二N+层23处的电阻很小。同样，参见图3，本实施例的第一N+层22也具有一定的厚度，使得该部分电阻相比较于现有技术也很小。虽然在P-沟道层24反型后形成的导电沟道的宽度(即厚度，图3中Y方向)和现有技术中相同，但是，当沟槽21、第一N+层22和第二N+层23均沿图3中X方向继续延伸时，导电沟道的深度也在进一步延伸，相当于增加了导电沟道的宽度，使得沟道电阻逐渐减小，整个器件的导通电阻也逐渐减小，同时，本实施例的导电沟道长度(图3中Z方向)较短，使得沟道电阻进一步减小。
由以上内容可知，本实施例在沟槽21的侧壁外沿沟槽21的长度方向设有第一N+层22和第二N+层23，且第一N+层22和第二N+层23由P-外延层2内P-型半导体形成的P-沟道层24隔开，同时，第一N+层22和源极4连接，第二N+层23和漏极5连接，这样，在栅极211施加开启电压后，P-沟道层24反型，导通电流I从下往上流入第二N+层23后，横向流入反型层，再流入第一N+层22，然后流出源极4，通过增加沟槽21、第一N+层22和第二N+层23的深度，便相当于增加了导电沟道的宽度，从而降低了沟道电阻。
进一步地，如图3所示，第一N+层22的底端高于N-漂移区12，使得两者由P-外延层2内的P-半导体隔开，如果两者直接接触，便会直接形成漏极5、N+衬底11、N-漂移区12、第一N+层22、源极4的导通路径，那么无论栅极211有没有施加电压，均会直接导通，功率器件失去开关功能。
优选地，如图3-4所示，本实施例的第一N+层22的第一端和源极4电性连接，第二端即底端高于沟槽21的底端，便于对栅氧化层212的底部进行保护，具体地，沟槽21底部和底部侧边均为P-半导体，该P-半导体和N-漂移区12在漏极5的高电场下相当于形成一个反向偏置的PN结，漏极5产生的高电场由该PN结承受，可对栅氧化层212的底部和底部侧边进行保护。同时，由于电流方向从第二N+层23横向流向第一N+层22，本实施例中位于沟槽21底部和底部侧边的P-半导体不会影响到导通电流I的路径，也就不会影响导通电阻，而现有技术中，如图2，导通电流上下流动，在和本实施例的器件的截面积(XY所在平面)相同的情况下，如果在沟槽21’的底部和底部侧边增加和图3中一样的P-半导体，虽然也能一定程度上保护栅氧化层，但是很明显会大大增加沟道电阻。
进一步地，如图3-4所示，在本实施例的P-外延层2中，位于沟槽21的底部以及底部侧边的区域形成为第一P+层25，高掺杂的第一P+层25使得上述反向偏置的PN结更不容易击穿，更好的保护栅氧化层212的底部和底部侧边，同时，由于本实施例的沟槽深度加深时需要同时加深N基体1的深度，而本实施例对栅氧化层212增加了保护，使得栅氧化层212不容易被击穿，那么便可以适当缩小N基体1的深度(图3中X方向)，使得本实施例的器件尺寸减小。而且本实施例的N基体1和P-外延层2均使用SiC材料，由于SiC能耐受10倍于Si的电场，栅氧化层更不易被击穿，N基体1的深度可以设置更小，可进一步减小器件尺寸。
优选地，如图5所示，第二N+层23和沟槽21的底部之间形成有第一P+层25，第一P+层25包裹沟槽21的底部及底部侧边，在器件关断状态下，高电场使得第一P+层25周围形成的耗尽层非常宽，会夹断第二N+层23，使得第二N+层23和沟槽侧壁区域的栅氧化层之间的电压减小，这样便是同时保护了栅氧化层底部和侧壁，而且由于对栅氧化层进行了隔离和保护，使得本实施例的沟槽和第一N+层可以进一步向下延伸，进一步减小导通电阻。
进一步地，如图3-4所示，第一N+层22和P-沟道层24的外表面均形成有第二P+层26，高掺杂的第二P+层26使得P-沟道层24的残余少子迅速移动到第一N+层22，使得本实施例的MOSFET器件更容易关断，关断速度更快。
进一步地，如图3所示，本实施例在P-外延层的上表面设有和源极4接触的源极接触槽41，为了防止源极4和第二N+层23连通，本实施例在第二N+层23上方设置隔离区，如图5所示，在绝缘介质层3和第二N+层23之间设置有第三P+层27，同时，如图4所示，本实施例的绝缘介质层3和P-沟道层24之间也设置有第三P+层27，并且第三P+层27的底端低于所述源极接触槽41的底端。而在如图6-7所示的另一实施方式中，也可在绝缘介质层3和P-沟道层24之间不设置第三P+层27，仅在绝缘介质层3和第二N+层23之间设置第三P+层27。
进一步地，如图3所示，本实施例的沟槽21的侧壁外沿第一N+层22和第二N+层23的排布方向交错设置有多个第一N+层22和第二N+层23，且任意两个第一N+层22和第二N+层23之间均由P-沟道层24隔离，第一N+层22、第二N+层23和第二N+层23两侧的P-沟道层24形成为一组，以该组为一个单位向所述排布方向延伸，以形成功率器件。
本实施例的N基体1和P-外延层2的材料均为SiC，因为SiC不易被击穿，相对于其他材料，可以将沟槽深度延伸的更加深，使得导通电阻更加小，但是需要注意，本实施例的N基体1和P-外延层2的材料并不局限于SiC，在使用其他材料时，也能产生一定的有益效果，仅是因为用在SiC材料制作的器件中，效果更加明显，可有效降低沟道电阻和导通电阻，解决SiC低表面质量带来的沟道电阻很高的技术问题。
另外，需要说明的是，虽然本实施例的功率器件为U型MOSFET，但是，本领域的技术人员应当理解，本发明的器件结构同样适用于V型MOSFET和IGBT。
综上所述，本实施例提供的一种功率器件，增加了导电沟道的宽度，降低了沟道电阻，同时可保护栅氧化层，防止栅氧化层烧毁。
实施例二：
本实施例提供一种制造实施例一的功率MOSFET器件的方法，包括以下步骤：
S1:采用外延工艺，在N基体1表面外延制得P-外延层2，N基体1根据需要可预先掺杂形成N+衬底11和N-漂移区12；
S2:采用刻蚀工艺，在P-外延层光刻定义出沟槽区域，并进行刻蚀，形成沟槽21；
S3:采用离子注入工艺，在沟槽21底部，利用注入角度选择性地将铝离子注入到沟槽21底部及底部侧边相应区域形成第一P+层25；
S4:采用光刻和离子注入工艺，首先光刻定义出需要注入的区域，利用特定注入角度注入氮离子或磷离子到沟槽21侧壁相应区域,形成第一N+层22的侧壁层，该侧壁层即为第一N+层22中靠近沟槽21侧壁的层域；
S5:采用热氧化工艺，在沟槽21内表面使用热氧化生长一层氧化层，形成栅氧化层212；
S6:采用淀积工艺，在栅氧化层212上面淀积一层多晶硅，填充沟槽21，形成多晶硅栅，此处多晶硅栅即为实施例一中的栅极；
S7:采用光刻和刻蚀工艺，光刻定义需要的多晶硅栅层域，并刻蚀掉不需要的多晶硅；
S8:采用光刻和离子注入工艺，光刻定义出需要注入的区域，注入氮离子或磷离子到P-外延层2表面相应区域，形成第一N+层22的表面层，该表面层即为第一N+层22中除去上述侧壁层的层域；
S9:采用光刻和离子注入工艺，光刻定义出需要注入的第二P+层区域，利用不同注入能量将铝离子注入到不同深度相应区域形成第二P+层26；
S10:采用光刻和离子注入工艺，光刻定义出需要注入的第二N+层区域，利用不同注入能量将氮离子或磷离子注入到不同深度相应区域形成第二N+层23；
S11:采用光刻和离子注入工艺，光刻定义出需要注入的第三P+层区域，通过注入铝离子形成第三P+层27；
S12:采用淀积工艺，在多晶硅栅表面淀积一层绝缘介质层3，作为多晶硅栅与金属电极的电隔离；
S13:采用光刻和刻蚀工艺，光刻定义出有源层孔层和多晶硅栅上的孔层，并刻蚀掉绝缘介质层3上不需要的部分；
S14:采用淀积工艺，在绝缘介质层3上淀积一层金属；
S15:采用刻蚀工艺，光刻定义出源极金属层域、漏极金属层域和栅极金属层域，进行刻蚀，形成器件的源极电极、漏极电极和栅极电极，需要说明的是，源极电极即为实施例一中的源极4；漏极电极即为实施例一中的漏极5，在N+衬底 11的下表面淀积金属形成；栅极电极可形成在图3中Z方向的终端。
其中，步骤S3-S9可根据需要重新调整部分顺序，例如步骤S4和S5可调换顺序，但是并不影响本实施例的功率器件的制作。
本实施例通过先刻蚀出沟槽21，然后从沟槽21注入杂质形成第一P+层25和第一N+层22的侧壁层，减小了工艺的难度，便于制造加工。
实施例三：
本实施例提供另外一种制造实施例一的MOSFET功率器件的方法，包括以下步骤：
S1:采用外延工艺，在N基体1表面外延制得P-外延层2，N基体1根据需要可预先掺杂形成N+衬底11和N-漂移区12；
S2:采用光刻和离子注入工艺，首先光刻定义出需要注入的区域，利用不同注入能量注入氮离子或磷离子到相应区域的不同深度,形成第一N+层22中沿深度方向的层域，此处沿深度方向的层域即为实施例二中的第一N+层的侧壁层；
S3:采用光刻和离子注入工艺，光刻定义出需要注入的第二P+层区域，利用不同注入能量将铝离子注入到不同深度相应区域形成第二P+层26；
S4:采用光刻和离子注入工艺，光刻定义出需要注入的第二N+层区域，利用不同注入能量将氮离子或磷离子注入到不同深度相应区域形成第二N+层23；
由于离子需要注入的深度较深，步骤S1-S4可根据需要重复循环进行多次，如可以先通过步骤S1外延制得P-外延层2中的第一层，第一层的厚度可以为P-外延层2总厚度(图3中X方向)的1/M，M为正整数，然后通过步骤S2-S4进行离子注入，接着在上述第一层上制得P-外延层2的第二层，第二层以及之后的每一层的厚度均为P-外延层2总厚度的1/M，然后再通过步骤S2-S4进行离子注入，如此循环进行M次，该种方法通过将步骤S1-S4根据需要重复循环进行多次，便于离子的深度注入，减小了工艺的难度，便于制造加工。
S5:采用刻蚀工艺，在P-外延层光刻定义出沟槽区域，并进行刻蚀，形成沟槽21；
S6:采用离子注入工艺，在沟槽21底部，利用注入角度选择性地将铝离子注入到沟槽21底部及底部侧边相应区域形成第一P+层25；
S7:采用热氧化工艺，在沟槽21内表面使用热氧化生长一层氧化层，形成栅氧化层212；
S8:采用淀积工艺，在栅氧化层212上面淀积一层多晶硅，填充沟槽21，形成多晶硅栅，此处多晶硅栅即为实施例一中的栅极；
S9:采用光刻和离子注入工艺，光刻定义出需要注入的区域，注入氮离子或磷离子到P-外延层表面相应区域，形成第一N+层22的表面层，此处表面层和实施例二中的第一N+层的表面层相同；
S10:采用光刻和离子注入工艺，光刻定义出需要注入的第三P+层区域，通过注入铝离子形成第三P+层27；
S11:采用光刻和刻蚀工艺，光刻定义需要的多晶硅栅层域，并刻蚀掉不需要的多晶硅；
S12:采用淀积工艺，在多晶硅栅表面淀积一层绝缘介质层3，作为多晶硅栅与金属电极的电隔离；
S13:采用光刻和刻蚀工艺，光刻定义出有源层孔层和多晶硅栅上的孔层，并刻蚀掉绝缘介质层上不需要的部分；
S14:采用淀积工艺，在绝缘介质层3上淀积一层金属；
S15:采用刻蚀工艺，光刻定义出源极金属层域、漏极金属层域和栅极金属层域，进行刻蚀，形成器件的源极电极、漏极电极和栅极电极，需要说明的是，源极电极即为实施例一中的源极4；漏极电极即为实施例一中的漏极5，在N+衬底11的下表面淀积金属形成；栅极电极可形成在图3中Z方向的终端。
其中，步骤S2-S4可根据需要重新调整顺序，例如步骤S3和S4可调换顺序，但是并不影响功率器件的制作；步骤S6-S9可根据需要重新调整部分顺序，例如步骤S6和S7可调换顺序，但是并不影响功率器件的制作。
实施例四：
如图8所示，本实施例的功率器件和实施例一的区别在于，本实施中，第一P+层25的一部分形成在N-漂移区12中。
实施例五：
如图9所示，本实施例的功率器件和实施例一的区别在于，本实施中，第一N+层22的底端低于沟槽21的底端，但高于N-漂移区12，第一N+层22将在其长度(图9中Z方向)内的沟槽21的侧壁和底部全部包裹。
实施例六：
如图10所示，本实施例的功率器件和实施例五的区别在于，本实施中，第一P+层25的一部分也可形成在N-漂移区12中。
实施例七：
如图11所示，本实施例的功率器件和实施例一的区别在于，本实施例中的沟槽21内的栅极211的顶端低于P-外延层2的上表面，这样便可省去实施例一中的绝缘介质层3，而由图11中栅极211上方区域充当绝缘介质层，可节省一定的材料和工艺成本。同时，本实施例中的第一N+层22无需设置表面层，其制作方法相对于实施例二，节省了实施例二中第一N+层的表面层的注入工艺，并且减小了源极孔层光刻的工艺难度。
实施例八：
如图12所示，本实施例的功率器件和实施例一的区别在于，本实施例中的沟槽21内的栅极211的顶端超出P-外延层2的顶端，并且向两侧(图12中Y方向和Y方向的反方向)延伸，同时如图13所示，P-沟道层24顶端也向外侧延伸，如图14所示，第二N+层23上方也不需要设置第三P+层与源极4隔离，减小了工艺成本。
本实施例的功率器件的制作方法，和实施例二相比，除了可以取消第三P+层的注入步骤之外，同时还需要将第二N+层23和第二P+层26的注入步骤提前到形成多晶硅栅之前，否则在形成了多晶硅栅之后，便无法注入形成第二N+层23和第二P+层26。需要注意的是，本实施例的第一N+层22包括两部分，其中一部分如图12所示完全与源极4隔开，另一部分和图3中相同通过接触孔或接触槽的形式和源极接触。
本实施例由于栅极和P-沟道层的顶端均向两侧延伸，相当于进一步增加了导电沟道的宽度，可进一步减小导通电阻。
实施例九：
现有技术中的沟槽型MOSFET存在N-MOS和P-MOS两种，两者结构基本相同，只是注入的杂质不同，同样，实施例一的功率器件类似于N-MOS，那么，本领域的技术人员很容易想到和实施例一相对应的P-MOS，如图15所示，本实施例的功率器件包括P基体6和P基体6上延伸出的N-外延层61，在N-外延层61内形成有相互隔离的P+1层62和P+2层63，P+1层62和P+2层63由N-外延层61 内的N-半导体隔开，且该部分N-半导体形成为N-沟道层64，P+1层62电连接位于N-外延层61表面的源极4，P+2层63电连接位于P基体6底部的漏极5。
进一步地，N-外延层61内同样设有沟槽21，沟槽21内形成有栅极211，栅极211沿着P+1层62和P+2层63的排布方向延伸，当栅极211施加开启电压时，P+1层62和P+2层63之间的N-沟道层64形成横向的导电沟道。
本实施例中的导通电流i从源极4经过P+1层62，在N-外延层61内也是横向流动到P+2层63，再经过P基体6流到漏极5，同样可通过加深沟槽的深度以减小沟道电阻。
需要说明的是，本实施例中的N+1层、N+2层和N+3层均为N型高掺杂，其中的数字1、2和3仅是为了相互区分；P+1层和P+2层均为P型高掺杂，其中的数字1和2也仅是为了相互区分。
本实施例中的栅极211的顶端和N-外延层61的上表面齐平，可选地，和实施例八、实施例九类似，在其他实施例中，栅极的顶端可以低于N-外延层61的上表面，也可高于N-外延层61的上表面，并向两侧延伸。
以上所述，仅为本发明较佳的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，根据本发明的技术方案及其发明构思加以等同替换或改变，都应涵盖在本发明的保护范围之内。

Claims (14)

  1. 一种功率器件，其特征在于，包括：
    N基体(1)，所述N基体(1)上形成P-外延层(2)，所述P-外延层(2)内设有沟槽(21)；
    P-外延层(2)，所述P-外延层(2)内形成有相互隔离的第一N+层(22)和第二N+层(23),所述第一N+层(22)电连接位于所述P-外延层(2)表面的源极(4)，所述第二N+层(23)电连接位于所述N基体(1)底部的漏极(5)；
    栅极(211)，所述栅极(211)至少一部分形成在所述沟槽(21)内，且所述栅极(211)沿着所述第一N+层(22)和第二N+层(23)的排布方向延伸，当所述栅极(211)施加开启电压时，所述第一N+层(22)和第二N+层(23)之间的P-沟道层(24)形成横向的导电沟道。
  2. 根据权利要求1所述的一种功率器件，其特征在于，所述第一N+层(22)和所述N基体(1)之间通过第一P+层(25)隔开，所述第一P+层(25)至少一部分形成在所述P-外延层(2)中或者至少一部分形成在所述N基体(1)中。
  3. 根据权利要求1所述的一种功率器件，其特征在于，所述第二N+层(23)和所述沟槽(21)的底部之间形成有第一P+层(25)，所述第一P+层(25)包裹所述沟槽(21)的底部及底部侧边。
  4. 根据权利要求1所述的一种功率器件，其特征在于，所述第一N+层(22)的底端高于所述沟槽(21)的底端，且在所述P-外延层(2)中，位于所述沟槽(21)的底部以及底部侧边的区域均形成有第一P+层(25)。
  5. 根据权利要求1所述的一种功率器件，其特征在于，所述第一N+层(22)和所述P-沟道层(24)的外表面均形成有第二P+层(26)。
  6. 根据权利要求1所述的一种功率器件，其特征在于，所述沟槽(21)上还设有绝缘介质层(3)，所述绝缘介质层(3)和所述第二N+层(23)之间形成有第三P+层(27)。
  7. 根据权利要求1所述的一种功率器件，其特征在于，所述沟槽(21)的侧壁外沿所述第一N+层(22)和第二N+层(23)的排布方向交错设置有多个所述第一N+层(22)和第二N+层(23)，且任意两个所述第一N+层(22)和第二N+层(23)之间均由所述P-沟道层(24)隔离。
  8. 根据权利要求1所述的一种功率器件，其特征在于，所述N基体(1)和所述P-外延层(2)的材料均为SiC。
  9. 一种功率器件的制作方法，其特征在于，包括以下步骤：
    S1:采用外延工艺，在N基体(1)表面外延制得P-外延层(2)；
    S2:采用刻蚀工艺，在所述P-外延层(2)光刻定义出沟槽区域，并进行刻蚀，形成沟槽(21)；
    S3:采用离子注入工艺，利用注入角度选择性地将铝离子注入到所述沟槽(21)底部及底部侧边相应区域形成第一P+层(25)；
    S4:采用光刻和离子注入工艺，首先光刻定义出需要注入的区域，利用特定注入角度注入氮离子或磷离子到所述沟槽(21)侧壁相应区域,形成第一N+层(22)的侧壁层。
  10. 根据权利要求9所述的功率器件的制作方法，其特征在于，还包括以下步骤：
    S5:采用热氧化工艺，在所述沟槽(21)内表面使用热氧化生长一层氧化层，形成栅氧化层(212)；
    S6:采用淀积工艺，在所述栅氧化层(212)上面淀积一层多晶硅，填充所述 沟槽(21)，形成多晶硅栅；
    S7:采用光刻和刻蚀工艺，光刻定义需要的多晶硅栅层域，并刻蚀掉不需要的多晶硅；
    S8:采用光刻和离子注入工艺，光刻定义出需要注入的区域，注入氮离子或磷离子到所述P-外延层(2)表面相应区域，形成所述第一N+层(22)的表面层；
    S9:采用光刻和离子注入工艺，光刻定义出需要注入的第二P+层(26)区域，利用不同注入能量将铝离子注入到不同深度相应区域形成所述第二P+层(26)；
    S10:采用光刻和离子注入工艺，光刻定义出需要注入的第二N+层(23)区域，利用不同注入能量将氮离子或磷离子注入到不同深度相应区域形成所述第二N+层(23)；
    S11:采用光刻和离子注入工艺，光刻定义出需要注入的第三P+层(27)区域，通过注入铝离子形成所述第三P+层(27)；
    S12:采用淀积工艺，在所述多晶硅栅表面淀积一层绝缘介质层(3)，作为所述多晶硅栅与金属电极的电隔离；
    S13:采用光刻和刻蚀工艺，光刻定义出有源层孔层和所述多晶硅栅上的孔层，并刻蚀掉所述绝缘介质层(3)上不需要的部分；
    S14:采用淀积工艺，在所述绝缘介质层(3)上淀积一层金属；
    S15:采用刻蚀工艺，光刻定义出源极金属层域、漏极金属层域和栅极金属层域，进行刻蚀，形成所述功率器件的源极电极、漏极电极和栅极电极。
  11. 一种功率器件的制作方法，其特征在于，包括以下步骤：
    S1:采用外延工艺，在N基体(1)表面外延制得P-外延层(2)；
    S2:采用光刻和离子注入工艺，首先光刻定义出需要注入的区域，利用不同注入能量注入氮离子或磷离子到相应区域的不同深度,形成第一N+层(22)中沿深度方向的层域；
    S3:采用光刻和离子注入工艺，光刻定义出需要注入的第二P+层(26)区域，利用不同注入能量将铝离子注入到不同深度相应区域形成所述第二P+层(26)；
    S4:采用光刻和离子注入工艺，光刻定义出需要注入的第二N+层(23)区域，利用不同注入能量将氮离子或磷离子注入到不同深度相应区域形成所述第二N+层(23)。
  12. 根据权利要求11所述的功率器件的制作方法，其特征在于，所述步骤S1-S4可重复循环进行多次。
  13. 根据权利要求11所述的功率器件的制作方法，其特征在于，还包括以下步骤：
    S5:采用刻蚀工艺，在所述P-外延层(2)光刻定义出沟槽区域，并进行刻蚀，形成沟槽(21)；
    S6:采用离子注入工艺，利用注入角度选择性地将铝离子注入到所述沟槽(21)底部及底部侧边相应区域形成第一P+层(25)；
    S7:采用热氧化工艺，在所述沟槽(21)内表面使用热氧化生长一层氧化层，形成栅氧化层(212)；
    S8:采用淀积工艺，在所述栅氧化层(212)上面淀积一层多晶硅，填充所述沟槽(21)，形成多晶硅栅；
    S9:采用光刻和离子注入工艺，光刻定义出需要注入的区域，注入氮离子或磷离子到所述P-外延层(2)表面相应区域，形成所述第一N+层(22)的表面层；
    S10:采用光刻和离子注入工艺，光刻定义出需要注入的第三P+层(27)区 域，通过注入铝离子形成所述第三P+层(27)；
    S11:采用光刻和刻蚀工艺，光刻定义需要的多晶硅栅层域，并刻蚀掉不需要的多晶硅；
    S12:采用淀积工艺，在所述多晶硅栅表面淀积一层绝缘介质层(3)，作为所述多晶硅栅与金属电极的电隔离；
    S13:采用光刻和刻蚀工艺，光刻定义出有源层孔层和所述多晶硅栅上的孔层，并刻蚀掉所述绝缘介质层(3)上不需要的部分；
    S14:采用淀积工艺，在所述绝缘介质层(3)上淀积一层金属；
    S15:采用刻蚀工艺，光刻定义出源极金属层域、漏极金属层域和栅极金属层域，进行刻蚀，形成所述功率器件的源极电极、漏极电极和栅极电极。
  14. 一种功率器件，其特征在于，包括：
    P基体(6)，所述P基体(6)上形成N-外延层(61)，所述N-外延层(61)内设有沟槽；
    N-外延层(61)，所述N-外延层(61)内形成有相互隔离的P+1层(62)和P+2层(63),所述P+1层(62)电连接位于所述N-外延层(61)表面的源极，所述P+2层(63)电连接位于所述P基体(6)底部的漏极；
    栅极，所述栅极至少一部分形成在所述沟槽内，且所述栅极沿着所述P+1层(62)和P+2层(63)的排布方向延伸，当所述栅极施加开启电压时，所述P+1层(62)和P+2层(63)之间的N-沟道层(64)形成横向的导电沟道。
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