TWI553726B - 改良的溝槽內輪廓 - Google Patents

改良的溝槽內輪廓 Download PDF

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TWI553726B
TWI553726B TW101135395A TW101135395A TWI553726B TW I553726 B TWI553726 B TW I553726B TW 101135395 A TW101135395 A TW 101135395A TW 101135395 A TW101135395 A TW 101135395A TW I553726 B TWI553726 B TW I553726B
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史派勒凱達
茵可尼汀
湯靜
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應用材料股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

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Description

改良的溝槽內輪廓 【相關申請案之交互參照】
此申請案主張美國臨時申請案61/539,279之權益，該美國臨時申請案於2011年9月26日提出申請，發明名稱為「Improved Intrench Profile(改良的溝槽內輪廓)」。該臨時申請案之全文在此併入本文。
本發明關於半導體處理技術。
半導體處理經常包括許多各別的製造步驟。在技術現況中，常規上將電路部件形成為處於奈米尺寸，且需要具敏感度的製造技術。例如，在用於淺溝槽隔離(STI)閘極形成上的整合方案上，在選擇性材料存在於奈米級的細小溝槽中時，必須優先移除犧牲膜。隨著半導體技術持續發展，這些半導體基材溝槽繼續在寬度上縮小，這使得膜的移除更加困難。
這些小寬度的溝槽需要精細的蝕刻技術。儘管可用各種蝕刻技術，但幾乎沒有蝕刻技術提供這麼錯綜複雜的細節所必須的選擇性移除。例如，使用氫氟化物溶液的溼式移除法可用於選擇性移除。但此類溼式移除法不能用於STI的凹部形成上，因為該製程的化學條件 (chemistry)與溶液浴(bath)的壽命經常無法充分受到控制以用於此類細微的蝕刻。
可運用乾式蝕刻技術，且該乾式蝕刻技術已顯示能提出選擇性移除。例如，使用乾式蝕刻劑氣體(包括氨氣與含氟氣體)之組合的SiconiTM製程已被用於在移除期間較佳地控制材料的移除。然而，該乾式蝕刻劑氣體仍以不同速率選擇性地蝕刻不同品質的氧化物。儘管此氧化物的選擇性在半導體處理期間經常是可被接受的，但在STI凹部形成中，細微的選擇性可能引發在STI溝槽中有凹陷(concave)輪廓，其中襯墊氧化物與可流動氧化物同時存在。這樣的輕微凹陷(或彎月面(meniscus))可能潛在地引發整合被動元件規模縮放以及溝槽間控制閘極多晶矽填充之整合問題。因此，需要在STI凹部產生上有改良的溝槽輪廓。這些與其他需求由本發明解決。
本技術提供從已蝕刻在半導體基材上的溝槽內移除不同品質的介電材料的方法。可用乾式蝕刻劑氣體執行該移除，所述乾式蝕刻劑氣體對沉積的氧化物之品質不敏感。因為不敏感，從而該等乾式蝕刻劑氣體可以實質上類似的速率移除不同的氧化物。以此方式，包括不同品質的多種氧化物之溝槽可受到蝕刻，而使得溝槽內的輪廓遍及不同氧化物上是一致的。
在此描述於半導體基材中蝕刻凹部的方法。該等方法可包含：在該基材的溝槽中形成介電襯墊層，其中該襯墊層具有第一密度。該等方法也可包含：沉積第二介電層，該第二介電層至少部分位在該溝槽中於該襯墊層上。該第二介電層在沉積後最初為可流動，並且該第二介電層可具有第二密度，該第二密度低於該襯墊層的第一密度。該等方法可進一步包括：將該基材暴露至乾式蝕刻劑，其中該蝕刻劑移除該第一襯墊層與該第二介電層的一部分，而形成凹部，其中該乾式蝕刻劑包括含氟化合物與分子氫。移除該第一介電襯墊層與移除該第二介電層的蝕刻速率比為約1：1.2至約1：1。
本發明的實施例也包括一種蝕刻介電材料的方法，該介電材料位在覆於半導體基材上的選擇性材料的多個區塊之間。選擇性材料可包括諸如多晶矽或其他用於形成如浮置閘極之結構的材料。諸如多晶矽的選擇性材料可能需要某些移除技術，這些移除技術能夠在移除其他材料的同時盡可能多地維持該選擇性材料。另一態樣中，在某些類型的溼式或腐蝕性蝕刻期間，可相對於犧牲材料優先地移除選擇性材料，因而可使用維持選擇性材料的移除技術。該等方法包括：沉積選擇性材料覆於半導體基材上。該等方法也可包括：在該選擇性材料與半導體基材中蝕刻至少一個溝槽，該至少一個溝槽在該半導體基材上建立至少兩個彼此隔離的該選擇性材料之區塊。可沉積該介電材料以至少部分填充該選擇性材料的 該等隔離區塊之間的該溝槽。隨後可將該基材暴露至乾式蝕刻劑氣體，該乾式蝕刻劑氣體移除該選擇性材料的該等隔離區塊之間的該介電層的一部分而形成凹部。該乾式蝕刻劑氣體可包括含氟化合物與分子氫。
額外的實施例與特徵在某種程度上於下文的實施方式中提出，且對發明所屬技術領域中具有通常知識者而言，一旦審視本說明書將能明瞭該額外的實施例與特徵及/或可透過操作所揭露的實施例而學得該額外的實施例與特徵。透過說明書中所描述的手段、組合、與方法，可實現與達成所揭露的實施例的特徵與優點。
下文的描述是以解釋為目的，其中提出許多細節以使世人瞭解本發明的各實施例。然而，對於發明所屬技術領域中具有通常知識者而言，無須這些細節中的一些細節而可操作某些實施例，或可用額外的細節操作某些實施例。
本技術提供在半導體基材中蝕刻凹部的方法，該等方法中，使用實質上無氨氣的乾式蝕刻劑。透過納入極微濃度的氨氣，可強化蝕刻劑氣體內氟自由基的量，此舉可容許對氧化物品質較不敏感的移除。乾式蝕刻劑可包括含氟氣體以及分子氫。
在此描述一種在半導體基材中蝕刻凹部的方法。該等 方法可包含：在該基材的溝槽中形成介電襯墊層，其中該襯墊層具有第一密度。該等方法也可包含：沉積第二介電層，該第二介電層至少部分位在該溝槽中於該襯墊層上。該第二介電層在沉積後最初為可流動，並且該第二介電層可具有第二密度，該第二密度低於該襯墊的第一密度。該等方法可進一步包括：將該基材暴露至乾式蝕刻劑，其中該蝕刻劑移除該第一襯墊層與該第二介電層的一部分而形成凹部，其中該乾式蝕刻劑包括含氟化合物與分子氫，且其中移除該第一介電襯墊層與移除該第二介電層的蝕刻速率比為約1：1.2至約1：1。
參考第1圖(該圖顯示根據所揭露的實施例的蝕刻製程100)，可在半導體基材上形成介電襯墊層(110)。最初沉積在溝槽中的該介電襯墊層可被沉積成產生實質上共形的襯墊。共形是指所沉積的膜層在水平表面與垂直表面二者上具有一致的厚度，或階梯覆蓋率等於約1。襯墊也可形成為覆於基材的其他層上，所述其他層包括墊氧化物與浮置閘極。此襯墊助於避免矽通過可用於填充間隙的較低品質的可流動介電質短路，該等介電質可用於填充間隙是因為該等介電質有較佳的間隙填充品質，諸如可流動性。一些實施例中，介電襯墊層是透過較無法流動或非可流動的沉積技術所沉積，該沉積技術可以是HDP-CVD，或在其他實施例中可為諸如HARP的SACVD或諸如電漿強化TEOS與氧(或TEOS與臭氧)的PECVD。沉積的介電質可包括矽氧化物，諸如無摻雜 的矽土(silica)玻璃或摻雜的矽土，諸如磷矽酸鹽玻璃、硼矽酸鹽玻璃、或硼磷矽酸鹽玻璃。另外其他的介電質可包括氮化矽與氮氧化矽。
HDP沉積產生具HDP品質氧化物(諸如氧化矽)的襯墊層以作為第一介電層，該第一介電層具有比由可流動製程沉積的氧化物高的第一密度以及整體品質。HDP膜是由以下方式產生：在低壓或甚至真空(經常是以射頻能量)激發反應物氣體，而在接近基材表面處建立電漿。電漿能量使元素具高度反應性且產生高密度與高品質膜。其他實施例中，可在基材上執行熱製程，以產生襯墊氧化物層，其中藉由將基材加熱至高溫而引發反應物氣體的化學反應，以誘導膜的反應與形成。
可沉積第二介電層(115)，此步驟是由可流動沉積方法所產生，該方法可包括例如旋塗玻璃或可流動CVD。一些實施例中，可流動CVD用於覆蓋介電襯墊層並且填充基材中的溝槽。可流動氧化物可透過以下步驟形成：分開激發前驅物氣體，之後使這些前驅物氣體在基材正上方的處理腔室之區域中結合，而產生可流動氧化物，該可流動氧化物於溝槽頂部開始流動，之後向下流動以將該可流動氧化物填入而不至於建立空洞或接縫。第二介電層具有第二密度，該第二密度低於襯墊層的第一密度。除了填充溝槽外，一些實施例中，可流動氧化物可額外填充在墊氧化物層(諸如氮化矽)之間，或對於包括產生例如NAND快閃記憶體的情況而言，該可流動氧 化物額外地可填充在多晶矽浮置閘極之間。
沉積後，可使用許多方法沉積最初可流動的介電層。例如，可使用可流動CVD製程，其中將矽前驅物導至容納基材的基材處理區域。另一前驅物僅在通過遠端電漿區域而建立自由基前驅物(諸如氮前驅物)後導入，該前驅物隨後流進基材處理區域並且與矽前驅物結合。此技術中，含矽前驅物並未直接被基材處理區域中施加的電漿功率所激發。反而，電漿功率只激發基材處理區域外的前驅物。此安排方式造成含矽與氮層以可流動式沉積進入受襯的溝槽中。膜的可流動性隨著沉積進展而衰減，且可流動性在下文所述的固化操作期間基本上消除。
含矽前驅物可含有碳及/或氮，以確保間隙填充之介電層形成期間的可流動性。一些實施例中，含矽前驅物可以是無碳的含矽前驅物，該無碳的含矽前驅物使間隙填充層能夠在固化製程期間歷經較少縐縮。除了其他類型的矽前驅物之外，該無碳的矽前驅物特別可以是例如矽與氮前驅物、矽與氫前驅物、或含矽氮與氫的前驅物。這些前驅物的特定範例可包括矽烷胺，除其他矽烷胺之外，該前驅物特別諸如為H2N(SiH3)、HN(SiH3)2、與N(SiH3)3。這些矽烷胺可以與額外氣體混合，該額外氣體可作用如載氣、反應性氣體、或前述兩種氣體。這些額外氣體的範例除其他氣體之外特別可包括H2、N2、NH3、He與Ar。無碳的矽前驅物之範例也可包括甲矽烷(SiH4)，該甲矽烷為單獨存在或與其他含矽氣體(例如 N(SiH3)3)、含氫氣體(例如H2)、及/或含氮氣體(例如N2、NH3)混合。含矽前驅物也可包括不具有碳或氮的矽化合物，諸如甲矽烷、乙矽烷等。若沉積的氧化物膜是受摻雜的氧化物膜，也可使用摻質前驅物，該摻質前驅物除了其他硼與磷摻質之外特別諸如為TEB、TMB、B2H6、TEPO、PH3、P2H6、與TMP。
氮可納入自由基前驅物與含矽前驅物之任一者或二者中。當氮存在於自由基前驅物中時，可稱為自由基氮前驅物。該自由基氮前驅物包括電漿流出物，該電漿流出物是透過激發電漿中較穩定的含氮前驅物而建立。例如，含有NH3及/或聯胺(N2H4)的相對穩定含氮前驅物可在腔室電漿區域或處理腔室外的遠端電漿系統(RPS)中活化，而形成該自由基氮前驅物，該自由基氮前驅物隨後輸送進入無電漿的基材處理區域。不同實施例中，該穩定的氮前驅物也可以是包含NH3與N2、NH3與H2、NH3與N2與H2、以及N2與H2的混合物。N2與H2的混合物中也可使用聯胺以取代NH3或與NH3結合使用。不同實施例中，穩定的氮前驅物之流速可為約200 sccm或更大、約300 sccm或更大、約500 sccm或更大、或者是約700 sccm或更大。含氮前驅物也可包括N2O、NO、NO2、與NH4OH。
所產生的自由基氮前驅物可包括.N、.NH、.NH2等之一或多者，且可伴隨在電漿中形成的離子化物種。其他實施例中，自由基氮前驅物在處理腔室的一區塊中生 成，該區塊與基材處理區域分隔，在該基材處理區域，該等前驅物混合並且反應而沉積含矽與氮層於沉積基材(例如半導體晶圓)上。該分隔可併入供應反應物至基材處理區域的噴頭。該自由基氮前驅物也可伴隨載氣，諸如氬氣、氦氣等。氧可被同時遞送進入遠端電漿區域(以O2及/或O3的形式)，以調整自由基氮前驅物中以及用此技術沉積的襯墊或間隙填充層中的氧含量的量。
該可流動性可能(至少某種程度上)是由於沉積膜中顯著的氫成份。例如，沉積的膜可具有矽氮烷形式的Si-NH-Si骨架，即Si-N-H膜。可流動性也可能是由於矽氮烷形式的短鍊聚合物所致。使短鍊聚合物與可流動性形成的氮可源自於自由基前驅物或含矽前驅物之任一者。當矽前驅物與自由基氮前驅物為無碳時，沉積的含矽與氮膜也是實質上無碳。當然，無碳並非必然意味該膜缺乏甚至痕量的碳。碳混入物(contamination)可存在於前驅物材料中而找到該碳混入物進入沉積的含矽與氮膜的途徑。然而，這些碳雜質的量遠低於具有碳基團的矽前驅物(例如TEOS、TMDSO等)中可見的量。
其他實施例中，第一與第二介電層二者皆為可流動或可能皆為不可流動。一些實施例中，介電質是透過不同機制沉積(例如第一介電質為不可流動，第二介電質為可流動)，但取決於使用的反應物而具有類似的介電性質。尚有其他實施例，該第一介電質與該第二介電質是由相同機制沉積，但具有不同品質，這是由於使用不同 反應物物種於該兩個介電質之故。
當基材溫度在沉積含矽膜期間維持在相對低溫的同時，可流動膜的生長可持續進展。該可流動氧化物膜可於低溫下沉積在基材表面，該低溫是透過在沉積期間冷卻基材所維持。基座可包括加熱及/或冷卻導管，該等導管在不同的實施例中將基座與基材溫度設定在約-40℃至約1000℃之間、約100℃至約600℃之間、低於約500℃或處於約400℃或更低。
已將可流動介電質沉積在基材上之後，可執行蝕刻製程以移除過多的介電質，以為後續的整合被動元件製造步驟做好準備。一些實施例中，乾式蝕刻劑氣體用於蝕刻該介電層(120)。該蝕刻劑移除第一襯墊層與第二介電層二者的一部分。包括在該蝕刻劑中的氣體可包括在進入半導體處理區域之前先通過遠端電漿區域而被激發的氣體。該蝕刻劑可包括含氟化合物與分子氫，且與介電層反應而產生固體副產物，該固體副產物會在基材溫度提昇到超過昇華溫度時昇華，從而移除過多的介電質。移除第一介電襯墊層與移除第二介電層的蝕刻速率比可為約1：2，或在其他實施例中可為約1：1.5、1：1.3、1：1.2、1：1.1、或約1：1。當蝕刻速率比等於1：1時，各別的介電質以相同速率被移除。
一些實施例中，乾式蝕刻劑氣體含有三氟化氮與分子氫。在其他實施例中，該乾式蝕刻劑氣體實質上無氨氣。三氟化氮與氫的乾式蝕刻劑氣體的組合可產生較緩慢的 反應，該較緩慢的反應相較於包括氨氣的乾式蝕刻劑氣體對氧化物的品質較不具選擇性。添加氨氣可減少反應性物種中氟的濃度，而產生氟化銨與氟化氫銨。這些產物以一較快的速率移除較低密度與較低品質的可流動介電質，移除得比移除較高密度、較高品質的襯墊氧化物層(透過例如HDP沉積)快。因具有更為接近1：1的針對HDP氧化物的選擇性，相較於包括氨氣的乾式蝕刻劑氣體，該實質上無氨氣的乾式蝕刻劑氣體能夠產生具有較不凹陷的轉角輪廓之凹部。一些實施例中，實質上無氨氣的乾式蝕刻劑氣體產生抵靠凹部側壁的實質上平整的轉角輪廓。
可流動的介電質可在沉積之後固化，以改良介電膜品質。各實施例中，固化可在氧化環境(如蒸汽)、惰性環境(諸如氮氣)、或其他環境中執行。膜的可流動性隨著沉積進展而衰減，且可流動性基本上在固化操作期間消除。該固化操作可涉及將含矽與氮的層轉換成氧化矽。固化涉及提昇圖案化基材的溫度，以及將間隙填充介電層暴露至含氧環境。一些實施例中，升高的溫度誘導氧化物從襯墊層擴散進入間隙填充層，而提供來自間隙填充介電層下方的額外氧來源。該固化可以是退火，且可在低於約1000℃的溫度下執行。其他實施例中，固化可發生在低於約800℃、600℃、500℃、400℃、300℃、或低於約200℃。利用可流動介電質可減少製造製程的熱預算，且在一些情況中，該製程可在低於約600℃、 500℃、400℃、300℃、200℃、或低於約100℃下執行，以維持可流動的介電質。
現在參考第2圖，在此描述蝕刻介電材料的方法200，該介電材料位在覆於半導體基材上的選擇性材料的多個區塊之間。該方法包括沉積選擇性材料覆於半導體基材上(210)。選擇性材料可以是期望在移除另外材料(separate material)的同時還維持住的任何材料。例如(且並非意欲限制本發明)，該選擇性材料可以是在快閃記憶體單元中做為浮置閘極的多晶矽。另一材料(諸如介電質)可與選擇性多晶矽共同位於基材上。一些實施例中的目的可為移除介電材料的同時維持選擇性多晶矽。在這樣的情況中，該介電質可透過限制移除或不移除多晶矽的方式移除。此舉可用優先移除該介電質的特殊蝕刻技術執行。例如，利用與氧化物或氮化物反應但不與多晶矽反應的乾式蝕刻劑氣體提供了一種移除介電質的同時維持選擇性材料的方式。其他實施例中，該選擇性材料是矽、沉積的金屬、介電質、或可沉積在基材上的任何其他材料，其中該目的是在移除另外材料期間移除顯著少量的選擇性材料。
已沉積選擇性材料之後，可蝕刻溝槽穿過選擇性材料(215)，且在一些例子中是蝕刻溝槽穿過半導體基材。該蝕刻建立位於半導體基材上的選擇性材料的隔離區塊，該等區塊被蝕刻的溝槽所分隔。該等溝槽可顯示高深寬比，其中溝槽深度可顯著地比該溝槽的寬度還大。 示範性的溝槽可具有約2：1或更大、約3：1或更大、約5：1、約7：1、或約10：1或更大等深寬比。
該方法可進一步包括沉積介電材料於該溝槽內(220)。該沉積可包括完全填充該溝槽以及沉積充分的介電質以覆蓋該選擇性材料，或在其他實施例中，該沉積可部分填充該溝槽。該介電質可沉積越過基材的高度(level)，使得該介電質至少部分填充在選擇性材料的隔離區塊之間。取決於溝槽的特性，可透過可流動或非可流動的方法沉積介電材料。在一些窄且深的溝槽的實施例中，可用可流動的方式沉積該介電質，以限制空洞發展的可能性。其他實施例中，更高品質的介電質可用於場部件之間改良的絕緣。一些實施例中，使用旋塗玻璃沉積介電材料。替代性實施例中，介電材料是透過可流動CVD所沉積。
一些實施例中，可執行多種介電質沉積而填充該溝槽。例如，在溝槽被可流動介電質填充之前，可將襯墊層沉積在該溝槽內。這樣的組合可提供以下優點：改良對襯墊層的絕緣，以及改良可流動介電質的填充特性。額外範例包括以一系列步驟沉積介電質，該等步驟包括沉積與往回蝕刻介電質，以盡量減少麵包狀現象(bread-loafing)與空洞形成。最初的介電層可沉積在溝槽中，之後進行中間蝕刻製程，以移除沿著溝槽頂部的介電質堆積。蝕刻後，可用後續介電材料的沉積填充溝槽的其餘部分。
可在沉積介電層後執行蝕刻製程(225)。該蝕刻可包括將基材暴露至乾式蝕刻劑氣體，該乾式蝕刻劑氣體移除選擇性材料的隔離區塊之間的一部分介電層，而形成凹部。該乾式蝕刻劑氣體可以是包括含氟化合物以及分子氫的氣體混合物。該等氣體可分別流進基材所處的處理腔室，且在一些實施例中，該乾式蝕刻劑氣體在流進處理腔室之前被遠端電漿源激發。一些實施例中，乾式蝕刻劑氣體實質上無氨氣，而可提供較慢的反應，且有較大量的氟自由基可用於反應。使用實質上無氨氣的乾式蝕刻劑氣體可產生具有實質上平整的轉角輪廓的凹部，這是由於防止氟自由基還原成包括氟化銨與氟化氫銨之產物所致。乾式蝕刻劑氣體可完全無氨氣，以進一步防止因形成中間化學物質(包括氟化銨與氟化氫銨)所造成的氟自由基移除。
一些沉積中，介電層沉積成遠高於選擇性材料的高度，且可執行中間的介電質移除。諸如化學機械研磨之類的製程可用於移除過多的介電質。選擇性材料可用做為蝕刻停止層，該蝕刻停止層可例如為場閘極多晶矽或氮化矽。一旦介電質已被移除降至選擇性材料層，則乾式蝕刻劑可用於移除位在選擇性材料的區塊之間的介電質。
可基於選擇性材料的有效場高度移除位在選擇性材料的區塊之間的介電質。例如，該介電質可被蝕刻至介於約200埃至約1200埃之間。額外的範例可具有被蝕刻至 介於約400埃至約1000埃之間、介於約600埃至約800埃之間等的介電質。有多個選擇性材料區塊且有在這些區塊之間必須移除介電質的多個區域時，乾式蝕刻劑氣體可提供單元至單元間(cell to cell)變化低於約10 nm的凹部。示範性的單元間(intercell)凹部深度之間的有效場高度變化低於約8 nm或低於約6 nm。乾式蝕刻劑氣體可提供單元之間蝕刻的一致性，其中單元凹部深度與形狀之間的偏差低於5%。單元深度與形狀之間的差異可低於約3%、約2%、約1.5%、約1%、約0.5%、約0.1%等。
在介電質已從選擇性材料的區塊之間移除之後所得的凹部輪廓可具有基底部(floor)，該基底部由基材的淺溝槽隔離中的殘餘介電材料所界定。該基底部的輪廓可在橫越該介電質至介電材料與選擇性材料交會處的位置為止皆為實質上平整。此交會點可界定凹部的轉角，且介電材料的轉角輪廓可為與選擇性材料呈大約直角。當界定凹部的介電材料基底部與選擇性材料壁之間形成直角時，平整的轉角輪廓業已形成。可形成超過或低於90°的角度，在此情況中，轉角輪廓可為實質上平整。於轉角處可能無法完全移除介電質，而在凹部轉角產生介電質的稍微凹陷。儘管該凹陷可能無法界定出完美的圓形剖面，然而該凹部側邊與基底部的曲率半徑可低於約5 nm。在一些實施例中，該曲率半徑可能低於約3 nm、2 nm、1 nm、5埃、3埃、2埃、或約1埃，從而提供實質 上平整的轉角輪廓。
該介電質可在沉積後且於蝕刻前固化，以改良介電膜的品質。固化可透過任何先前所討論的方法執行。該固化可以是退火，且可在低於約1000℃的溫度下執行，例如，該固化可發生在低於約800℃、600℃、500℃、400℃、300℃或低於約200℃。利用可流動介電質可減少製造製程的熱預算，且在一些情況中，該等製程可在低於約600℃、500℃、400℃、300℃、200℃或低於約100℃下執行，以維持可流動的介電質。
一些實施例中，已知為穿隧氧化物的氧化物層沉積在半導體基材與選擇性材料之間，以確保浮置閘極的隔離。該穿隧氧化物是在最初沉積選擇性材料與形成溝槽之前沉積。溝槽中與選擇性材料區塊之間所沉積的介電質可被蝕刻降至穿隧氧化物的高度。或者，該介電材料可以被蝕刻至選擇性材料區塊之間，但不被蝕刻降至穿隧氧化物的高度。
已從選擇性材料區塊之間移除介電材料後，可發生後續的製造。隔離層可沉積覆於選擇性層上以及蝕刻後的凹部中。此隔離層可提供例如浮置閘極與控制閘極(可在之後沉積)之間的襯墊。另一材料(諸如金屬、介電質、或某些其他材料)的沉積物可在隔離層已鋪設後沉積。該後續材料可以是多晶矽，作為快閃記憶體單元(諸如NAND快閃記憶體元件)中的控制閘極。蝕刻後的介電凹部的實質上平整的轉角輪廓能夠使後續整合的被動 元件層填充在(例如)寬度可為幾奈米的溝槽內側。當隔離層與後續的控制閘極層沉積在具有實質上平整的轉角輪廓及/或較佳的單元一致性的凹部內時，可因提供改良的界面供IPD規模縮放而防止進一步的整合問題。
現在轉至第3A圖，剖面視圖中顯示基材310，在該基材310上已執行根據本發明之方法的蝕刻製程。穿隧氧化物320沉積在基材310與選擇性材料325之間。該選擇性材料325可以是金屬、介電質、或氧化物，或者是某些其他材料。在一些實施例中，選擇性材料325可以是多晶矽，該多晶矽可受摻雜或不受摻雜。溝槽315建立在該等層中，且被介電材料319填充。該介電材料可在沉積後最初為可流動，且可在沉積後固化。該介電質隨後可往回蝕刻而形成具有轉角335的凹部單元330。該蝕刻製程可使用含氟氣體與分子氫的乾式蝕刻劑氣體混合物，且該乾式蝕刻劑氣體實質上無氨氣。雖然轉角335顯示些微凹陷，其他實施例可使該等轉角在界定凹部單元330的介電質基底部與選擇性材料壁之間的界面處平整或實質上平整，而建立直角的交會。第3A圖的剖面視圖可以是處理半導體元件中的中間步驟，該處理將包括沉積後續材料層(諸如多晶矽)於所形成的凹部單元內。此後續材料可在形成隔離層或襯墊層覆於選擇性材料上及凹部內之後沉積。該介電層319可包括襯墊層與額外的間隙填充介電層二者。
第3B圖中，剖面視圖顯示基材310，在該基材310上 已執行根據本發明之方法的蝕刻製程。基材310具有墊層340，該墊層340於形成溝槽315前沉積。溝槽形成後，可沉積介電襯墊材料317。襯墊317可例如透過HDP沉積。接著，沉積介電材料319在溝槽315內覆於襯墊層317上。介電材料319可在沉積後最初為可流動，且可在沉積後固化。介電材料319可與介電襯墊層317具有相同或不同的品質及/或密度。例如，襯墊層319可比介電材料319更高品質。
介電質319可延伸於墊氧化物340上方，且可在最初以諸如化學機械研磨之類的製程移除而降至墊氧化物層。可執行蝕刻製程，其中乾式蝕刻劑氣體混合物用於移除介電材料319與介電襯墊層317。乾式蝕刻劑氣體混合物可包括含氟氣體與分子氫，且可實質上無氨氣，或完全無氨氣。該乾式蝕刻劑氣體移除介電材料319與襯墊層317，而產生包括轉角335的凹部330。該轉角335的輪廓可實質上平整，這是指介電材料319與介電襯墊317被移除至實質上相同的深度。移除至同等深度是指乾式蝕刻劑氣體實質上對氧化物品質不敏感。
範例
在使用有氨氣及無氨氣的蝕刻劑氣體混合物的蝕刻選擇性之間製作比較性範例。這些蝕刻是在先襯以HDP襯墊層再以可流動氧化物填充的溝槽上進行。該等介電質暴露至含有三氟化氮與分子氫的乾式蝕刻劑氣體混合物。一個範例中，該乾式蝕刻劑氣體也含有氨氣，而在 比較性範例中，該乾式蝕刻劑氣體實質上無氨。如下文中的表1所見，含有氨氣的乾式蝕刻劑氣體比實質上無氨氣的乾式蝕刻劑氣體移除較多的可流動氧化物(相較於HDP氧化物)。
第4A圖與第4B圖顯示已執行蝕刻後的基材的比較TEM影像。第4A圖顯示已在上面執行利用氨氣的蝕刻的基材。影像中所見的轉角輪廓顯示凹陷，這是指於溝槽內並未一致地移除介電質。然而，第4B圖顯示在上面以實質上無氨氣的乾式蝕刻劑氣體執行的蝕刻的基材。如影像中可見，轉角輪廓實質上平整，其中介電層交會氮化物墊，而建立幾乎成直角的轉角輪廓。平整的轉角輪廓是指，在溝槽內一致地移除介電質。
已揭露數個實施例，發明所屬技術領域中具有通常知 識者將瞭解，可使用各種修飾、替代性架構、與等效物而不背離所揭露的實施例之精神。此外，在此並未描述許多已知的製程與元件，以避免不必要地混淆了本發明。因此，前述的說明書內容不應被視為限制本發明的範疇。
請注意，可將個別的實施例描述成以流程圖、流程的示意圖、或方塊圖所繪的製程。雖然流程圖可將方法描述為依序的製程，但可平行或同時執行該等操作中的許多操作。此外，可重新排列操作順序。當完成製程的操作時，可終結製程，但該製程可有不在圖中討論或包括在圖中的額外步驟。再者，任何特定描述的製程中並非所有操作可發生在所有實施例中。製程可對應方法、函數、程序、子常式、子程式等。當製程對應函數時，該製程的終結對應函數返回至呼叫函數或主函數。
當提供一數值範圍時，應瞭解，除非上下文中另外清楚地指示，否則也特定地揭露該範圍的上限與下限之間的每一居中數值(該數值至下限單位的最小的小數)。也涵蓋了陳述的範圍中任何陳述數值(或居中數值)以及該陳述範圍中的任何其他陳述數值(或居中數值)之間的每一較小範圍。在該陳述範圍中的任何特定被排除的極限的條件下，這些較小範圍的上限與下限可獨立地被包括在該範圍中或被排除於該範圍，且本發明內也涵蓋了在該等較小範圍中包括任一、無一、或兩個極限的每一範圍。當所陳述的範圍包括該等極限的一者或二者 時，也包括了排除這些所包括的極限之任一者或二者的範圍。
如在此以及所附的申請專利範圍中所用，除非上下文另外清楚地指示，否則單數形式的「一」、「該」、與「所述」包括複數的參考物。因此，例如「一介電材料」所指的參考物包括複數個此類材料，且「該應用」所指的參考物包括一或多個應用及發明所屬技術領域中具有通常知識者已知的該等應用之等效物與諸如此類之物的參考物。
同樣，「包含」與「包括」等詞彙在用於此說明書及隨後的申請專利範圍時，申請人希望該等詞彙指定存在陳述的特徵、整體、部件、或步驟，但這些詞彙不排除一或多個其他特徵、整體、部件、步驟、動作、或群組的存在或增加。
100‧‧‧蝕刻製程
110-120‧‧‧步驟
200‧‧‧蝕刻製程
210-225‧‧‧步驟
310‧‧‧基材
315‧‧‧溝槽
317‧‧‧介電襯墊
319‧‧‧介電材料
320‧‧‧穿隧氧化物
325‧‧‧選擇性材料
330‧‧‧凹部單元
335‧‧‧轉角
340‧‧‧墊層
透過參考說明書的其餘部分以及圖式，能夠進一步瞭解所揭露的實施例的本質與優點。
第1圖顯示根據所揭露的實施例的蝕刻製程的流程圖。
第2圖顯示根據所揭露的實施例的蝕刻製程的流程圖。
第3A圖顯示基材的剖面視圖，該基材上已執行根據本 發明方法之蝕刻製程。
第3B圖顯示基材的剖面視圖，該基材上已執行根據本發明方法之蝕刻製程。
第4A圖顯示基材的TEM影像，在該基材上已執行利用氨氣的蝕刻。
第4B圖顯示基材的TEM影像，在該基材上已執行根據本發明方法的蝕刻製程。
在附圖中，類似的部件及/或特徵可具有相同的元件符號。進一步而言，同類型的各部件可由以下方式區分：在元件符號後附加區分類似部件及/或特徵的字母。若在說明書中只用第一元件符號，則該描述可應用至具有相同的第一元件符號(無論後綴的字母為何)的類似部件及/或特徵之任何一者。
310‧‧‧基材
315‧‧‧溝槽
317‧‧‧介電襯墊
319‧‧‧介電材料
330‧‧‧凹部單元
335‧‧‧轉角
340‧‧‧墊層

Claims (15)

  1. 一種在一半導體基材中蝕刻一凹部的方法，該方法包含以下步驟：形成一介電襯墊層於該半導體基材的一溝槽中，其中該介電襯墊層具有一第一密度；沉積一第二介電層，使該第二介電層至少部分位在該溝槽中於該介電襯墊層上，其中該第二介電層在該沉積後一開始為可流動，且其中該第二介電層具有一第二密度，該第二密度低於該介電襯墊層的該第一密度；將該半導體基材暴露至乾式蝕刻劑，其中該乾式蝕刻劑移除該介電襯墊層與該第二介電層的一部分，而形成該凹部，其中該乾式蝕刻劑包含一含氟化合物與分子氫，其中該介電襯墊層及該第二介電層是在約400℃或更低之溫度下沉積與蝕刻，且其中移除該介電襯墊層與移除該第二介電層的蝕刻速率比為約1：1.2至約1：1。
  2. 如請求項1所述的方法，其中該介電襯墊層包含一高密度電漿所形成的氧化矽層。
  3. 如請求項1所述的方法，其中該第二介電層包含由可流動CVD所沉積的氧化矽層。
  4. 如請求項1所述的方法，其中該含氟化合物包含NF3。
  5. 如請求項1所述的方法，其中該乾式蝕刻劑實質上無氨氣。
  6. 如請求項1所述的方法，其中該凹部具有一實質上平整的轉角輪廓。
  7. 如請求項1所述的方法，進一步包含以下步驟：在該第二介電層沉積之後，固化該第二介電層。
  8. 一種蝕刻一介電材料的方法，該介電材料位在覆於一半導體基材上的一選擇性材料的多個區塊之間，該方法包括以下步驟：沉積一選擇性材料覆於一半導體基材上；在該選擇性材料與該半導體基材中蝕刻至少一個溝槽，該至少一個溝槽在該半導體基材上建立該選擇性材料之至少兩個彼此隔離的區塊；於該溝槽內形成一第一介電層作為一襯墊層；將一第二介電材料沉積於該溝槽中，其中該第二介電材料至少部分填充於該選擇性材料的該等隔離的區塊之間；以及將該基材暴露至一乾式蝕刻劑氣體，該乾式蝕刻 劑氣體移除該選擇性材料的該等隔離的區塊之間的該第一介電層和該第二介電材料的一部分，而於該選擇性材料的該等隔離的區塊之一頂高度下方形成一凹部，其中該乾式蝕刻劑氣體包括一含氟化合物與分子氫，且其中該第一介電層及該第二介電材料是在約400℃或更低之溫度下形成與蝕刻。
  9. 如請求項8所述的方法，其中該乾式蝕刻劑氣體實質上無氨氣。
  10. 如請求項8所述的方法，其中該選擇性材料是多晶矽。
  11. 如請求項8所述的方法，進一步包含以下步驟：在沉積該選擇性材料之前，沉積一穿隧氧化物於該半導體基材上，其中該選擇性材料是沉積在該穿隧氧化物上。
  12. 如請求項8所述的方法，其中該第二介電材料是由可流動CVD所沉積。
  13. 如請求項8所述的方法，其中該凹部具有一實質上平整的轉角輪廓。
  14. 如請求項8所述的方法，進一步包含以下步驟：在該 第二介電材料沉積之後，固化該第二介電材料。
  15. 如請求項9所述的方法，其中移除該第一介電層與移除該第二介電材料的蝕刻速率比為約1：1.2至約1：1。
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US8927390B2 (en) 2015-01-06
WO2013049173A3 (en) 2013-06-13
US9012302B2 (en) 2015-04-21
KR20140065478A (ko) 2014-05-29
US20130260533A1 (en) 2013-10-03
WO2013049173A2 (en) 2013-04-04
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KR102068636B1 (ko) 2020-01-21
TW201320179A (zh) 2013-05-16

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