CN103907182B - 改良的沟槽内轮廓 - Google Patents

改良的沟槽内轮廓 Download PDF

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CN103907182B
CN103907182B CN201280051888.0A CN201280051888A CN103907182B CN 103907182 B CN103907182 B CN 103907182B CN 201280051888 A CN201280051888 A CN 201280051888A CN 103907182 B CN103907182 B CN 103907182B
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dielectric
dielectric layer
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K·萨普瑞
N·K·英格尔
J·唐
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    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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Abstract

在此描述一种在半导体基板中蚀刻凹部的方法。该方法可包含：在基板的沟槽中形成介电衬垫层，其中该衬垫层具有第一密度。该方法也可包含：至少部分位在该沟槽中于该衬垫层上沉积第二介电层。该第二介电层在沉积后最初为可流动，并且有第二密度，该第二密度低于该衬垫的第一密度。该方法可进一步包括：将该基板暴露至干式蚀刻剂，其中该蚀刻剂移除该第一衬垫层与该第二介电层的一部分而形成凹部，其中该干式蚀刻剂包括含氟化合物与分子氢，且其中移除该第一介电衬垫层与移除该第二介电层的蚀刻速率比为约1:1.2至约1:1。

Description

改良的沟槽内轮廓
相关申请案的交互参照
此申请案是美国专利申请案13/624,724的PCT申请，该美国申请案于2012年9月21日提出申请，发明名称为“Improved Intrench Profile（改良的沟槽内轮廓）”。此申请案与美国临时申请案61/539,279有关并且主张其权益，该美国临时申请案于2011年9月26日提出申请，发明名称为“Improved Intrench Profile（改良的沟槽内轮廓）”。这两件美国专利申请案的全文在此并入本文。
背景技术
半导体处理经常包括许多不同的制造步骤。在技术现况中，常规上将电路部件形成为处于纳米尺寸，且需要具敏感度的制造技术。例如，在用于浅沟槽隔离（“STI”）栅极形成上的整合方案上，在选择性材料存在于纳米级的细小沟槽中时，必须优先移除牺牲膜。随着半导体技术持续发展，这些半导体基板沟槽继续在宽度上缩小，这使得膜的移除更加困难。
这些小宽度的沟槽需要精细的蚀刻技术。尽管可用各种蚀刻技术，但几乎没有蚀刻技术提供这么错综复杂的细节所必须的选择性移除。例如，使用氢氟化物溶液的湿式移除法可用于选择性移除。但此类湿式移除法不能用于STI的凹部形成上，因为该工艺的化学条件（chemistry）与溶液浴（bath）的寿命经常无法充分受到控制以用于此类细微的蚀刻。
可运用干式蚀刻技术，且该干式蚀刻技术已显示能提供选择性移除。例如，使用干式蚀刻剂气体（包括氨气与含氟气体）的组合的SiconiTM工艺已被用于在材料移除期间较佳地控制材料的移除。然而，该干式蚀刻剂气体仍以不同速率选择性地蚀刻不同品质的氧化物。尽管此氧化物的选择性在半导体处理期间经常是可被接受的，但在STI凹部形成中，细微的选择性可能引发在STI沟槽中有凹陷（concave）轮廓，其中衬垫氧化物与可流动氧化物同时存在。这样的轻微凹陷（或弯月面（meniscus））可能潜在地引发整合无源器件规模缩放以及控制沟槽间的栅极多晶硅填充的整合问题。因此，需要在STI凹部产生上有改良的沟槽轮廓。这些与其他需求由本发明解决。
发明内容
本技术提供从已蚀刻在半导体基板上的沟槽内移除不同品质的介电材料的方法。可用干式蚀刻剂气体执行该移除，所述干式蚀刻剂气体对沉积的氧化物的品质不敏感。因为不敏感，从而该等干式蚀刻剂气体可以实质上类似的速率移除不同的氧化物。以此方式，包括不同品质的多种氧化物的沟槽可受到蚀刻，而使得沟槽内的轮廓遍及不同氧化物上是一致的。
在此描述于半导体基板中蚀刻凹部的方法。该等方法可包含：在该基板的沟槽中形成介电衬垫层，其中该衬垫层具有第一密度。该等方法也可包含：至少部分在该沟槽中于该衬垫层上沉积第二介电层。该第二介电层在沉积后最初为可流动，并且该第二介电层可具有第二密度，该第二密度低于该衬垫层的第一密度。该等方法可进一步包括：将该基板暴露至干式蚀刻剂，其中该蚀刻剂移除该第一衬垫层与该第二介电层的一部分，而形成凹部，其中该干式蚀刻剂包括含氟化合物与分子氢。移除该第一介电衬垫层与移除该第二介电层的蚀刻速率比为约1:1.2至约1:1。
本发明的实施例也包括一种蚀刻介电材料的方法，该介电材料位在半导体基板上的选择性材料的多个区块之间。选择性材料可包括诸如多晶硅或其他用于形成如浮置栅极的结构的材料。诸如多晶硅的选择性材料可能需要某些移除技术，这些移除技术能够在移除其他材料的同时尽可能多地维持该选择性材料。另一态样中，在某些类型的湿式或腐蚀性蚀刻期间，可相对于牺牲材料优先地移除选择性材料，因而可使用维持选择性材料的移除技术。该等方法包括：沉积选择性材料于半导体基板上。该等方法也可包括：在该选择性材料与半导体基板中蚀刻至少一个沟槽，该至少一个沟槽在该半导体基板上建立至少两个彼此隔离的该选择性材料的区块。可沉积该介电材料以至少部分填充该选择性材料的该等隔离区块之间的该沟槽。随后可将该基板暴露至干式蚀刻剂气体，该干式蚀刻剂气体移除该选择性材料的该等隔离区块之间的该介电层的一部分而形成凹部。该干式蚀刻剂气体可包括含氟化合物与分子氢。
额外的实施例与特征在某种程度上于下文的实施方式中提出，且对发明所属技术领域中具有通常知识者而言，一旦审视本说明书将能明了该额外的实施例与特征及/或可通过操作所揭露的实施例而学得该额外的实施例与特征。通过说明书中所描述的手段、组合、与方法，可实现与达成所揭露的实施例的特征与优点。
附图说明
通过参考说明书的其余部分以及附图，能够进一步了解所揭露的实施例的本质与优点。
图1显示根据所揭露的实施例的蚀刻工艺的流程图。
图2显示根据所揭露的实施例的蚀刻工艺的流程图。
图3A显示基板的剖面视图，该基板上已执行根据本发明方法的蚀刻工艺。
图3B显示基板的剖面视图，该基板上已执行根据本发明方法的蚀刻工艺。
图4A显示基板的TEM影像，在该基板上已执行利用氨气的蚀刻。
图4B显示基板的TEM影像，在该基板上已执行根据本发明方法的蚀刻工艺。
在附图中，类似的部件及/或特征可具有相同的元件符号。进一步而言，同类型的各部件可由以下方式区分：在元件符号后附加区分类似部件及/或特征的字母。若在说明书中只用第一元件符号，则该描述可应用至具有相同的第一元件符号（无论后缀的字母为何）的类似部件及/或特征的任何一者。
具体实施方式
下文的描述是以解释为目的，其中提出许多细节以便理解本发明的各实施例。然而，对于本领域普通技术人员而言，无须这些细节中的一些细节而可操作某些实施例，或可用额外的细节操作某些实施例。
本技术提供在半导体基板中蚀刻凹部的方法，该等方法中，使用实质上无氨气的干式蚀刻剂。通过纳入极微浓度的氨气，可强化蚀刻剂气体内氟自由基的量，此举可容许对氧化物品质较不敏感的移除。干式蚀刻剂可包括含氟气体以及分子氢。
在此描述一种在半导体基板中蚀刻凹部的方法。该等方法可包含：在该基板的沟槽中形成介电衬垫层，其中该衬垫层具有第一密度。该等方法也可包含：至少部分位在该沟槽中于该衬垫层上沉积第二介电层。该第二介电层在沉积后最初为可流动，并且该第二介电层可具有第二密度，该第二密度低于该衬垫层的第一密度。该等方法可进一步包括：将该基板暴露至干式蚀刻剂，其中该蚀刻剂移除该第一衬垫层与该第二介电层的一部分而形成凹部，其中该干式蚀刻剂包括含氟化合物与分子氢，且其中移除该第一介电衬垫层与移除该第二介电层的蚀刻速率比为约1:1.2至约1:1。
参考图1（该图显示根据所揭露的实施例的蚀刻工艺100），可在半导体基板上形成介电衬垫层110。最初沉积在沟槽中的该介电衬垫层可被沉积以产生实质上共形的衬垫。共形是指所沉积的膜层在水平表面与垂直表面二者上具有一致的厚度，或阶梯覆盖率等于约1。衬垫也可形成为基板的其他层上，所述其他层包括垫氧化物与浮置栅极。此衬垫助于避免硅通过可用于填充间隙的较低品质的可流动介电质短路，该等介电质可用于填充间隙是因为该等介电质有较佳的间隙填充品质，诸如可流动性。一些实施例中，介电衬垫层通过较无法流动或非可流动的沉积技术所沉积，该沉积技术可以是HDP-CVD，或在其他实施例中可为诸如HARP的SACVD或诸如等离子体增强TEOS与氧（或TEOS与臭氧）的PECVD。沉积的介电质可包括硅氧化物，诸如无掺杂的硅土（silica）玻璃或掺杂的硅土，诸如磷硅酸盐玻璃、硼硅酸盐玻璃、或硼磷硅酸盐玻璃。另外其他的介电质可包括氮化硅与氮氧化硅。
HDP沉积产生具HDP品质氧化物（诸如氧化硅）的衬垫层以作为第一介电层，该第一介电层具有比由可流动工艺沉积的氧化物高的第一密度以及整体品质。HDP膜是由以下方式产生：在低压或甚至真空（经常是以射频能量）激发反应物气体，而在接近基板表面处建立等离子体。等离子体能量使元素具高度反应性且产生高密度与高品质膜。其他实施例中，可在基板上执行热工艺，以产生衬垫氧化物层，其中通过将基板加热至高温而引发反应物气体的化学反应，以诱导膜的反应与形成。
可沉积第二介电层115，此步骤是由可流动沉积方法所产生，该方法可包括例如旋涂玻璃或可流动CVD。一些实施例中，可流动CVD用于覆盖介电衬垫层并且填充基板中的沟槽。可流动氧化物可通过以下步骤形成：分开激发前体气体，之后使这些前体气体在基板正上方的处理腔室的区域中结合，而产生可流动氧化物，该可流动氧化物于沟槽顶部开始流动，之后向下流动以将该可流动氧化物填入而不至于建立空洞或接缝。第二介电层具有第二密度，该第二密度低于衬垫层的第一密度。除了填充沟槽外，一些实施例中，可流动氧化物可额外填充在垫氧化物层（诸如氮化硅）之间，或对于包括产生例如NAND闪存的情况而言，该可流动氧化物额外地可填充在多晶硅浮置栅极之间。
沉积后，可使用许多方法沉积最初可流动的介电层。例如，可使用可流动CVD工艺，其中将硅前体导至容纳基板的基板处理区域。另一前体仅在通过远端等离子体区域而建立自由基前体（诸如氮前体）后导入，该前体随后流进基板处理区域并且与硅前体结合。此技术中，含硅前体并未直接被基板处理区域中施加的等离子体功率所激发。反而，等离子体功率只激发基板处理区域外的前体。此安排方式造成含硅与氮的层以可流动式沉积进入受衬的沟槽中。膜的可流动性随着沉积进展而衰减，且可流动性在下文所述的固化操作期间基本上消除。
含硅前体可含有碳及/或氮，以确保间隙填充的介电层形成期间的可流动性。一些实施例中，含硅前体可以是无碳的含硅前体，该无碳的含硅前体使间隙填充层能够在固化工艺期间历经较少收缩。除了其他类型的硅前体之外，该无碳的硅前体特别可以是例如硅与氮前体、硅与氢前体、或含硅氮与氢的前体。这些前体的特定范例可包括硅烷胺，除其他硅烷胺之外，该前体特别诸如为H2N(SiH3)、HN(SiH3)2、与N(SiH3)3。这些硅烷胺可以与额外气体混合，该额外气体可用作如载气、反应性气体、或前述两种气体。这些额外气体的范例除其他气体之外特别可包括H2、N2、NH3、He与Ar。无碳的硅前体的范例也可包括甲硅烷（SiH4），该甲硅烷为单独存在或与其他含硅气体（例如N(SiH3)3）、含氢气体（例如H2）、及/或含氮气体（例如N2、NH3）混合。含硅前体也可包括不具有碳或氮的硅化合物，诸如甲硅烷、乙硅烷等。若沉积的氧化物膜是受掺杂的氧化物膜，也可使用掺质前体，该掺质前体除了其他硼与磷掺质之外特别诸如为TEB、TMB、B2H6、TEPO、PH3、P2H6、与TMP。
氮可纳入自由基前体与含硅前体的任一者或二者中。当氮存在于自由基前体中时，可称为自由基氮前体。该自由基氮前体包括等离子体流出物，该等离子体流出物通过激发等离子体中较稳定的含氮前体而建立。例如，含有NH3及/或联氨（N2H4）的相对稳定的含氮前体可在腔室等离子体区域或处理腔室外的远端等离子体系统（RPS）中被激活，而形成自由基氮前体，该自由基氮前体随后输送进入无等离子体的基板处理区域。不同实施例中，该稳定的氮前体也可以是包含NH3与N2、NH3与H2、NH3与N2与H2、以及N2与H2的混合物。N2与H2的混合物中也可使用联氨以取代NH3或与NH3结合使用。不同实施例中，稳定的氮前体的流速可为约200sccm或更大、约300sccm或更大、约500sccm或更大、或者是约700sccm或更大。含氮前体也可包括N2O、NO、NO2、与NH4OH。
所产生的自由基氮前体可包括·N、·NH、·NH2等的一或多者，且可伴随在等离子体中形成的离子化物种。其他实施例中，自由基氮前体在处理腔室的一区块中生成，该区块与基板处理区域分隔，在该基板处理区域，该等前体混合并且反应而沉积含硅与氮层于沉积基板（例如半导体晶圆）上。该分隔可并入供应反应物至基板处理区域的喷头。该自由基氮前体也可伴随载气，诸如氩气、氦气等。氧可被同时递送进入远端等离子体区域（以O2及/或O3的形式），以调整自由基氮前体中以及用此技术沉积的衬垫或间隙填充层中的氧含量的量。
该可流动性可能（至少部分地）是由于沉积膜中显著的氢成份。例如，沉积的膜可具有硅氮烷形式的Si-NH-Si骨架，即Si-N-H膜。可流动性也可能是由于硅氮烷形式的短链聚合物所致。使短链聚合物与可流动性形成的氮可源自于自由基前体或含硅前体的任一者。当硅前体与自由基氮前体为无碳时，沉积的含硅与氮膜也是实质上无碳。当然，无碳并非必然意味该膜缺乏甚至痕量的碳。碳污染物（contaminants）可存在于前体材料中而找到该碳污染物进入沉积的含硅与氮膜的途径。然而，这些碳杂质的量远低于具有碳基团的硅前体（例如TEOS、TMDSO等）中可见的量。
其他实施例中，第一与第二介电层二者皆为可流动或可能皆为不可流动。一些实施例中，介电质通过不同机制沉积（例如第一介电质为不可流动，第二介电质为可流动），但取决于使用的反应物而具有类似的介电品质。尚有其他实施例，该第一介电质与该第二介电质由相同机制沉积，但具有不同品质，这是由于使用不同反应物物种于该两个介电质之故。
当基板温度在沉积含硅膜期间维持在相对低温的同时，可流动膜的生长可持续进展。该可流动氧化物膜可于低温下沉积在基板表面，该低温是通过在沉积期间冷却基板所维持。基座可包括加热及/或冷却导管，该等导管在不同的实施例中将基座与基板温度设定在约-40℃至约1000℃之间、约100℃至约600℃之间、低于约500℃或处于约400℃或更低。
已将可流动介电质沉积在基板上之后，可执行蚀刻工艺以移除过多的介电质，以为后续的整合无源器件制造步骤做好准备。一些实施例中，干式蚀刻剂气体用于蚀刻该介电层120。该蚀刻剂移除第一衬垫层与第二介电层二者的一部分。包括在该蚀刻剂中的气体可包括在进入半导体处理区域之前先通过远端等离子体区域而要被激发的气体。该蚀刻剂可包括含氟化合物与分子氢，且与介电层反应而产生固体副产物，该固体副产物会在基板温度提升到超过升华温度时升华，从而移除过多的介电质。移除第一介电衬垫层与移除第二介电层的蚀刻速率比可为约1:2，或在其他实施例中可为约1:1.5、1:1.3、1:1.2、1:1.1、或约1:1。当蚀刻速率比等于1:1时，各别的介电质以相同速率被移除。
一些实施例中，干式蚀刻剂气体含有三氟化氮与分子氢。在其他实施例中，该干式蚀刻剂气体实质上无氨气。三氟化氮与氢的干式蚀刻剂气体的组合可产生较缓慢的反应，该较缓慢的反应相较于包括氨气的干式蚀刻剂气体对氧化物的品质较不具选择性。添加氨气可减少反应性物种中氟的浓度，而产生氟化铵与氟化氢铵。这些产物以一较快的速率移除较低密度与较低品质的可流动介电质，移除得比移除较高密度、较高品质的衬垫氧化物层（通过例如HDP沉积）快。因具有更为接近1:1的针对HDP氧化物的选择性，相较于包括氨气的干式蚀刻剂气体，该实质上无氨气的干式蚀刻剂气体能够产生具有较不凹陷的转角轮廓的凹部。一些实施例中，实质上无氨气的干式蚀刻剂气体产生抵靠凹部侧壁的实质上平整的转角轮廓。
可流动的介电质可在沉积之后固化，以改良介电膜品质。各实施例中，固化可在氧化环境（如蒸汽）、惰性环境（诸如氮气）、或其他环境中执行。膜的可流动性随着沉积进展而衰减，且可流动性基本上在固化操作期间消除。该固化操作可涉及将含硅与氮的层转换成氧化硅。固化涉及提升图案化基板的温度，以及将间隙填充介电层暴露至含氧环境。一些实施例中，升高的温度诱导氧化物从衬垫层扩散进入间隙填充层，而提供来自间隙填充介电层下方的额外氧来源。该固化可以是退火，且可在低于约1000℃的温度下执行。其他实施例中，固化可发生在低于约800℃、600℃、500℃、400℃、300℃、或低于约200℃。利用可流动介电质可减少制造工艺的热预算，且在一些情况中，该工艺可在低于约600℃、500℃、400℃、300℃、200℃、或低于约100℃下执行，以维持可流动的介电质。
现在参考图2，在此描述蚀刻介电材料的方法200，该介电材料位在半导体基板上的选择性材料的多个区块之间。该方法包括沉积选择性材料覆于半导体基板上（210）。选择性材料可以是期望在移除另外材料（separate material）的同时还维持住的任何材料。例如（且并非意欲限制本发明），该选择性材料可以是在闪存单元中做为浮置栅极的多晶硅。另一材料（诸如介电质）可与选择性多晶硅共同位于基板上。一些实施例中的目的可为移除介电材料的同时维持选择性多晶硅。在这样的情况中，该介电质可通过限制移除或不移除多晶硅的方式移除。此举可用优先移除该介电质的特殊蚀刻技术执行。例如，利用与氧化物或氮化物反应但不与多晶硅反应的干式蚀刻剂气体提供了一种移除介电质的同时维持选择性材料的方式。其他实施例中，该选择性材料是硅、沉积的金属、介电质、或可沉积在基板上的任何其他材料，其中该目的是在移除另外材料期间移除显著少量的选择性材料。
已沉积选择性材料之后，可蚀刻沟槽穿过选择性材料215，且在一些例子中是蚀刻沟槽穿过半导体基板。该蚀刻建立位于半导体基板上的选择性材料的隔离区块，该等区块被蚀刻的沟槽所分隔。该等沟槽可显示高深宽比，其中沟槽深度可显著地比该沟槽的宽度还大。示范性的沟槽可具有约2:1或更大、约3:1或更大、约5:1、约7:1、或约10:1或更大等的深宽比。
该方法可进一步包括沉积介电材料于该沟槽内220。该沉积可包括完全填充该沟槽以及沉积充分的介电质以覆盖该选择性材料，或在其他实施例中，该沉积可部分填充该沟槽。该介电质可沉积越过基板的高度（level），使得该介电质至少部分填充在选择性材料的隔离区块之间。取决于沟槽的特性，可通过可流动或非可流动的方法沉积介电材料。在一些窄且深的沟槽的实施例中，可用可流动的方式沉积该介电质，以限制空洞发展的可能性。其他实施例中，更高品质的介电质可用于场部件之间改良的绝缘。一些实施例中，使用旋涂玻璃沉积介电材料。替代性实施例中，介电材料是通过可流动CVD所沉积。
一些实施例中，可执行多种介电质沉积而填充该沟槽。例如，在沟槽被可流动介电质填充之前，可将衬垫层沉积在该沟槽内。这样的组合可提供以下优点：改良对衬垫层的绝缘，以及改良可流动介电质的填充特性。额外范例包括以一系列步骤沉积介电质，该等步骤包括沉积与往回蚀刻介电质，以尽量减少面包状现象（bread-loafing）与空洞形成。最初的介电层可沉积在沟槽中，之后进行中间蚀刻工艺，以移除沿着沟槽顶部的介电质堆积。蚀刻后，可用后续介电材料的沉积填充沟槽的其余部分。
可在沉积介电层后执行蚀刻工艺225。该蚀刻可包括将基板暴露至干式蚀刻剂气体，该干式蚀刻剂气体移除选择性材料的隔离区块之间的一部分介电层，而形成凹部。该干式蚀刻剂气体可以是包括含氟化合物以及分子氢的气体混合物。该等气体可分别流进基板所处的处理腔室，且在一些实施例中，该干式蚀刻剂气体在流进处理腔室之前被远端等离子体源激发。一些实施例中，干式蚀刻剂气体实质上无氨气，而可提供较慢的反应，且有较大量的氟自由基可用于反应。使用实质上无氨气的干式蚀刻剂气体可产生具有实质上平整的转角轮廓的凹部，这是由于防止氟自由基还原成包括氟化铵与氟化氢铵的产物所致。干式蚀刻剂气体可完全无氨气，以进一步防止因形成中间化学物质（包括氟化铵与氟化氢铵）所造成的氟自由基移除。
一些沉积中，介电层沉积成远高于选择性材料的高度，且可执行中间的介电质移除。诸如化学机械研磨之类的工艺可用于移除过多的介电质。选择性材料可用做为蚀刻停止层，该蚀刻停止层可例如为场栅极多晶硅或氮化硅。一旦介电质已被移除降至选择性材料层，则干式蚀刻剂可用于移除位于选择性材料的区块之间的介电质。
可基于选择性材料的有效场高度移除位在选择性材料的区块之间的介电质。例如，该介电质可被蚀刻至介于约200埃至约1200埃之间。额外的范例可具有被蚀刻至介于约400埃至约1000埃之间、介于约600埃至约800埃之间等的介电质。有多个选择性材料区块且有在这些区块之间必须移除介电质的多个区域时，干式蚀刻剂气体可提供单元至单元间（cell to cell）变化低于约10nm的凹部。示范性的单元间（intercell）凹部深度之间的有效场高度变化低于约8nm或低于约6nm。干式蚀刻剂气体可提供单元之间的蚀刻一致性，其中单元凹部深度与形状之间的偏差低于5%。单元深度与形状之间的差异可低于约3%、约2%、约1.5%、约1%、约0.5%、约0.1%等。
在介电质已从选择性材料的区块之间移除之后所得的凹部轮廓可具有底部（floor），该底部由基板的浅沟槽隔离中的残余介电材料所界定。该底部的轮廓可在横越该介电质至介电材料与选择性材料交会处的位置为止皆为实质上平整。此交会点可界定凹部的转角，且介电材料的转角轮廓可为与选择性材料呈大约直角。当界定凹部的介电材料基底部与选择性材料壁之间形成直角时，平整的转角轮廓业已形成。可形成超过或低于90°的角度，在此情况中，转角轮廓可为实质上平整。于转角处可能无法完全移除介电质，而在凹部转角产生介电质的稍微凹陷。尽管该凹陷可能无法界定出完美的圆形剖面，然而该凹部侧边与基底部的曲率半径可低于约5nm。在一些实施例中，该曲率半径可能低于约3nm、2nm、1nm、5埃、3埃、2埃、或约1埃，从而提供实质上平整的转角轮廓。
该介电质可在沉积后且于蚀刻前固化，以改良介电膜的品质。固化可通过任何先前所讨论的方法执行。该固化可以是退火，且可在低于约1000℃的温度下执行，例如，该固化可发生在低于约800℃、600℃、500℃、400℃、300℃或低于约200℃。利用可流动介电质可减少制造工艺的热预算，且在一些情况中，该等工艺可在低于约600℃、500℃、400℃、300℃、200℃或低于约100℃下执行，以维持可流动的介电质。
一些实施例中，已知为穿隧氧化物的氧化物层沉积在半导体基板与选择性材料之间，以确保浮置栅极的隔离。该穿隧氧化物是在最初沉积选择性材料与形成沟槽之前沉积。沟槽中与选择性材料区块之间所沉积的介电质可被蚀刻降至穿隧氧化物的高度。或者，该介电材料可以被蚀刻至选择性材料区块之间，但不被蚀刻降至穿隧氧化物的高度。
已从选择性材料区块之间蚀刻介电材料后，可发生后续的制造。隔离层可沉积于选择性层上以及蚀刻后的凹部中。此隔离层可提供例如浮置栅极与控制栅极（可在之后沉积）之间的衬垫。另一材料（诸如金属、介电质、或某些其他材料）的沉积物可在隔离层已铺设后沉积。该后续材料可以是多晶硅，用作为闪存单元（诸如NAND闪存元件）中的控制栅极。蚀刻后的介电凹部的实质上平整的转角轮廓能够使后续整合的无源器件层填充在（例如）宽度可为几纳米的沟槽内。当隔离层与后续的控制栅极层沉积在具有实质上平整的转角轮廓及/或较佳的单元一致性的凹部内时，可因提供改良的界面供IPD规模缩放而防止进一步的整合问题。
现在转至图3A，剖面视图中显示基板310，在该基板310上已执行根据本发明的方法的蚀刻工艺。穿隧氧化物320沉积在基板310与选择性材料325之间。该选择性材料325可以是金属、介电质、或氧化物，或者是某些其他材料。在一些实施例中，选择性材料325可以是多晶硅，该多晶硅可受掺杂或不受掺杂。沟槽315建立在该等层中，且被介电材料319填充。该介电材料可在沉积后最初为可流动，且可在沉积后固化。该介电质随后可往回蚀刻而形成具有转角335的凹部单元330。该蚀刻工艺可使用含氟气体与分子氢的干式蚀刻剂气体混合物，且该干式蚀刻剂气体实质上无氨气。虽然转角335显示些微凹陷，其他实施例可使该等转角在界定凹部单元330的介电质底部与选择性材料壁之间的界面处平整或实质上平整，而建立直角的交会。图3A的剖面视图可以是处理半导体器件的中间步骤，该处理将包括沉积后续材料层（诸如多晶硅）于所形成的凹部单元内。此后续材料可在形成隔离层或衬垫层于选择性材料上及凹部内之后沉积。该介电层319可包括衬垫层与额外的间隙填充介电层二者。
图3B中，剖面视图显示基板310，在该基板310上已执行根据本发明的方法的蚀刻工艺。基板310具有垫层340，该垫层340于形成沟槽315前沉积。沟槽形成后，可沉积介电衬垫材料317。衬垫317可例如通过HDP沉积来沉积。接着，在沟槽315内沉积介电材料319于衬垫层317上。介电材料319可在沉积后最初为可流动，且可在沉积后固化。介电材料319可与介电衬垫层317具有相同或不同的品质及/或密度。例如，衬垫层319可比介电材料319具有更高品质。
介电质319可于垫氧化物340上方延伸，且可在最初以诸如化学机械抛光之类的工艺移除而降至垫氧化物层。可执行蚀刻工艺，其中干式蚀刻剂气体混合物用于移除介电材料319与介电衬垫层317。干式蚀刻剂气体混合物可包括含氟气体与分子氢，且可实质上无氨气，或完全无氨气。该干式蚀刻剂气体移除介电材料319与衬垫层317，而产生包括转角335的凹部330。该转角335的轮廓可实质上平整，这是指介电材料319与介电衬垫317被移除至实质上相同的深度。移除至同等深度是指干式蚀刻剂气体实质上对氧化物品质不敏感。
范例
在使用有氨气及无氨气的蚀刻剂气体混合物的蚀刻选择性之间制作比较性范例。这些蚀刻是在先衬以HDP衬垫层再以可流动氧化物填充的沟槽上进行。该等介电质暴露至含有三氟化氮与分子氢的干式蚀刻剂气体混合物。一个范例中，该干式蚀刻剂气体也含有氨气，而在比较性范例中，该干式蚀刻剂气体实质上无氨。如下文中的表1所见，含有氨气的干式蚀刻剂气体比实质上无氨气的干式蚀刻剂气体移除较多的可流动氧化物（相较于HDP氧化物）。
表1：干式蚀刻剂气体的蚀刻深度
图4A与4B显示已执行蚀刻后的基板的比较TEM影像。图4A显示已在上面执行利用氨气的蚀刻的基板。影像中所见的转角轮廓显示凹陷，这是指于沟槽内并未一致地移除介电质。然而，图4B显示在上面以实质上无氨气的干式蚀刻剂气体执行蚀刻的基板。如影像中可见，转角轮廓实质上平整，其中介电层交会氮化物垫，而建立几乎成直角的转角轮廓。平整的转角轮廓是指，在沟槽内一致地移除介电质。
已揭露数个实施例，本领域的普通技术人员将理解，可使用各种修饰、替代性架构、与等效物而不背离所揭露的实施例的精神。此外，在此并未描述许多已知的工艺与元件，以避免不必要地混淆了本发明。因此，前述的说明书内容不应被视为限制本发明的范畴。
请注意，可将个别的实施例描述成以流程图、流程的示意图、或方块图所绘的工艺。虽然流程图可将方法描述为依序的工艺，但可平行或同时执行该等操作中的许多操作。此外，可重新排列操作顺序。当完成工艺的操作时，可终结工艺，但该工艺可有不在图中讨论或包括在图中的额外步骤。再者，任何特定描述的工艺中并非所有操作可发生在所有实施例中。工艺可对应方法、函数、程序、子例程、子程序等。当工艺对应函数时，该工艺的终结对应函数返回至调用函数或主函数。
当提供一数值范围时，应了解，除非上下文中另外清楚地指示，否则也特定地揭露该范围的上限与下限之间的每一居中数值（该数值至下限单位的最小的小数）。也涵盖了陈述的范围中任何陈述数值（或居中数值）以及该陈述范围中的任何其他陈述数值（或居中数值）之间的每一较小范围。在该陈述范围中的任何特定被排除的极限的条件下，这些较小范围的上限与下限可独立地被包括在该范围中或自该范围被排除，且本发明内也涵盖了在该等较小范围中包括任一、无一、或两个极限的每一范围。当所陈述的范围包括该等极限的一者或二者时，也包括了排除这些所包括的极限的任一者或二者的范围。
如在此以及所附的申请专利范围中所用，除非上下文另外清楚地指示，否则单数形式的“一”、“该”、与“所述”包括数个参考物。因此，例如“一介电材料”所指的参考物包括数个此类材料，且“该应用”所指的参考物包括一或多个应用及本领域普通技术人员已知的该等应用的等效物与诸如此类的物的参考物。
同样，“包含”与“包括”等词汇在用于此说明书及随后的权利要求书时，申请人希望该等词汇指定存在陈述的特征、整体、部件或步骤，但这些词汇不排除一或多个其他特征、整体、部件、步骤、动作或群组的存在或增加。

Claims (15)

1.一种在半导体基板中蚀刻凹部的方法，所述方法包含以下步骤：
形成介电衬垫层于所述基板的沟槽中，其中所述衬垫层具有第一密度；
至少部分位在所述沟槽中于所述衬垫层上沉积第二介电层，其中所述第二介电层在沉积后最初为可流动，且其中所述第二介电层具有第二密度，所述第二密度低于所述衬垫层的第一密度；
将所述基板暴露至干式蚀刻剂，其中所述蚀刻剂移除所述介电衬垫层与所述第二介电层的一部分而形成所述凹部，其中所述干式蚀刻剂包括含氟化合物与分子氢，其中所述介电衬垫层和所述第二介电层在400℃或更低的温度下沉积与蚀刻，且其中移除所述介电衬垫层与移除所述第二介电层的蚀刻速率比为1:1.2至1:1。
2.如权利要求1所述的方法，其特征在于，所述介电衬垫层包含高密度等离子体形成的氧化硅层。
3.如权利要求1所述的方法，其特征在于，所述第二介电层包含由FCVD所沉积的氧化硅层。
4.如权利要求1所述的方法，其特征在于，所述含氟化合物包含NF3。
5.如权利要求1所述的方法，其特征在于，所述干式蚀刻剂实质上无氨气。
6.如权利要求1所述的方法，其特征在于，所述凹部具有实质上平整的转角轮廓。
7.如权利要求1所述的方法，进一步包含以下步骤：在所述第二介电层沉积之后，固化所述第二介电层。
8.一种蚀刻介电材料的方法，所述介电材料位在半导体基板上的选择性材料的多个区块之间，所述方法包括以下步骤：
沉积选择性材料于半导体基板上；
在所述选择性材料与半导体基板中蚀刻至少一个沟槽，所述至少一个沟槽在所述半导体基板上建立至少两个彼此隔离的选择性材料的区块；
在所述沟槽中形成第一介电层作为衬垫层；
将第二介电材料沉积于所述沟槽中，其中所述第二介电材料至少部分填充于所述选择性材料的隔离区块之间；以及
将所述基板暴露至干式蚀刻剂气体，所述干式蚀刻剂气体移除所述选择性材料的隔离区块之间的所述第一介电层和所述第二介电材料的一部分而形成凹部，其中所述干式蚀刻剂气体包括含氟化合物与分子氢，其中所述第一介电层与所述第二介电材料在400℃或更低的温度下形成与蚀刻，且其中移除所述第一介电层与移除所述第二介电材料的蚀刻速率比为1:1.2至1:1。
9.如权利要求8所述的方法，其特征在于，所述干式蚀刻剂气体实质上无氨气。
10.如权利要求8所述的方法，其特征在于，所述选择性材料是多晶硅。
11.如权利要求8所述的方法，进一步包含以下步骤：在沉积所述选择性材料之前，沉积穿隧氧化物于所述半导体基板上，其中所述选择性材料被沉积在所述穿隧氧化物上。
12.如权利要求8所述的方法，其特征在于，所述介电材料由可流动CVD所沉积。
13.如权利要求8所述的方法，其特征在于，所述凹部具有实质上平整的转角轮廓。
14.如权利要求8所述的方法，进一步包含以下步骤：在所述第二介电材料沉积之后，固化所述第二介电材料。
15.如权利要求14所述的方法，其特征在于，所述第二介电材料在400℃或更低的温度下固化。
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US8927390B2 (en) 2015-01-06
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WO2013049173A3 (en) 2013-06-13
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