TWI337775B - Partially patterned lead frames and methods of making and using the same in semiconductor packaging - Google Patents

Partially patterned lead frames and methods of making and using the same in semiconductor packaging Download PDF

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Publication number
TWI337775B
TWI337775B TW096140480A TW96140480A TWI337775B TW I337775 B TWI337775 B TW I337775B TW 096140480 A TW096140480 A TW 096140480A TW 96140480 A TW96140480 A TW 96140480A TW I337775 B TWI337775 B TW I337775B
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TW
Taiwan
Prior art keywords
wafer
lead frame
lead
package
region
Prior art date
Application number
TW096140480A
Other languages
English (en)
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TW200834859A (en
Inventor
Mary Jean Ramos
Anang Subagio
Lynn Simporios Guirit
Antonio Romarico Santos San
Original Assignee
Unisem Mauritius Holdings Ltd
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Publication date
Priority claimed from US11/553,664 external-priority patent/US7799611B2/en
Application filed by Unisem Mauritius Holdings Ltd filed Critical Unisem Mauritius Holdings Ltd
Publication of TW200834859A publication Critical patent/TW200834859A/zh
Application granted granted Critical
Publication of TWI337775B publication Critical patent/TWI337775B/zh

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    • HELECTRICITY
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    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828Etching
    • H01L21/4832Etching a temporary substrate after encapsulation process to form leads
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    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L23/49503Lead-frames or other flat leads characterised by the die pad
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九、發明說明: 【發明所屬之技術領域】 此申請案係2_年10月27日提出的序列號第ιι/553,664 號之部分接㈣請案,該申請㈣则年…日提出的序 列號第U/197,944號之部分接續申請案,該申請案係讓 年8月丨0曰提出的序列號第1〇/916,〇93號(現在為仍 7,129,Η6)之接續中請案,該中請㈣·2年4月29日提出 的序列號第io/m’m號(現在為us 6,812,552)之接續申請 案。所有此等申請案係全部以引用的方式併入本文中。 本發明-般係關於電子封裝,I更特定言之,係關於一 部份圖樣化之引線框及製造其與使用其之方法。該部份圖 樣化之弓丨線框係比傳統引線框堅固且穩定。該部份圖樣化 之引線框之堅固會改良製造引線框封裝之程序並增強最終 產品之總可靠性。引線框亦為裝置整合及增加功能提供高 度的撓性。 【先前技術】 在製造使用引線框之電子封裝中,存在若干程序步驟, 其使引線框經歷機械及熱應力。目前引線框之較細小幾何 形狀以及半導體晶片上的電路之不斷增加整合已產生將更 大應力置於引線框上的處理。精細組態的引線框通常類似 於很精緻的刺繡或模板狀金屬結構,其傾向於輕易彎曲、 斷裂、毀形及變形。(參見圖la及丨b)。此類傳統引線框係 在工業中用以建立各種晶片封裝,包含線路接合及覆晶 (FC)封裝。(參見圖2a至2d以及圖3a至3b)。 I26204.doc 133^775 u fc 傳統引線框一般缺乏結構剛性。引線框的指狀部分可以 係相當脆弱且難以固持在適當位置。此導致組裝程序中的 處理缺陷、損壞及扭曲以及複雜線路接合情形。因此,必 須最佳化接合參數以補償接合程序期間的引線跳動。未能 最佳化接合參數以補償引線框之機械不穩定性可能產生較 差的接合黏著,並因此產生較差品質及較差可靠性之接 合0
典型引線框之較大金屬板部分從一中心部分延伸
Λ 〜部分係已知為晶片接收區域,且亦瞭解為晶片墊。晶片 通常係在背側向下的情況下附著於該接收區域,並且前側 係面向上固定,其中端子係以周邊形式定位在晶片之周長 上,或以陣列之形式定位在晶片之表面上。該接收區域通 常具有約5 mm x 5 mm的尺寸,並且從晶片墊區域向外延 伸的引線具有約1〇 _長χ 1 _寬父〇2 _厚之典型尺 寸。通常藉由真空夾頭及機械夹具來固持引線框。必須針 對不同大小及形狀的引線框來改裝夾頭及夾具。本發明減 輕此問題。 先前技術尚未顯示可以耐受目前半導體封裝程序中遇到 的應力以及可採用成本效益方式加以製造的任何引線框。 本發明藉由下列方式達到此目的:提供部㈣樣化之引線 框’其不僅改良引線框本身的可製造性,而且改良從其形 成的電子封裝之整體性及可靠性 框不能提供的針對增加夺置…本發月亦解決傳統引線 17複雜性之連續需求,例如高 夕晶片設計、系統封裝以及選路方面的撓性。 126204.doc 【發明内容】 引線框係由具有一頂部表面及一底部表面之一膜組成。 該膜之一第一區係從該頂部表面部份圖樣化但並非完全透 過該膜至該底部表面。未從該頂部表面圖樣化之該膜之一 第二區形成一用以支撐一積體電路(1C)晶片的晶片接收區 域,以及用以提供與該1(:晶片之電連接的複數個引線接 點。該第一區在該膜中形成溝渠並建立一網式結構,其與 未從該頂部表面加以部份圖樣化的該第二區互連。本發明 亦係關於製造部份圖樣化之引線框之方法以及利用該等引 線框之電子封裝。本發明之引線框因其網狀或網式結構而 具有改良式結構剛性。 依據本發明,一金屬膜(引線框欲從其加以形成)之頂部 表面係首先使用標準光微影技術或類似技術而圖樣化以確 定將對應於一晶片接收區域及引線之區域的外形。在下一 步驟中,在具有該外形之區域外面的該膜之第一區中從該 膜之頂部表面部份透過底下膜之厚度執行蝕刻’以在該膜 中建立-引線框圖樣。在部份圖樣化之後,未從該頂部表 面加以圖樣化的其餘區域形成—第二區,其將用作沿該頂 部表面的一晶片接收區域及引線。該第一區在該膜之頂部 表面下面形成-凹入網式區。該第一區之網式結構將引線 部分彼此連接並與該晶片接收區域連接。因此,部份圖樣 化膜看似網式腳並料其_及強度,因此其可以财受隨 後製程步驟之力1定言之,部份圖樣化之引線框可以耐 受在線路接合及囊封程序期間遇到的力。在某些具體實施 126204,doc 1337775 例中’可以從該第二區之相同部分形成該晶片接收區域及 電引線(例如’在電引線支撐積體電路並提供與其之電連 接的情況下)。 本發明亦提供使用部份圖樣化之引線框製造複數個電子 封裝之一獨特方法。該方法包含具有一頂部表面及一底部 表面之一膜。在該第一區中,該膜係從該頂部表面但並非 完全透過該膜至該底部表面而部份圖樣化。該獏上未從該 頂部表面加以部份圖樣化的其餘第二區形成複數個部㈣ 樣化之引線框。該等引線圖之每一個因此具有用以支揮一 積體電路(1〇晶片的-晶片接收區域以及用以提供與該κ 晶片之電連接的複數個電引線。 該膜之該第一區形成一網式結構,其將每一個引線框之 該等晶片接收區域與電引線互連。該第一區亦在該膜之街 道形部分中將複數個引線框彼此連接。 提供複數個晶片’每一個晶片具有複數個電端子以附著 !一對應引線框。每-個晶片係附著於-對應引線框上的 晶片接收區域並且—雷,鱼
A 子與引線框的電引線之 在母一個晶片的至少一個端 膜之 ,之一之間形成。然後,在引線框及該 邻—#上應用—囊封物材料以完全覆蓋該膜之頂 ;表=烘乾該囊封物材料,則在該第-區中從該膜之底 ==:圖樣化程序以移除網式結構以及該膜之* 物材料以形成置在該膜之街道形部分上的該囊封 在—較佳具體奋执 只包例中,該方法包含在以區塊/視窗圖 126204.doc 1337775 樣之形式的矩陣中將引線框形成於該 片級封裝。 膜中,並包含產生晶 若干優點出自本發 。丨伤圖樣化之引線框。引線框之
〜"外低u Ή深 扁平及實心未㈣底部表面在線路接合程序期間作為一優 良散熱片。此提供均句的熱轉移以獲得較佳且較一致的接 合品質"匕外’該實心結構為萬用真空失頭提供連續表面 以固持引線樞’從而在隨後的程序步驟期間使晶片附著程 序更穩定以及引線更牢固。消除難以夾緊引線框之外部邊 緣以在不需要轉換的情況下允許進行陣列矩陣弓丨線框設計 及處理。因為部份圖樣化之引線框之底部側係_扁平連續 表面’所以萬用真空夾頭可用以固持許多不同大小的引線 框。此移除每次在封裝程序中使用不同尺寸之引線框時必 須改裝真空夾頭之複雜。此外,不需要進一步夾緊。萬用 真空夾頭之使用以及夾緊之消除致能在第二區上構造雙或
三列交錯引線以獲得較高引線計數。 本發明係關於不僅適應線路接合晶片而且適應焊料凸塊 覆aa之部伤圖樣化之引線框◎此外,本發明教導下列方 Λ
法:將部份圖樣化之引線框用以製造使用線路接合的蝕刻 引線框封裝(ELP)、具有覆晶的ELP(ELPF)、以及具有平A 栅格陣列(LGA)墊之ELP或ELPF以形成蝕刻平台柵格陣列 (ELGA)封裝,如本發明之具體實施例中進—步說明。 覆晶(FC)技術係朝一晶片上的電端子與下一位準封參, 即與一陶瓷或塑膠基板,或與後來與該基板接合之一晶片 微載體的完全自動接合之一或多個步驟。稍大於該晶片本 126204.doc •10· 2錢載體現在係稱為晶片級封裝(csp)。^術從夥 I自動接W)發展而來,該接合依次使其原點處於線 :接合(WB)中。然而—B中,將晶片固定在其背 面上並且與定位在其頂部表面上的周長周圍之端子電連 接,在FC技術中’倒轉晶片之方位。將晶片放置成面向下 而且將晶片之背側定向為向上。此覆晶方位具有重要優 因為其將電功能集令在晶片之下側上’從而使頂側保 自由以用於進行南度有效率的熱轉移設計。 在FC程序中,晶片端子或接合墊係採用晶片之表面上的 不同類型之凸塊而密封,其中該等圖樣可在區域陣列、周 邊圖樣或其他圖樣中展開。可採用下財式將晶片附著於 下位準.a)將Fc附著於一引線框;b)已知為插入物的層/ 基板之FC附著,以對一引線框上的連接間距進行重新選 路’ C)將FC附著於—引線框上的預附著插入物;或幻使用 包含晶片回焊方法之傳統技術將FC附著於印刷電路板。 當在製造QFN(四方扁平無引線)封裝及其衍生物(例如 VFQPF-N)中將使用傳統技術的晶片附著應用於引線 框時,該晶片附著會變得尤其困難。此係因為傳統引線樞 一般缺乏結構剛性.引線框的指狀部分可以係相當脆弱且 難以保持在一個精確位置。此導致組裝程序中的處理缺 陷、損壞及扭曲以及複雜晶片接合情形,pc接合程序需要 將凸塊焊料頭與懸掛物及引線框之較脆弱引線端精確對 準。此外’濕潤的焊料端在透過焊料回焊程序放置之後必 須保持其位置。因此,必須最佳化回焊參數以補償晶片接 126204.doc 11 1337775 , 合期間的引線框跳動’其在未得到適當完成的情況下可產 生較差接合處’並因此產生最終產品的較差品質及較差可 - 靠性。 ^ 通常在實務上藉由下列方式來形成傳統模板狀引線框: ' 圖樣化金屬帶或金屬膜上的光阻,並透過圖樣而蝕刻以形 -. 成從晶片接收區域向外延伸的指狀引線。亦習慣於使用指 . 狀物之間的”連桿,,以便使手指在各種程序步驟期間保持隔 _ 開,如圖3&及3b所示。本發明藉由形成網狀部份圖樣化之 引線框替代模板狀引線框而減輕引線框之結構剛性的缺乏 問題。 依據本發明之—方法,從欲變為—引線框的膜之—側執 ^形成一半導體封裝之所有主要程序步驟。另一側(即底 邛側)在一表面(例如真空夾頭之表面)上保持扁平且未接 觸此包3囊封及密封該封裝之部份形成的前側之步驟。 心成囊封’則對底部表面進行背面蝕刻以選擇性地移 Φ &將引線彼此連接且與該晶片接收區域連接的網式部分。 在使S玄晶片與該晶片接收區域上的-晶片塾進行背面接合 4 1且藉由線路接合而進行與晶片端子的電連接之ELP情況 - &過_來切斷所有中間網式部分以便晶片墊及處於 線路接合端的引線接點現在係藉由包圍該晶片、該等線路 及線路接合接點區域之前表面的模製材料而彼此隔離。 然而’在ELPF封裝 衣 < 障況下’透過蝕刻切斷僅將引線彼 此連接的網或部八 m . 11刀,因為與晶片焊料頭凸塊連接的引線本 身""供與下—位準封震之電連接。 126204.doc 1337775 透過網式部分中的料度或街道形而移除嵌 有若干優點,其包含喷…六敘_ 31 裔八 .^ m 核在整則線框結構中傳播的鋸 ’並因此預防金屬-塑膠介面上的分層。此外,透過背 面㈣進行的電隔離致能任何鑛切或分割或者因該事件在 任何進一步的處理步驟 郑之别的帶測试。纟背面圖樣化之 後,可接著透過沈零餛、含、.主 錫’又/貝或無電鍍鎳電鍍採用任何數 的可焊材料以閃光方式完成底 、凡坎低#表面上的其餘及曝 部分。ELGA封裝使用弘 路孟屬 t裝之PC,然而將lga塾用於 與下一位準封裝的連接。 、 為預防在製造期間模製材料與封裝的其他組件之間的任 何分離’本發明亦教導如何在部份㈣之引線框之凹入網 式邰刀的曝路垂直壁上(例如在引線之側壁上)形成鎖定特 徵’其將與模製材料(例如樹脂)接觸。作為一替代例,亦 教導在晶片墊及引線接點之邊緣上形成”唇狀物,,以便捕獲
每一個唇狀物下面的榲塑妊扭 γ ,, A 扪杈氣材枓,從而使模製材料難以從配 合表面分離。 從以上5兒明應明白部份姓刻之引線框提供結構與附帶剛 性及強度之聯合以適當地耐受在製造電子封裝中各種製程 之應力及應變。其係因為此等獨特機械特性,所以部份蝕 刻之引線框封裝亦可以耐受線路與封裝之底部的超聲波接 «之嚴密以與下-位準封裝連接,此迄今尚不可能採用傳 統塑膠封裝來達到。 本發明之一態樣提供用於形成電子封裝之方法。該方法 包括形成具有選擇性地預電錢之頂部及底部表面的部份钱 J26204.doc 13 刻之弓丨線框之區塊。該等引線框包括網式部分並且係藉由 街道形部分而彼此分離。 一第一晶片集係附著於引線框上的晶片墊區域。為方便 起見’支揮一積體晶片(IC)或一 1(:晶片所附於的一引線框 之區域將稱為一晶片墊區域或一晶片接收區域,無論此區 域係用於線路接合晶片、覆晶或該技術中已知的任何其他 種類之晶片。此等第一晶片集可使用一黏著劑、樹脂或與 兩種成分相容的其他材料與晶片接收區域進行背面接合。 例如,可使用環氧樹脂、非導電環氧、膠帶或焊料膏來完 成背面接合。其他適當材料在該技術中已為人所知。 接著將一第二晶片集晶粒堆疊至對應第一晶片集之頂部 上。在將第二晶片集晶粒堆疊至第一晶片集之頂部上之 後,可將一或多個另外晶片集晶粒堆疊至第二晶片集之頂 部上,從而提供由彼此疊加的二、三或多個晶片組成之封 裝。在本發明之某些具體實施例中,並非自第一晶片集的 所有晶片均可具有晶粒堆疊在其上的晶片。在此類具體實 施例中,引線框將具有一或多個單一(未堆疊)晶片以及— 或多個晶粒堆疊晶片集。 在第曰曰片之母一個晶片的端子與對應引線框之電引線 部分之間形成電連接。電引線部分係與晶片墊區域電分 離。亦形成至第二或額外晶片集的電連接。在已將晶片晶 粒堆疊在引線框上之後,可同時形成電連接。或者第_ 晶片集可附著於引線框並與其電連接,而且隨後第二或額 外晶片集可晶粒堆疊至第一晶片集之頂部並與引線框電連 126204.doc 14 丄337775 接。 在將晶片晶粒堆疊至引線框上並與引線框電連接之後, 接著藉由在引線框及分離引線框的街道形部分上應用囊封 物材料來囊封引線框。在囊封之後,對引線框之底部表面 進行背面圓樣化以移除網式部分以及衝道形部分。可藉由 任何方便的方法(例如蝕刻)來執行背面圖樣化。
若將預電鍍材料應用於引線框之底部(例如作為光阻), 則可在背面圖樣化之後移除此預電鍍材料。 可以在背面圖樣化之後於引線框之底部上形成隔離圖 樣。可採用一材料來電鍍或塗布此等隔離圖樣以保護其表 面。適當材料之範例包含無電鍍Ni/沈積Au、沈浸Ag、沈 浸Sn、有機表面保護劑(〇sp)以及其他可焊材料。此完成 或電鍍步驟促進提供額外穩定性至晶片封裝之背表面並可 以提供改良式連接性至電腦板、插座或放置晶片封裝的其 他位置。
分割置放在衝道形部分上的囊封物材料來形成個別晶片 級封裝以用於半導體行業中的各種應用。可使用可用以分 離個別晶片封裝的任何方便構件來完成分割。在—具體= f 施例中,T藉由使用鑛或磨耗性喷水來切開囊封“ 分割。 本發明之另―態樣提供包括一晶片墊區域及引線且且有 變更的5丨線框。變更可視為定位在引線框之結構特訂的 元件:其在與不具有變更之引線框相比時提供增加表面區 域。變更促進在分割之前應詩引線框上的㈣物材料之 )26204.doc 1337775 保持力 切口。 交更可以係任何形式 例如引線框之電引線上的 ::片木之母—個晶片可以具有與對應第一晶片相同 命:不同大小。此外,附著於引線框的第-晶片集並 不需要係全部相同,且闵 „ , ^ a , 且因此此等第—晶片集可包含較大及 車乂小的晶片。—舶·ε_ 15?丨 ▲ 5 ,最大晶片將附著於晶片墊區域而 且不斷較小的曰y必 曰曰片將加以晶粒堆疊在此晶片之頂部上。在 替代性具體實施例φ,县
最大a曰片將不附著於該晶片墊區域 而將在晶粒堆疊晶Η & 士卩g < 登曰曰片的中間或頂部上。晶粒堆疊晶片亦可 全部係同一大小β 第—及額外晶片集可使用該技術中已知的將晶片彼此接 合之㈣方便構件堆疊於對應第並與其接合。例 如’可使用非導電環氧或絕緣材料(例如膠帶)來堆義曰片 以預防晶片之間或當中的干擾或電移動。在另一具:二 < J中第一 a曰片集可使用一膠帶、導電黏著劑或導電 附於對應第一晶片。 第一晶片集係使用已知技術與引線框電連接。例如,晶 片y使用 '線路接合技術或使用I晶技術與引線框連接。 可在將第—晶片集晶粒堆疊至第一晶片上之前將第一晶 片集,引線框電連接。或者,可在將第二或額外晶片集晶 粒堆且至對應第一晶片集上之後將第一晶片集可與引線框 電連接。可藉由將該晶片上的端子與延伸至晶片區域的電 引線之端部分連接來完成形成電連接之步驟。可使用任何 方便或適當技術形成電連接。例如’若晶片係線路接合晶 126204.doc 16 1337775 J 片,則可使用諸如熱聲波接合之線路接合技術來形成連 “ 接。一般使用覆晶技術將覆晶與引線框電連接。線路接合 與覆晶技術的組合係亦在本發明之範疇内。當將覆晶直接 / 附著引線框時,對應W線可以係電鍍或未電鍍的。 第二晶片集接收電源以執行計算或其他功能。此第二晶 片集可與對應第一晶片、引線框或兩者電連接。在各種晶 片與引線框之間形成的連接將取決於手邊的特定情形及= 成的特定電子封裝。 本發明中使用的晶月之類型將亦取決於特定情況。例 如,晶片可以係線路接合晶片、覆晶或適用於電子晶片封 裝的任何種類之晶片。在一具體實施例中,第一晶片集包 括覆晶或線路接合晶片或兩者,並且第二及任何隨後晶片 集匕括線路接合晶片。該等晶片之任一者亦可包括一半 體裝置。 依據本發明藉由晶粒堆疊晶片形成的電子封裝在囊封及 9 分割之後將具有特定高度。為減小電子封裝之高度,晶片 ,區域可凹人以減小獲得的封裝之高度。,引線框上的 " a 曰曰#塾可採用降低的㈣來形成以使晶片可適合於此區域 r 内並從而提供具有降低高度的晶片。 依據揭示方法形成的電子封裝係堅固及穩定的。為在應 力條件及製造期間提供封裝之進一步的可靠性,可將變更 、a加囊封物之保持力。變更可沿晶片墊之周邊、引線 或兩者而定位。 底部引線框之選擇性預電鍍可用以界定引線框之底部特 126204.doc * 17- 1337775 徵。此選擇性預電鍍可在引線框之頂部及底部表面兩者上 提供類似圖樣。可使用任何方便材料來完成選擇性預電 鍵。在一具體實施例中’將NiPdAu或銀合金用以預電銀引 線框。 在囊封之後,晶粒堆疊晶片將藉由一實心囊封物所包圍 以預防晶片與引線框之間的電連接移動或弱化。可藉由囊 封物來覆蓋整個堆疊晶片集。或者,最高晶片之一部分 (例如背面或頂部表面)可在囊封之後保持曝露。例如,最 高晶片之表面可透過囊封物而曝露並且晶片之其餘部分嵌 入在囊封物中。採用此方式,可減少囊封物之數量而不引 人/主目地影響最終封裝之穩定性。此外,#最高晶片之頂 部或背表面包含識別資訊,料形成封裝讀此資訊並非 藉由囊封物所覆蓋且可輕易地藉由使用者所觀察。 :先前所陳述,晶片及晶粒堆疊晶片係電附著於引線框 以提供電源至晶片。除諸如覆晶或線路接合晶片之晶片以 外:其他元件亦可與引線框連接。此等額外元件可以係結 構7^件^其為封裝提供增加支律或穩定性。額外it件亦可 系:7L件,其支撐晶片或晶片封裝之功能。此類額外元 件之祀例係無源組件、隔㈣、電源環、接地環及選路。 中的此等及其他結構或w件之任何組態係在本 發明之範疇内。 爲曰=物材料可以係任何種類的物質,其可應用於晶粒堆 ::物:且會凝固以形成耐久固體。在-具體實施例令, 體樹脂,其包圍晶片並硬化以產生晶片。 126204.doc •18· ^37775 囊封物之一範例係環氧樹脂。該囊封物通常係非導電物質 以預防囊封之材料内的電信號從一個晶片跨越至另一個晶 片0 當額外元件包括電元件時’此等元件可與引線框直接或 間接電連接。此等額外元件亦可與封裝中的—或多個晶片 電連接,並且此類具體實施例將取決於所形成的特定晶片 級封裝。
可使用該技術中已知的生產技術來形成引線框。例如, 可使用化學㈣、衝壓或壓印技術來形成引線框。 可採用材料(例如導電材料)之膜塗布或部份塗布引線 框1沒有此類膜之引線框相比,該膜可以提供引線框與 寸著於引線框的晶片之間的增加電輸出。在一具體實施例 中:從銅或銅合金形成該膜。該膜之厚度—般並不重要, 儘管該膜將必須足夠厚以具有機械穩^性。在—且 例中,該膜之厚度係大於或等於約。,。5麵。
本毛月之另-態樣提供包括-晶片墊區域及引線的引線 2引線框具有變更,其提供覆蓋引線框的囊封物材料之 增加保持力。晶片將通常係附著於晶片墊區域且與引線電 σ、丄、纟°構设計及組態用以為囊封物之保持力提供增 =面區域。變更可採取提供囊封物之增加保持力的心 線框或引绫扩 夂更了乂抓用工腔、低降或定位在?丨 上面报/王之—部分上的切口之形狀。變更亦可出現在 >成至晶片之電連接的引線上。 126204.doc 19 1337775 變更可以在引線框之任何部分上。例如,變更可以在晶 片墊區域之周邊或引線或兩者上。變更亦可以採用晶片塾 區域之周邊、引線或兩者之粗糙化的形式。 除提供用於囊封物之改良式保持力的變更以夕卜可粗糙 化引線框之表面以提供增加表面區域。粗縫化表面將促進 囊封物與引線框之表面的黏著。 可視需要地使用一夾子代替線路接合以増加至晶片的電 源流並從而改良晶片之性能。 在本發明之另—具體實施例中形成具有超聲波接合線 路的電子封裝之方法。形成部份姓刻之引線框之-區塊’ 其中包括網式部分且藉由街道形部分加以彼此分離的引線 框具有連續的底部表面。將晶片附著於引線框上的晶片接 收區域。在每一個晶片之端子與對應引線框之電引線部分 之間:成電連接。線路係與引線框之底部表面超聲波接 糟由在引線框(包含分離引線框之街道形部分)上應用 囊封物材料而囊封引線框。接著執行底部表面之背面圖樣 除網式部分以及街道形部分。接著在街道形部分上 _以形成個別晶片級封裝,其在底部表面 上"、有超耷波接合線路。 方=之一具體實施例提供形成晶片級封裝之方法。該 方法包括形成部份蝕刻 括網式部分、一曰片1「…之一區塊,該等引線框包 道形部分。將二:域、複數個電引線部分以及街 二=一積體電路晶片附著於該膜之第 —域。接著在晶片上的—或多個端子 126204.doc -20- 2個電引線部分之間形成電連接。接著藉由將囊封物材 用於引線框及街道形部分上來囊封引線框。接著背面 ,刻引線框之底部表面以移除網式部分、衔道形部分以及 曰曰片文裝區域’從而移除積體電路晶片底下的引線框之所 有或實質部分。接著分割佈置在引線框之街道形部分上的 囊:物材料以形成個別晶片級封裝。任何類型的任何數目 之晶片均可附於部份圖樣化引線框。 可採用預電鍍材料選擇性地預電鍍引線框,或可在囊封 之月|j採用其頂部側、底部側或兩者上的遮罩材料遮罩引線 樞。 可使用任何方便或傳統物質選擇性地預電鍍引線框。此 類物質之範例包含衝擊型Ni/Pd/Au、沈浸Ag、Sn/Pb、無 釔焊料、沈浸錫無電鍍鎳、銀(Ag)以及衝擊型Au(金P 亦可使用任何方便或傳統遮罩物質(例如可印刷油墨、 模板油墨'環氧油墨)或有機物質來選擇性地遮罩引線 框。 可在任何適當時間(例如在背面圖樣化之後)從引線框之 底部移除預電鑛材料或遮罩材料。 可由該技術中已知的任何適當物質來形成引線框。例 如弓丨線框可包括銅或銅合之臈金或另一金屬或金屬合 金0 如先前所陳述,將一積體電路晶片附著於引線框之晶片 安裝區域。可使用該技術中已知的一黏著劑或其他觸覺或 固定物質來附著該晶片。例如,該黏著劑可以係樹脂、環 126204.doc 21 氡樹脂、焊料膏或膠帶。 可使用傳統程序(例如藉由化學触刻、衝壓或壓印)來形 成引線框。 晶片可使用適當電連接構件(例如藉由線路接合)與引線 樞電連接。 在另一具體實施例中,本發明方法允許在晶片安裝區域 上晶粒堆疊多個晶片。例如,該方法可包含晶粒堆疊一或 夕個第二晶片至附於引線框的積體電路晶片之頂部上。此 等第二晶片可與引線框或附於引線框之積體電路晶片或兩 者電連接。可使用此類連接方法的組合。第二晶片亦可彼 此電連接。 本發明之另一態樣提供用以製造電子封裝的部份圖樣化 之引線框。 部份圖樣化之引線框可由—具有一頂部表面及一底部表 面之膜組成。該膜可具有一頂部表面,其具有(a)從該頂部 表面但並非完全透過該膜至該底部表面之部份圖樣化之— 第一區’以及(b)未從該頂部表面部份圖樣化之一第二區。 δ亥第二區可以形成一用以支撐一積體電路(1C)晶片的晶片 墊區域,以及用以提供與該IC晶片之電連接的複數個電引 線。έ亥晶片墊區域及複數個電引線可經由該第一區進行連 接’但並非透過該頂部表面進行連接。該膜之底部表面亦 可從該底部表面但並非完全透過該膜至該頂部表面而加以 部份圖樣化。 可採用任何特定方式來圖樣化引線框之頂部及底部表 126204.doc 面。例如,可力方、士门w 任互補圖樣中圖樣化頂部及底部表面,以便 兩個表面在引始4 < Ή線框之兩側上具有實質上相同的特徵。 此可2用影線、通道或兩者來圖樣化引線框之底部表面。 類〜線或通道有利地允許側通風口及側通風,因此在回 焊期間不存在捕獲空氣。 I月之另一態樣的另一具體實施例提供用以形成晶片 紹L圭4癸'夕卞' 、、各_ ^ i / 忒方法包括提供一部份圖樣化之引線框, :、具有⑷從底部表面但並非完全透過該引線框至底部表面 ^份圖樣化之—第—區’以及(b)未從頂部表面部份圖樣化 7 —第一區。該第二區形成(a)-用以支撐-積體電路(1C) 曰曰片的s曰片墊區域,以及(b)用以提供與該1C晶片之電連接 的複數個電引線。該晶片墊區域及複數個電引線可經由該 第—區進行連接,但並非透過該頂部表面進行連接。 接著將一積體電路晶片附著於引線框之第—區的晶片墊 區域。接著在晶片上之一$多個端子與引線框上之一或多 個電引線部分之間形成電連接。接著藉由將囊封物材料應 用於引線框及街道形部分上來囊㈣線框。接著對引線框 之底部表面進行背面圖樣化’以移除網式部分以及街道形 部分。亦移除晶片墊區域之底部表面之一小部分,以形成 透過晶片《域之-或多個通道。此等通道有利地允許側 通風口及側通風,因此在回焊期間不存在捕獲空氣。接著 为割佈置在引線框之街道形部分上的囊封物材料,以形成 個別晶片級封裝,其係準備隨後使用。 晶片墊區域之通道橫跨整個晶片墊區域之長度而延伸, 126204.doc -23· 二二可;U跨晶片塾區域之—部分而延伸。此等通道可以採 用影線或其他類似結構之形式g 七月之另一態樣提供用以製造電子封裝的部份圖樣化 引線框。引線框包括具有—頂部表面及一底部表面之一 骐。該膜係從該頂部表面但並非完全透過該膜至該底部表 上而邛伤圖樣化。該膜亦係從該底部表面但並非完全透過 ㈣至該頂部表面而部份圖樣化。該頂部表面上的圖樣化 係比及底部表面上的圖樣化深。所獲得的引線枢之圖樣化 在其頂部上比在其底部上深。雙側蝕刻允許最終加以移除 的引線框之部分具有減小的厚度並從而使獲得的電子封裝 之處理及製造流線化。 本發明Μ —態樣提供具有Μ通道之一底冑表面的一 晶片級封裝。肖晶片級封裝包括一或多個囊填充的電腦晶 片,並且該等通道作為通氣口以減小或消除回焊期間的捕 獲空氣。 【實施方式】 現在參考圖式說明本發明,其中相同數字指相同元件。 圖4至J5b及圖】6至24b顯示形成具有可與接近晶片級封裝 (CSP)之引線計數相比的引線計數之部份圖樣化引線框封 裝的不同具體實施例。本發明之方法改良製造線的自動化 以及從其來製造封裝之品質及可靠性。此係藉由下列方式 而完成:執行製程步驟的主要部分’其中將部份圖樣化之 金屬膜形成於一側上的網狀引線框中。與傳統衝穿模板狀 引線框相反,本發明中使用的引線框在一側上係部份圖樣 126204.doc -24- 1337775 化的而在另—側上係實心及 方式加以改良,並且才” $。此-構鞛由機械及熱 ^ 、’且在日日片附著、線路接合以及囊封浐床 期間執行無扭曲或變 £ 標記以描-將二二 可加以遮罩或另外加以 枯,.曰將最終错由背面蝕刻加以移除之 片附著及線路接合程序步驟並附加晶片及線路接合 =囊封在模製材料中之後,在未藉由底部表面之選擇;生 預電鍍所遮罩的區域中透過該膜而部份㈣底部表面’以
:引線接點與晶片墊隔離且彼此隔離。隨後,分割獲得的 曩封之封裝而不必將其切成任何額外金屬。 更明確而言,圖4至15b顯示用於線路接合晶片的部份圖 樣化之引線框的形成以及使用其用以形成ELp型電子封裝 的方去。方面,圖16至22顯示用於覆晶的部份圖樣化 之引線框的形成以及使用其用以形成ELpF型電子封裝的 方法。亦結合圖24a及24b說明使用瞬時的部份圖樣化之引 線框形成ELGA型電子封裝的方法。
圖4係一膜(較佳為金屬薄片,且較佳為銅)之斷面圖, 該膜係不僅形成於引線框巾,而且亦在確保形成引線框的 程序步驟期間作為穩定載體。金屬帶之厚度係等於或大於 約〇.〇5 mm。在另一具體實施例中,該厚度的範圍可以係 在約0.05至0.5 mm之間。 形成一引線框通常包含切穿金屬帶,像切割一模板一 樣’並接著採用極細小指狀引線進行操作。為將此類精緻 結構固持在適當位置,可使用真空夾頭。然而,傳統真空 失頭通吊並非調適用以為此類精緻裝置提供吸力而且必須 I26204.doc • 25- 1337775 通吊在周邊上對引線框施加壓 引線框改裝用於此目的之任何 改裝步驟。因為部份圖樣化之 連續的’所以傳統真空夾頭可
框固持在適當位置。此外’可以在引線框的製造中普遍使 用適應各種工業用引線框之一種大小的金屬帶。可以採用 ''人力以幵v成之引線框上的甚小應力及應變來完成晶片附著 及線路接合之隨後程序步驟。可以輕易製造具有甚細小幾 何形狀的引線框,因為藉由網狀結構將引線固持在一起並 且該等引線框係至直最終步驟才彼此分離。
力。必須從各類型及大小的 索具。然而,本發明減輕此 引線框的底部表面為實心且 以在處理期間輕易地將引線 可以採用若干方式完成在引線框上形成各種圖樣。一種 方法可以係將圖樣衝壓/壓印至金屬中。其他方法可包含 化學或電化學研磨及放電加工(EDM)。另一方面,較佳使 用光微影圖樣化,其係半導體製造的主要方式。在本發明 中’在光微影圖樣化之前於前(或頂部)側及背(或底部)側 上預電鍍圖4所示的金屬帶(100)。可採用分別致能接合及 可焊性的材料來預電鍍前表面及背表面之任一者或兩者。 在一具體實施例中’採用可接合材料(例如衝擊型Ni/pd/Au 或Ag)來預電鍍前表面。在另一具體實施例中,採用可焊 材料(例如Sn/Pb、無鉛焊料、沈浸錫無電鍍鎳或衝擊型 Au)來預電鍍背表面。在另一具體實施例中,採用與頂部 側相同的材料預電鍍背表面,該材料因此可在背面圖樣化 期間作為光阻。此光阻狀電鍍可以後來在最終完成之前加 以剝離。在需要的情況下,可以在後來步驟中執行預電 126204.doc -26- 鍍。 在下 V驟中,光微影圖樣化預電鍍之前側(丨1以 成對應於包圍B U奴「山 a 圍日曰片墊區域的晶片墊(115)及電接點(in)之 區域。-電接點⑴3)的特徵可以為—引線之端部分,其係 透心成網狀結構的中間凹人部分之第—區與晶片塾區域 115)連接。當從背面姓刻金屬膜(100)時,在-後來時間 示此等中間凹入網狀部分,以便端部分及晶片墊部分將 t此隔離°包括晶片_15)及周圍接點⑴3)的區域係有 時稱為晶片地點。可以在以鍵輪方式與一捲轴連接的連續 銅4片觀上形成複數個晶片地點以輕易地使包括一或多個 晶片地點的引線框之形成自動化。圖5說明兩個晶片地 ’其將形成於兩個對應引線框中,該等引線框依次為將 從其形成的兩個封裝之部分。 針對圖5所說明的兩個晶片地點加以顯示的圖樣係接著 藉由敍刻轉移至膜帶(〗00)。如圖6所示,本發明之一主要 特徵係僅部份透過金屬之厚度執行触刻,其在本文中稱為 部份圖樣化。在膜之—笛 -.^, 第一 £中執行部份圖樣化以形成一 網式結構(130),其遠蛀t 3Ι , '運接母一個引線框之引線接點(113)的 晶片塾(115)。該第—F介—如时 &亦在泫膜之衔道形部分(136)中將 引線框彼此連接。 如圖6a至6c所示,可力 了在一區塊/視窗膜(138)中形成一矩 陣或此類引線框(例如,16 X 16)。圖6b及6c顯示該第一區 包含網式結構(139),复遠桩息伽2| &上 /、運接母一個引線框之晶片墊及引線 接點。S玄第一區亦在該膜 、之衝道形。P ’刀(1 36)中將複數個引 I26204.doc •27· 1337775 線框彼此連接。 2二二具體實施例中’部份圖樣化可以從該膜之厚度的 發生變化。然而,部份圖樣化可事實上為該膜 厚度的百分比’並且可藉由考量影響可製造性參數的各 因素來決定部份圖樣化之數量’該等參數包含撓性、剛 二熱厚度(或導熱率)。可以根據給定晶片大小以及線 路接δ或其他連接媒體(其可用於一給定封裝中或下一位 準封裝中的封裝之間的位準間或位準内連接)所需的小型 ^之程度來決定引線接點區域⑴3)及晶片塾區域⑴5)的 k向尺寸。尤其應注意,由於指狀引線之網狀結構,對引 線框之細小特徵及尺寸穩定性的製造性關注現在不那麼重 要。 如圖7所示,接著使用任何方便構件(例如環氧⑽))將 阳片(刚)附者於晶片墊區域。依據本發明,顯示附著的晶 片與晶片塾之間的接合處包括環氧或輝料。可採用導電^ 子填充環氧(150)以增強晶片之冷卻。在替代例中,代替環 氧⑽)的焊料膏⑽)亦可^提供晶片與晶片墊之間的 較堅固接合’以及至周圍環境的更有效冷卻路徑。環氧得 以固化’且如圖8所示。Λ θ y 4 在日曰片附者之後,使用熟知的線 路接合技術將線路(16〇)與端子(145)及對應引線接點⑴3) 接合’如圖8所示。因為依據本發明形成的引線框具有(例 如m由真空夾頭(未顯示)而牢固地座落並固持在扁平表面 上的實心、連續背側’所以引線之網狀結構並不在線路接 合期間顏動或跳動。此產生優良的接合,其改良最終產品 I26204.doc -28· 1337775 之可靠性。即使背側為實心及連續 貝幻具仍可具有關於何 處將出現背面蝕刻的指示器。例^ ^ ^ ^ ^ ^ ^ ^ 一 1 ^ 渌側可具有破裂或其 他指示器’其可以係該膜之表面’或者背側可採用預電鍍 材料(120)加以遮罩以描繪將加以背面姓刻的預期區。例 如’預電鍍材料(120)可加以遮罩在區域⑴3)下面以指示 引線框之對應部分將在後來則期間保留並且將移除區域 (130)及(136)下面的區域。
在圖9中’在連接晶片及對應接點之後,接著(例如)藉 由樹脂在模製材料巾密封囊封金屬膜之前側上的所有組 件。在該膜及所有曝露表面上形成囊封物(17〇),該等表面 包含引線框及其相關聯的線路(16〇) '晶片〇4〇)及接點 (Π3)與網式結構(13〇)及街道形部分(136)。當提起獲得的 模製封裝時,乾淨的背側現在可用於進一步處理。採用此 揭示方法,可消除至封裝之下側上的覆蓋區之模製閃光之
共同遇到的問題可先前採用將促進隨後處理或蝕刻之物 質來電鍍乾淨的背側。 如圖10所示,引線接點(U3)及晶片墊(115)現在可以輕 易地彼此隔離以藉由透過封裝之背側蝕刻第一區之網式結 構(1 3 5)來开> 成其自己的島狀物。在此情況下,亦背面姓刻 街道形部分(136)。使用諸如可印刷油墨或有機油墨材料之 物質的預電鍍(120)可用作遮罩或光阻以形成所需底部特徵 (123 ' 125)。在其他具體實施例中,可使用有機材料代替 金屬或可焊材料作為蝕刻遮罩。有機材料可在背面蝕刻之 前於任何方便步驟中加以印刷或應用於引線框上。 126204.doc •29· 1337775 背面蝕刻會繼續,直至達 屬的蝕刻方沐飞 彳、氬材料。用於背面蝕刻金 的蚀刻時^可以不同於用於前側的'刻方法。用於背側 側執行2 同於用於前側的㈣日㈣,取決於從前 形成可進:份蝕刻之程度。因此’部份蝕刻引線框的初始 订疋製以適合對最終封裝之自動化、品質、可靠 性及功能的製造要求。作為 Π2 先阻之底部上的預電鍍 ()了加以剝離以曝露金屬帶(1〇〇)。
為保濩金屬且易於安裝至印刷電路板,可將可烊材料 =無電_^、沈浸^、沈浸Sn或其他此類材 鍍至金屬帶(1〇G卜任何預電鍵可保留或加以剝離 卓’此係視為適合於特定情況。
作為最終步驟,分割引線框之間之街道形部分(136)上 的:封物(170)以形成兩個個別封裝,如圖u所示。此係採 用右干方式元成,該等方式包含銘切、嘴水切割、雷射切 或其組合’或尤其適合於切割塑膠的其他技術。換言 之,不存在其他金屬需切穿且因此不存在分層以及與切割 組合的歸及金屬相關聯的其他問題。將此與傳統封裝比 較,在傳統封裝中必須在分割封裝的同時切割街道形之間 的橋接金屬。許多次當同時切割金屬及塑膠時,金屬晶片 之某些可能使線及接點短路’從而引起鋸條上不合需要及 不可預測的磨損β如圖6a所示,亦可將此方法用以從引線 框之矩陣產生大量封裝。 圖12 a顯示透過分割的E L p之囊封物所俯視的俯視斷面 圖。圖1 2b顯示晶片與接點之一之間的封裝之—轉角的放 126204.doc •30· 1337775 大圖’該等接點包括最初金屬帶(丨〇〇)之一部分、進行預電 鍍以形成可接合層(π 3)之一頂部表面、以及進行預電鍍以 形成可焊層(123)之一底部表面。在圖12b中,"唇狀物,'係 顯示在晶片之接點及轉角上。接點(i i 3)及晶片(140)係顯 示為在其自己的島狀物上彼此隔離,但僅透過已進行線路 接合的線路(160)而彼此連接。
在未加以剝離的情況下,於封裝之下侧上的可焊預電鍵 表面(120)現在可用於若干目的。首先,至晶片墊(14〇)之 责面(125)的直接外部存取提供用於冷卻之額外路徑。其 次,接近晶片大小封裝(csp)之覆蓋區内的接點(123)使下 列成為可能··在下一位準封裝中安裝緊密隔開的封裝,並 因此增加同一區域的性能。 本發明之另一態樣提供用以減少模製材料與其應附著的 表面之間的分層之可能性的構件。此係藉由下列方式完
成:半蝕刻晶片墊及接觸區域周圍的邊緣以形成一搭接物 或"唇狀物”,例如藉由圖12b中的數字(1〇5)所參考。亦可 形成圖12c所示的不規則形狀空腔(1〇7)以增強與模製材料 接觸的表面之聯鎖機制。圖13a至13f亦顯示各種其他空腔 之^大圓,並且此等表面増強之形成可以_易地加以併入 自前側的部份蝕刻中。此對於從背側進行蝕刻而言沒有必 要,因為模製材料僅囊封從前側加以部份形成的表面"。 圖Μ將本發明之方法概述為以從前側部份餘刻引線框 ()金屬帶中開始,並以採用形成所需晶片塾及周圍 接點之方式背面圖樣蝕刻(25〇)同一金屬帶結束。晶片附著 I26204.doc 1337775 (210)、環氧固化(22〇)、線路接合(23〇)及囊封(24〇)的中間 步驟係全部在機械及熱穩定引線框上完成’因為引線仍透 過金屬膜中的部份蝕刻之網狀或網式結構上的中間凹入部 分之第一區而連接。亦必須注意,僅在已將封裝之所有組 件固定在囊封物中之後才透過背面圖樣蝕刻(25〇)來移除中 間凹入部分之第一區,而且使周邊接點及晶片墊彼此分離 以進行適當隔離。在最終步驟之前,可以執行剝離預電鍍 〇2〇)以及應用可焊材料。因& ’不需要在分割(260)期間 將任何金屬切割成單一接近晶片大小封裝。 本發明之方法可用以形成各種封裝,例如用於電子封裝 的引線框之一陣列類型。陣列類型封裝(4〇〇)之俯視圖係在 圖1 5b中顯示為鄰近於圖i 5a所示的標準周邊型封裝㈠⑽)。 雖然數字(305)參考晶片端子之一周邊配置,但是數字 (4〇5)參考可經組熊而忐亩别赤办姐4 α^
準。數字(460)指ELP之仰視圖上的陣列類 型輸入/輸出組態。
電子封裝'製造成適應覆晶 一具體實施例揭示形成部份圖樣化 方法’其係尤其適合於大量產生 覆晶的引線框將在以下稱為FCL以 126204.doc •32· 1337775 將其與傳統引線框區分。此係因為,不像傳統引線框一 樣,FCL係較堅固且更適應於自動化製造線,如以下 明。 與傳統通用衝穿型模板狀引線框形成對比,fcl亦為網 狀結構。網狀FCL之前側#有凹人區段(包含部份圖樣化之 弓⑷,@背側係實心及扁平的。此提供機械剛性以在製 程期間執行而無扭曲或變形。在完成晶片附著及封裝密封 之後,蝕刻背侧以將引線接點彼此隔離。可以藉由無電鍍 或沈浸程序纟完成移除預電鍵或採用纟他可焊材料進行重 新電鍍。隨後,分割獲得的囊封之封裝而不必將其切成任 何額外金屬。因此,應明白可以輕易地製造具有甚細小幾 何形狀(例如具有VFQFP_N封裝)的FCL,因為引線係藉由 、周狀或網式結構保持在一起而且直至最終步驟分割才完全 彼此分離。 像已經揭示的第一具體實施例之部份圖樣化之引線框一 樣,第二具體實施例之FCL係亦從金屬薄片(較佳為如圖4 所示的銅膜)形成,其中預電鍍前表面及背表面,或如先 前所陳述,可以將電鍍延緩至一後來步驟。(應注意因 為用於兩項具體實施例的程序步驟係類似的,所以參考數 字已適當保持為相同,表示具有撇號的第二具體實施例之 參考數字除外。同一參考數字(100)已針對用於兩項具體實 施例的金屬膜而保持為一致)。因此,預電鍍前側(丨丨0,)係 光微影圖樣化以形成晶片接收區域(1 1 5,)、包圍晶片接收 區域的引線部分(1 13,)、以及其他中間區域(1 17,)。在以下 126204.doc •33· 1337775 揭示的一隨後程序步驟中,引線之一個端部分係與之 端子連接,而另一端部分將與下一位準封裝連接。包括 晶片接收區域及周圍引線的區域係有時稱為晶片地點,類 似於具有線路接合晶片之晶片地點。可以在以鏈輪方式與 一捲軸連接的連續銅薄片輥上形成包括複數個晶片地點的 複數個引線框以輕易地使包括一或多個晶片地點的引線框 之形成自動化。圖16說明兩個晶片地點,其將形成於兩個 對應引線框中’該等引線框依次為將從其形成的兩個封裝 之部分。 < 針對圖16所說明之兩個晶片地點加以顯示的圖樣接著透 過蝕刻,藉由部份圖樣化而轉移至金屬犋(1〇〇卜圖I?所示 之部份圖樣化可最多為金屬帶之厚度的一半、四分之—’ 或者因該事件的任何比率’並且可以藉由考量影響包含挽 性、剛性及熱厚度(或導熱率)之製造性參數的各種因素來 決定部份蝕刻的數量。可以根據包含晶片大小的給定晶片 地點以及引線(其可用於一給定封裝中或下一位準封裝中 的封裝之間的位準間或位準内連接)所需之小型化的程度 來決定引線接點區域(U3,)及晶片區域(115,)的橫向尺寸。 尤其應注意,由於指狀引線之網式結構,㈣線框之細小 特徵及尺寸穩定性的製造性關注現在不那麼重要。 接著翻轉覆晶(FC)(l 30,)使得晶片之前侧上的端子(1 35,) 位於如圖18所#之引線之一個端部分上。在一後來步驟 中,引線之相對端將形成於電接點中,以與下一位準封裝 (例如卡或板)連接 '然而,首先,透過如該技術中實施: 126204.doc •34· 1337775 晶片接合爐,發送圖18所示之網狀引線框結構上組裝的晶 片。對焊球進行回焊以便回焊受BLM的限制,從而形成焊 料柱。因為依據本發明形成的引線框具有牢固座落並固持 在扁平表面上的實心、連續背侧,所以引線之網狀結構並 不在晶片接合爐周圍顫動或跳動,從而產生優良的晶片接 合。因此’揭示之方法改良最終產品之可靠性,即 VFQFP-N型封裝之可靠性。 在晶片接合之後,晶片連同最初金屬膜之前側上的部份 圖樣化之引線接著(例如)藉由樹脂密封囊封於模製材料 中,如圖19所示。囊封物(14〇,)係形成於包含引線(ιΐ3)之 表面的所有曝露表面周圍、焊球(135,)周圍、晶片下面、 沿凹入晶片接收區域(115,)之垂直壁以及凹入區域(117,)之 垂直壁,牢固地固持至扁平表面上之金屬帶(100)的未蝕 刻、實心及扁平背侧除外。當提起獲得的模製封裝時,乾 淨的背側現在可用於進一步處理。在此具體實施例中亦消 除至封裝之下側上之覆蓋區之模製閃光之共同遇到的問 題。 引線(1 1 3 )現在可輕易地藉由下列方式彼此隔離:在程 序開始時,透過與從前側部份地蝕刻之圖樣對準之封裝的 背側進行圖樣化。t面触刻會繼續,直至達到模製材料。 此係顯示在圖20中,其中移除引線框之網狀部分(即區域 (Π1’)及(1191)),以使晶片區域(1151)彼此斷開,並使引線 (Π3·)彼此斷開。用於背面圖樣化金屬的蝕刻方法可以或 可以不與用於從前側進行部份蝕刻之方法相同。此外,用 126204.doc -35· 於背側的敍刻時間可以不同於用於前側的敍刻時間,取決 於從前側執行之部份㈣的程度。m純刻引線框 的初始形成可定製以適合對最終封裝之自動化、品質、可 靠性及功能的製造要求。作為化學光阻之底部上的預電鍍 (120)可加以剝離以曝露金屬帶(ι〇〇)。為保護材料且便於 P刷電路板,可將可焊材料(例如無電錄N"沈浸 AU '尤叹八8、沈浸Sn或其他材料)電鍍至金屬帶(ι〇0)β 作為最終步驟,具有用於說明本發明之目的之兩個囊封 :曰曰片地點的圖2〇之封裝係接著分割成單—接近晶片大小封 裝(CSP),其比VFQFP__封裝多,如圖21所示。分割式 部份圖樣化之引線框之俯視圖係顯示在圖22a中,其中引 線(113,)係顯示彼此隔離且與晶片〇3〇,)之下側上的焊球 (1 3 5 )連接。圖22b顯示晶片與提供在卡或板(丨5〇,)上之外 部接點(145«)連接的引線之—之間的封裝之轉角的放大 圖。預電鍍表面(120,)係已經製備以與下一位準接點接 合,如同一圖所示。可保持或移除預電鍍或遮罩材料,此 視為此時的適δ或所需方式。亦可在該程序中適當針對個 別情況於其他時間移除預電鍍或遮罩材料。此外,引線 (113’)之下側(114·)係曝露於周圍環境因而提供增強冷 钟。在某些情況下’可將—塗層應用於下側⑴4)以減小板 安裝期間可能短路的機會’尤其對於細小節距應用而言。 與以剛揭示的技術相同之技術可用以預防囊封物與 之表面的分層’即,藉由併入網式引線框之凹入區域 (US’)及(117|)之垂直壁上的圖13a至i3f之不規則形狀空 126204.doc •36- 1337775 * μ &等表面增強之形成可以從前側輕易地併人部份餘刻 中。此對於從背側進行钱刻而言沒有必要,因為模製材料 ^ 僅囊封從前側加以部份形成的表面。 ‘ 圖23將本具體實施例之方法概述為以從前側部份圖樣化 * 弓丨線框_')於-金屬帶中開始,並以採用形成所需晶片 . 接收區域及周圍引線夕t 4··北 深之方式#面圖樣化(24〇,)同一金屬帶 ,。束FC放置(210 )、FC晶片接合(22〇》以及囊封(23〇,)之 巾間步驟係全部在機械及_定咖中完成,因為仍透過 金屬膜中的部份钱刻網狀結構連接引線。亦必須注意,僅 在已將封裝之所有粗件固定在囊封物中之後才透過背面圖 樣姓刻(240,)來選擇性地移除引線之網狀部分,而且使引 線彼此分離以進行適當M m »ι _ _ T遇田&離。因此,不需要在分割(250,) 期間將任何金屬切割成單一接近晶片大小封裝。 本發明之方法可用以形成各種封裝,例如部份圖樣化之 引線框之一陣列類型,其中焊料凸塊之一區域陣列可同時 * 與上面使晶片翻轉的引線框進行晶片接合,類似於本文中 揭不的具有周邊焊料凸塊集之方法。此外,可同時形成部 , 份圖樣化之引線框本身之一陣列,而且接著亦同時接合 * FC,然後將該陣列分割成多個分離VFQFp_N型封裝。此 外,每一個獲得的CSP因此可在用於接合至下—位準封裝 的陣列類狀封裝Τ δ具有焊料凸塊、塾或其他電連接^ 形成具有平台柵格陣列之蝕刻引線框封裝,或圖2钝及2仆 所示的ELGA型封裝。圖2乜中顯示一斷面圖,其中在引線 U45’)上形成晶片墊(135,)。在背面圖樣化之後,引線 126204.doc •37· 1337775 (14 5')係彼此電隔離以與下一位準封裝接合。可透過沈浸 錫浸漬或無電鍍鎳電鍍採用任何數目的可焊材料閃光完成 (145·)之曝露的底部表面。ELGA封裝之底部表面(111,)係 顯示在圖24b中,其中將一陣列圖樣用於電連接(丨451)。
焊料凸塊可採用金屬柱凸塊(例如銅柱凸塊)的形式,其 中每一個凸塊均係由具有約75微米高度的Cu軸組成,該轴 具有焊料(或無Pb)蓋以產生約1〇〇微米的總高度。當使用 Cu柱凸塊時,•,焊料凸塊"將為,•焊料蓋"。使用“柱係提供 晶片表面UBM與板接點之間大於5〇微米的凸出物’並且使 塑膠囊封物能自由地流動而且覆蓋覆晶下面的裂縫。
因為形成ELP、ELPF或ELGA封裝之任一者的部份蝕刻 方法在各種製造步驟期間提供強固性,所以其他形式的電 子封裝亦可行。-種此類形式包括本發明之引線框封裝之 線路接合至下-位準封裝。超聲波接合技術由於引線本身 的脆弱而無法用於傳統引線框,除非將其附著於實心基底 以提供穩^性及強度。#比之下,部份㈣之引線框由於 其網式結構而係穩定的。部份圖樣化之引線框的未蝕刻及 預電鍵底部表面(12〇,)提供實心接合區域或柱狀物,以有 效地將超聲波能量應用於接合在ELP或ELPF之區塊或帶上 的紹線路楔形物。依據本發明之另—態樣,因此銘線路 (m)係以超聲波方式附著於部純刻之引線框之—區塊或 帶的底部表面,如匕 如圖25a所示。線路直徑範圍係在約〇 〇〇】 英吋至0.020英吋夕η ml _ ΐ之間’後者直徑代表帶狀物而非線路。 接著對帶進行囊封、接工m μ ^ 考面圖樣化及分割以形成個別接近 I26204.doc -38- 1337775 CSP。需要超聲波接合,目為其避免曝露於藉由球格柵類 型封裝所經歷的球接合溫度,並因此獲得改良式可靠性。 亦可應用鋼線路球接合方式,如圖25b所示。應瞭解圖Ma 及25b所示的CSP可以為ELP及ELPF之任一者。 本發明在用於電子封裝的製程中提升若干額外優點。例 如,在背面蝕刻之後且在分割之前,在封裝係仍配置在封 扁之一區塊中的同時,該區塊將係内在地準備用於帶測 試。與將封裝處理為個別單元相&,此提供重要的優點。 在將封裝se*置在—區塊中的同時對其進行帶測試會改良測 試的可靠性。 本發明亦使製造商能生產具有雙或三列交錯引線的封 裝,該等引線可以使給定封裝的I/C)容量倍增。引線框之 扁平連續底部表面致能通用組裝設備,其不需要為每一應 用而改裝,並且對於自動化係完全撓性。例如,至 12x12個封裝區塊之間的處理不需要任何機械變化。此 外,本發明輕易地促進構造具有用於每一個腳的"凸出物" 之封裝(例如在腳之表面上的模製體之底部之間的2 mils)。當晶片封裝係欲與下一位準封裝(例如板)連接時, 凸出物提供額外優點。 圖26a及26b說明本發明之一態樣的一具體實施例,其中 將兩個晶片(5G5、5 1G)晶粒堆疊在—引線框(5⑼)之一晶片 墊(515)上。下晶片(505)(即附於晶片墊接收區域(515)的晶 片)係與晶片墊區域(5 15)周圍的電引線之内部集(52〇)電連 接。上晶片(510)(即附於下晶片(5〇5)之頂部的晶片)係與晶 126204.doc -39- 1337775
片塾區域(515)周圍的引線之最外面集(525)電連接。採用 保》蒦明片及線路免於知壞之一囊封物(53〇)來囊封晶片。儘 管圖心及攝中的晶片⑽、5 Π))係與本發明—致的線路 接5曰曰片i_是π玄等晶片之一或多個亦可以為覆晶。下晶 粒堆叠Ba片(505)在大小方面係大於上晶片(5iq)。儘管在 f些具體實施例之說明中下及上晶片並未彼此電連接但 疋此等曰曰片可(例如)藉由從一個晶片連接至另一個晶片的 線路而進行電連接。可||由將各種晶片之端子與從引線框 延伸的電引線之端部分連接來完成形成電連接之步驟。 圖27a至27c說明本發明之一具體實施例,其中晶片墊區 域(550)係凹入的以提供改良式晶粒堆疊以及封裝高度方面 的減小。在圖27a至27ct,三個晶片(555、56〇、565)係晶 粒堆疊以形成Ή封裝^圖27a可以看出,已移除晶 片墊區域(550)之内部,因此僅存在正方形外環。一晶片
(555)得以放人並附著於此晶片塾區域。儘管圖27a至27c顯 示與本發明-致的三個晶粒堆疊晶片(555、560、565),但 是可存在任何數目的晶粒堆叠晶片。纟圖27a中,凹入晶 ;片墊區域(550)之内部係顯示為引線框之頂部表面。即,: 該晶片墊區域之外正方形環(575)已加以沈積在引線框之頂 部上,而且該晶片墊區域(55〇)的整個内部並未加以沈積或 從引線框得以移除。在本發明之替代性具體實施例中將 一薄材料層沈積在該晶片塾區域之内部,或者移除晶片内 部區域之-部分。在此類具體實施例中,該晶片塾區域之 内部將高於引線框背面,但仍低於該晶片塾區域之外部 126204.doc •40· 1337775 分’從而為晶片之附著提供凹入晶片墊區域。 儘管在圖27a至27c中,最大晶片(555)係定位在晶粒堆疊 之底部上’而且最小晶片(565)係定位在頂部,但是可固定 晶片以便最大晶片係在頂部而且最小晶片係在底部。最高 曰曰片(565)係顯示為與中間晶片(56〇)以及引線框(57〇)上的 電引線(580、585)連接。中間晶片(56〇)係顯示為與最高晶 片(5 65)以及引線框上的電引線連接。覆蓋晶粒堆疊晶片 (555、560、565)的囊封物(590)預防晶片封裝之線路在處 理或安裝期間遭到損壞。使用一黏著劑(例如導電或非導 電環氧)或使用一絕緣材料將各種晶片附著於引線框(55〇) 或將其彼此附著。 圖28&及28b係具體化本發明之若干態樣的引線框之透視 圖。圖28a顯示在將晶片附著於引線框之前具有四個晶片 墊區域(605、610、615、620)的引線框(600)。圖28b在已 將晶片(625、630、635、640)附著於晶片墊區域(6〇5、 610、615、620)並將其與引線框電連接之後的同一引線枢 (600)〇 圖28a將引線框(600)顯示為具有用於線路接合晶片之三 個晶片墊區域(610、615、620)以及用於一覆晶之一個晶片 墊區域(605)。用於線路接合晶片的三個晶片墊區域之二個 (615、620)並非凹入的而其餘晶片墊區域(61〇)係凹入的。 此等晶片墊區域(610、615、620)包括晶片墊區域之外周長 上形狀為"τ”的鎖定區域之形式的變更(645)。此等鎖定特 徵為欲黏著的囊封物(650)提供額外表面區域,並且提供用 126204.doc -41 · 1337775 以保持囊封物而無囊封物之橫向移動的構件。
在圖28b中,並非凹入的晶片墊區域(615、62〇)分別支 撐經由至引線框的電引線所連接的單一晶片(635 ' 64〇)。 藉由—層電引線形成用於覆晶(625)的晶片墊區域(6〇5), 並且將覆晶(625)放置在此等引線之頂部上以形成電連接。 如線路接合晶片(63〇、635 ' 640)相比,覆晶(625)從而節 省引線框(600)上的空間。儘管為清楚起見僅單一晶片係顯 示為附著於引線框上的兩個非凹入晶片墊區域(615、 620),但是在本發明之其他具體實施例中,可在此類線路 接合晶片或覆晶上放置一或多個晶片。 在圖28b中,引線框上的凹入晶片墊區域(61〇)支撐複數 個晶粒堆疊線路接合晶片(統稱為63〇)。此等晶片係使用黏 ㈣(例如導電或非導電黏㈣,如環氧)或使用絕緣層附 著於晶片墊區域(610)。凹入晶片墊區域(61〇)之外周邊包 括形狀為"τ"的鎖定區域之形式的變更(645)。
圖28a及28b中的引線框(6〇〇)亦具有定位在覆晶晶片墊區 域(605)與凹入晶片墊區域(61〇)之間的電引線(一般為 655),其可用於除電腦晶片以外的其他元件。例如,此等 電引線可以係元件’例如半導體元件、無源組件、電阻器 及電容器或其他非晶片組件[一般顯示為(66〇)],其用以補 充晶片封裝中的晶片之功能。在圖28b中,電容器或電阻 器係附著於此等電引線。 可以將晶片逐一地晶粒堆疊至晶片墊區域上並接著將其 與引線框電連接,然後晶粒堆疊且電連接下一晶片。或 J26204.doc •42· 1337775 者,可晶粒堆疊所有晶片並接著可將整個晶粒堆疊晶片集 與引線框電連接。在另—具體實施例中,晶片可分離地從 晶片墊區域加以晶粒堆疊,並且整個晶粒堆疊晶片集可附 著於引線框而且與其電連接。 圖29a至29c顯示可應用於晶片墊區域的各種類型之變更 的具體實施例。在圖293中,變更(7〇5)在晶片墊區域(72〇) 之外部邊緣上採取,,τ"形狀切口之形式。在圖29b中,變更 (7 10)係以沿晶片墊區域(725)之外周長定位的空腔或穿孔 之形式。圖29c說明以沿晶片墊區域(73〇)之外周長的切口 之形式的變更(71 5)。此等變更提供增加強度及改良穩定性 給囊封晶片封裝。 儘管圖29a至29c中的變更或鎖定特徵(7〇5、71〇、715)係 定位在個別晶片墊區域(720、725、73〇)之周邊上,但是該 等變更亦可加以放置在晶片墊區域之其他部分上。例如’ 該等變更可以係在將並非藉由一晶片所覆蓋的晶片墊區域 之内部部分上並因此可採用一囊封物加以填充。 在圖29a至29c中,已將該等變更顯示為係定位在晶片墊 區域上。在本發明之額外具體實施例(例如圖3 〇 a至3 2 f中說 明的具體實施例)中,該等變更可加以定位在定位於引線 框上的電引線上’並且晶片可與其電連接。該等變更亦可 加以同時放置在晶片塾區域及引線上。 圖30a至31b顯示具有變更的電引線之若干具體實施例的 俯視及側視圖。圖30a至30d說明各種類型的引線(735、 740、745、750)以及此等引線之某些的斷面。圖3〇b顯示 126204.doc -43· 1337775 一變更可具有定位在引線(740)之内部表面(755)中的可接 合材料。圖3 la及3 lb顯示可粗糙化引線(760、765)之表面 (7 70、775)以獲得囊封物之改良式保持力。 圖32a至32f說明圖30a至3 lb之具體實施例的透視圖並例 證具有變更的電引線之若干具體實施例。圖^“說明具有 晶片墊區域(805)的引線框(800)。該圖之圓形部分(81〇)說 明具有變更的電引線(815)。圖32b至32f例證此等類型的弓丨 線。圖32b至32d顯示引線(820、825、830)之具體實施例’ 其一般係類似於圖30a、30c及30d中說明的具體實施例。 圖32e說明一引線(835),其一般係類似於圖3〇1)所示的引 線。圖32f說明一引線(840) ’其具有以沿該引線之周邊的 水平切口之形式的表面粗糙化,從而為該引線提供階梯式 外觀。化學或另一類型的程序可用以獲得圖32f所示的表 面粗糙化。可結合引線及晶片墊變更而應用此表面粗輪 化。 圖33a至33b說明本發明之另一具體實施例之一態樣的斷 面圖’其中使用一夾子(925)代替線路接合以提供電源給晶 片級封裝(935)並從而改良其電源能力◊圖33a說明使用線 路接合晶片(905及9 10)的此具體實施例,而且圖33b說明用 於覆晶(顯示為單一晶片907)的具體實施例。該夾子提供實 質上數量比線路接合大的電源並因此提供獲得的晶片封裝 (935)之改良式可靠性。該夾子亦協助從晶片散熱。當使用 該夾子時,最高晶片[例如圖33a中的(9 10)]將包含用以將 電信號發射至印刷電路板的引線。 126204.doc •44· 1337775 在圖33a中,線路接合晶片(905及9 10)係放置在晶片墊區 域(900)上並經由線路(920)與引線(915)電連接。複數個線 路(920)係用以將晶片(9 1〇)與複數列電引線(915)連接,儘 管電連接之數目及類型將取決於特定具體實施例。在圖 33b中,覆晶(907)係放置在從一引線框突出的電引線(例如 9 1 5)上。為便於說明起見,圖3 3 b中僅說明單一覆晶 (907) ’儘管在實務上可存在覆晶及形成晶片級封裝(935) 的線路接合晶片之任何組合。 最上面的晶片(907及9 10)之頂部表面係藉由夾子(925)與 引線框(900)上的一或多個電引線(917)電連接。在已將晶 片附著於引線框之後,將夾子(925)與晶片之頂部接合。任 何方便構件均可用以將夾子與晶片接合。在圖33a至33b中 說明的範例中,一導電膏或焊料(93〇)係用以將夾子(925) 附於晶片(907及910)。可從任何導電物質(例如金屬或金屬 合金)製造夾子(925)。適當的導電物質之範例包含銅及 銀。取決於特定具體實施例’個別炎子可附於特定晶片, 或整個導電帶或面板可使用成群方法附於複數個晶片。在 此後者具體實施例+,分割之動作切穿導電帶或面板以有 效地獲得個別晶片封裝。 堆疊晶片係隨後藉由一囊封物所覆蓋並在分割之後產生 依據本發明之晶片級封裝(935)。 曝露的晶粒墊係通常用以提供一晶片級封裝與一印刷電 路板(PCB)之間的熱及電分離。《而,在某些實例中,曝 露的晶粒塾或晶片塾區域對於一晶片或晶片級封裝之適當 126204.doc -45· 1337775 功犯有害。例如’某些印刷電路板設計具有晶片級封裝下 的有源電路,並且此等電路在封裝具有—曝露的晶片墊 月兄下可以會出現故障。儘管在此等情形下使用QFN(四 方扁平無引線)封裝可以呈現一可行解決方式’但是設計 成使用QFN封裝的引線框具有若干相關聯的組裝困難。例 如’難以或不可能使用現有技術產生用於無墊引線框之 QFN封褒,該等技術即’⑷採用膠帶,其中引線框係妓同 採用叫(模製陣列程序)格式,或⑻不採用膠帶,其中引 線框係採用矩陣格式。 為克服此等困難’使用者將⑷使引線框從底部得以半钱 刻以便該墊可在模製期間得以嵌入,或㈨使晶粒势顛倒。 然而,對於膠帶式卿引線框而言,存在執行線路接合的 問題,因為膠帶將預防加熱器區塊(用於在將半導體與引 線框線路接合之前對引線框進行預加熱)與該塾接觸:、線 路接合之後執行的膠帶方法對產量具有負面影響。對於矩 陣引線框而言,可採用底座設計加熱器區塊以在線路接合 T間支撐晶片墊區域。然而’此引線框設計具有較低容 置,並因此將影響每小時單位生產量並增加生產成本。 在此等情況下,無墊ELP可以提供改良式功能及減小的 故障機會。無塾ELP可維持高密度設計並提供更強固的也 裝程序。無塾ELP具體實施例具有一般與ELp晶片塾具體 實施例類似的結構’但底部上沒有姓刻保護。因此,無墊 ELP具體實施例並不需要對製造線進行重大變動。 無墊引線框具有無底部㈣遮罩或電鍵材料的半姓刻晶 126204.doc -46 - 粒接收區域。晶粒接收區域能夠封閉比其他引線框大的晶 粒大小,並可解決需要晶粒完全加以隔離的裝置。因為晶 粒接收區域係凹人的,所以獲得的日日日片級封裝將具有很低 的輪廓,&而最小化其安裝所需要的高度。晶粒附著材料 (或黏著劑)因此係非導電性的以預防電短路,並通常具有 杈製化合物相同的顏色以提供均勻外觀。此外晶粒附著 材料或黏著劑在背面蝕刻期間應該係穩定的以便預防損壞 2片級封裝。晶粒附著材料可以係該技術十已知的任何^ 貝例如可固化環氧樹脂或膠帶(例如聚醯亞胺膠帶)。 圖34a至34f說明一部份圖樣化之引線框之一具體實施 例,其中缺少一晶片墊區域或一晶片接收區域,並且將晶 片直接附於將形成引線框的蝕刻膜之底部。在晶粒附著、 囊封及背面圖樣化之後,使晶片之底部曝露在晶片級封裝 中。如圖34a所示,部份蝕刻之膜並沒有用以接收一半導 體晶片之隆起的晶片墊區域。 圖34a顯示已在前側上加以部份蝕刻的一金屬膜(1〇〇〇)。 可採用將促進後來處理(例如線路接合)的物質在一或兩侧 上預電鍍該膜(1000)。例如,可採用可線路接合物質(例如
NiPdAu或銀(Ag),如沈浸Ag)來預電鍍該膜之頂部,並且 該臈之底部可以係裸露的或採用相同或另_可線路接合物 質加以預電鍍。在其他具體實施例中,有機材料可用作蝕 刻遮罩。 忒膜(1000)係在其前表面上蝕刻以製備電引線部分 (1005),一積體電路晶片後來將附著於該等部分。該膜具 I26204.doc •47· 1337775 有分離引線框之部分的街道形區域(1035),而且透過此等 街道形區(1035)分割囊封之引線框以獲得個別晶片級封 裝。晶片安裝區域(1010)係钱刻至該膜之前表面中。此等 晶片安裝區域(10 10)的高度係比引線低。換言之,該膜 (1000)係在引線(1005)之區域中蝕刻最少並在引線框之其 他部分中ϋ刻最多。 在已製備並適當钱刻該膜(1000)之後,將一半導體咬積 體電路晶片(1020)附著於該膜’如圖34b中說明。該晶片 (1020)可使用任何方便物質、晶粒附著材料或黏著劑 (1 0 1 5)加以附著,其通常係非導電的以避免電信號之傳 播。 在一具體實施例中,該晶片(1 〇2〇)可以使用非導電環氧 (1 0 1 5)加以附著。該黏著劑可應用為流體或黏性液體,其 接著硬化或形成内部交聯以形成堅固、耐久接合。該黏著 劑或晶粒附著材料(101 5)將係可見的並曝露在獲得的晶片 級封裝(1040)之底部上且因此將需要具有長期熱及機械穩 定性。在其他具體實施例中,該黏著劑可以採用膠帶(例 如聚醯亞胺膠帶)的形式。膠帶通常由兩側上採用黏性物 質(例如熱塑性聚合物)加以塗布的基底膜組成,而且膠帶 可以係黏的或不黏的《在另外的具體實施例中,該黏著劑 係固體塑膠物質,其在適當位置固化或凝固以提供晶片與 引線框之間的堅固附著。各種黏著劑、膠帶及其他晶粒附 著材料已為人所知且可商用。 在一具體實施例令,黏著劑〇〇15)及周圍囊封物(1〇3〇) I26204.doc -48· 1337775 皆為黑色,從而向完成的晶片級封裝(1〇4〇)呈現均勻著 色。在其他具體實施例中,該黏著劑及囊封物係不同顏 色。在另外的具體實施例中,製造商可能希望為該黏著劑 及囊封物選擇特定互補或對比顏色(例如)以提供特定商業 包裝。 该黏著劑(10 15)之厚度並不重要,儘管將必須為足夠厚 以具有機械穩定性並耐受引線框之背面蝕刻。該黏著劑 (1015)通常覆蓋積體電路晶片(1020)的整個底部表面以避 免在隨後的背面蝕刻或背面圖樣化程序期間以化學或機械 方式損壞晶片。 一旦已將晶片(1 020)與膜(1 〇〇〇)晶粒附著,貝,丨(例如)使用 引線線路(1025)將該晶片與電引線(1005)連接,如圖34(:中 說明。使用囊封物(1030)密封(圖34d)該晶片(1〇2〇)及線路 引線(1025)。如以上說明,囊封物(1030)可以係該技術中 已知的任何物質。工業中使用的共同囊封物之非限制清單 包含矽石微粒填充式環氧樹脂以及液體環氧樹脂。該囊封 物係通常作為液體或黏性液體應用於安裝在引線框上或附 於引線框的各種元件。固化該囊封物會產生強硬、耐久塗 層,其保護晶片級封裝中的底下元件免於損壞。 在已固化囊封物(1030)之後’接著背面蝕刻引線框 (1000)以隔離電引線(1005),如圖34e中說明。晶片(1〇2〇) 底下的引線框(1000)之部分(即,最初晶片安裝區域)係在 背面蝕刻期間實質上或完全移除直至晶片黏著劑(丨〇丨5)。 引線框係接著沿街道形部分(1035)分割以產生適合於隨 126204.doc -49· 1337775 後應用(例如附著於電腦電路板)的個別囊封之晶片級封裝 (1040)製造商可針對識別目的而選擇在完成的晶片級 封袭上印刷或筛選_標示、批號或其他種類的標記。 圖35及3 6a刀別说明經由圖34a至34f所示的序列加以製 備的晶片級封裝(1040)之仰視及斷面圖。纟圖35中固化 的黏著劑(1G15)係顯示在晶片級封裝(ig4q)之中心作為較 亮顏色的不規則正方形。以較暗顏色顯示的囊封物⑽〇) 包圍固化的黏性物質(1G15)。囊封物(lG3G)覆蓋並包絡積 體電路晶;U1G2G)、線路(1G25)、引線(刚抑及可附於引 線框或安裝於其上的任何其他組件。 圖36b說明本發明之另一具體實施例,丨中複數個積體 電路晶片(1020、1050)係晶粒堆疊在完成的無墊晶片級封 4 (1070)中。儘官圖26b及36b顯示具有晶粒堆疊晶片的本 發明之具體實施例,但是圖26b中的具體實施例具有一晶 片墊(515)而圖36b中的具體實施例使用無墊技術。圖26b及 36b之比較顯示,晶片墊之缺少會減小獲得的晶片級封裝 之尚度’攸而允許製備具有較低輪廓的晶片級封裝。 可使用揭示的發明方法來製備圖36b中說明的具體實施 例。簡短而言’首先,下晶片(1〇2〇)係放置在並沒有一晶 片塾的一部份圖樣化之引線框(此圖中未說明)上,並且晶 片(1 020)係使用晶粒附著材料(丨〇丨5)(例如黏著劑或環氧)附 於該引線框》上晶片(1050)係因此使用一黏性物質 (1045)(例如導電或非導電環氧或絕緣材料)放置在下晶片 (1〇2〇)之頂部上並附於該下晶片。晶片(1020、ι〇5〇)係使 126204.doc -50- 1337775 用線路接合方式與引線框電連接。 可在將每-個晶片放置在引線框上之後按順序進行電連 接(1025)。即’第-晶片(1()2())可加以放置在引線框上並 與其電連接,且因此第二晶片(1 050)可加以放置在第一晶 片(102G)上並㈣線框電連接^在其他具體實施例中晶 片(1020、1050)係首先在適當位置晶粒堆疊,並接著進行 電連接。&等堆疊及電連接步驟之各種組合係可行的且在 本發明之範鳴内。 在晶片(1020、1050)得以晶粒堆疊並與引線框電連接 (1 025)之後’帛著採用—囊封物(1㈣)來囊封引線框以將 晶片及電線路永久地安裝於引線框。引線框之背面係接著 背面圖樣化、蝕刻並適當完成以隔離電引線(ι〇〇5)。在此 背面圖樣化程序期Pa1 ’完全移除晶粒堆疊晶片下面的引線 框之4 /7而且僅引線(⑽5)從完成的晶片級封裝"突出"。 般而D在奇面圖樣化之後保留的最初引線框之僅部分 係電引線(1 005)。取後,在街道形區中分割晶片級封裝以 產生用於後應用的個別晶片級封裝(丨〇7〇)。 依據本發明之另-態樣,可在晶粒附著之前部份圖樣化 或部份蝕刻引線框之頂部及底部。如圖37a中說明,可在 組裝晶片級封裝之前於兩側上蝕刻引線框⑴〇〇)。引線框 之兩側上的姓刻可且古a ^ ,、有均勻深度。或者,蝕刻可以係不均 勻的而且-側可比另_側圖樣化得深。例#,頂部(例如 區域1 1 6G)可比底部(例如區域i ^⑼圖樣化得深。 又側敍刻允許用於將最終加以移除的引線框之膜之部分 126204.doc 的減小厚度°因此’钱刻將進行得較快並從而增加生產速 X且減少成本。部份圖樣化可將該膜之蝕刻部分的厚度減 任何方便的數量。例如,引線框之部份圖樣化片段可移 除蝕刻區在或中的最初膜厚度的25至90%。 可採用光阻材料預圖樣化引線框材料。光阻可以係金屬 或非i屬(例如有機光阻),並可加以烤爐固化或uv固化。 此頒預圖樣化程序在該技術中已為人所知。 除採用金屬而預電鍍引線框以外,可採用可印刷油墨 (例如%氧油墨或模板油墨)或有機材料(例如聚醯亞胺樹 月曰’其作為背面姓刻之前的蝕刻遮罩)來印刷引線框。可 P刷/由墨或此技術有利地提供成本減少及流線型製造。從 材料觀點看’將可印刷油墨或有機物質用作蝕刻遮罩使該 製造商可從許多製造商獲得引線框來源,因為並非所有供 應商均可在兩侧上預電鍍引線框。在此類實例中,引線框 供應商將僅在頂部上蝕刻並電鍍引線框,從而使底部未完 成。例如,引線框之底部可以係裸金屬(例如銅)。採用可 印刷油墨或有機物質進行遮罩的成本通常比採用貴金屬 (例如把、金、鉑、铑、銀或釕或其組合,其為已用以預 電鍍引線框的物質之範例)進行遮罩的成本少。此外,在 钱刻之後移除油墨通常係比移除貴金屬容易。 亦可在蝕刻之前預電鍍引線框。在引線框之頂部及底部 表面上’預電鍍材料可以係相同或不同。適當的預電鍍材 料之範例包含線路可接合材料(例如衝擊型Ni/Pd/Au及銀 (Ag)),以及可焊材料(例如Sn/Pb、無鉛焊料、沈浸錫無電 126204.doc •52· 1337775 鍍鎳或衝擊型Au(金))。在本路日日* ”隹本發明之—具體實施例中,採 用可接合材料預電鍍前表面而且 叫i鉍用可焊材料預電鍍背表 :。在另-具體實施射,可採料線路接合材料預電鑛 前表面’而且採用光阻預電鍍並覆蓋背表面。在另外的具 體實施例中,可將有機材料印刷或應用於引線框上以用作 光阻。 圖36a顯示一膜(1100),其已加以蝕刻以形成晶片墊 (1U0)及複數個電引線⑴〇5)。該膜之頂部已加以蚀刻至 比該膜之底部[如藉由⑴65)所例證]大的範圍[如藉由 (1160)所例證](>圖3615顯示經由線路接合(1125)與圖3以所 示之引線框電連接的一晶片(112〇)。在圖3讣中,已使用一 黏著知1( 11 1 5)將積體電路晶片(1丨2〇)附於引線框(1丨〇〇),並 且已採用環氧囊封物(1130)覆蓋晶片封裝。街道形區 (1 135)分離電連接及囊封晶片(112〇)。
在已將晶片(1 120)附於引線框之晶片墊(1丨1 〇)並囊封之 後’引線框之背表面可加以背面圖樣化並蝕刻以隔離電引 線(1105)及晶片墊(1110),或另外電分離引線框之各種部 分以建立所需特徵。因為已經部份蝕刻背表面,所以此背 面触刻程序將更迅速地繼續並從而有利地改良每小時單位 (UPU)容量並降低成本。 先前引線框之底部晶粒墊一般係平坦的。圖37b說明具 有平坦底部晶粒塾的引線框之一範例。然而,在某些實例 中’此4平坦晶粒塾係傾向於當將晶片級封裝安裝於印刷 電路板時導致焊料空隙問題。在不受理論束缚的情況下, 126204.doc -53- 咸1s焊'14空隙係主要藉由囊封溶劑之除氣所引起的現象。 儘管焊料空隙會減小電接點之效率並因此可以引起第二位 準可罪H問題’但是_般僅可藉由χ光線顯微鏡或破壞性 微切片來该測焊料空隙。 依據本發明之另—態樣,—引線框可具有-已劃影線之 底4日曰粒墊。圖38顯不此類晶粒墊之一具體實施例。影線 〇255)可形成橫跨晶粒塾(丨叫之—通道並減」、晶粒塾與 印刷電路板之間的表面接觸區域,從而有利地減少焊料空 隙之數量。影線或通道(1255)作為通氣口以便在回焊期間 不存在捕獲空氣。 藉由在引線框之底部側上的墊下面製造小電鍍遮罩陣列 來獲知·已劃影線之底部墊(丨2 1 〇) ^在蝕刻期間,此電鍍遮 罩陣列將建立橫跨底部晶粒墊的半蝕刻通道。該遮罩將在 名虫刻程序期間作為光阻。 該蝕刻遮罩可以係鎳/鈀/金合成物(NipdAu)、銀、 銻(Sri)、鎳(Ni)或其混合物,或任何非金屬或有機材料或 可應用或印刷至引線框上的油墨。該蝕刻遮罩可以適當地 進行烤爐或UV固化。其他適當的遮罩及光阻物質在該技 術中已為人所知。可執行遮罩及蝕刻之程序,如先前所說 明。 圖38顯示一晶片級封裝(丨240),其具有一已劃影線之底 部晶粒墊(1210) ’複數個積體電路晶片(122〇、ι25〇)係安 裝至s亥墊。下晶片(1 220)係經由黏著劑(1 2 1 5)附於已劃影 線之晶粒墊,而且上晶片(1250)係經由黏著劑(丨245)附於 126204.doc -54· 1337775 下晶片(1220)。晶片(1220、1250)係經由線路接合(1225)與 電引線(1205)電連接,儘管在其他具體實施例 τ ,日日片 (1220、1250)亦可彼此電連接。採用可以係環氧樹脂或另 一物質的囊封物(1230)來囊封晶片。 儘管圖3 8顯示包括兩個晶粒堆疊積體電路晶片一曰 Π ^ 一日曰片 級封裝,但是在本發明之其他具體實施例中,可存在單一 晶片,而在另外的具體實施例中’可存在三或多個晶粒堆 疊aa片。所以此類具體貫施例係在本發明之範_内。亦可 存在附於引線框上的各種晶片墊之不同數目的晶片。例 如,一引線框之一個晶片墊可具有單一晶粒安裝晶片,而 同一引線框上的另一晶片墊可具有三個晶粒安裝晶片。因 此,本發明可用以在單一引線框上製備若干不同及非相同 晶片。 本發明之各種說明的具體實施例並非相互排斥的並可視 需要地進行組合以製備揭示的引線框之變化β例如,圖 37a中說明的不均勻蝕刻之引線框的晶粒墊之底部可進行 交又影線並用以製備圖38中說明的具有底部通道之晶片級 封裝。其他變化係可行的且在本發明之範疇内。 雖然已參考特定具體實施例而顯示並說明本發明,但是 熟習技術人士應瞭解可進行各種形式及細節上的更改而不 脫離本發明之精神及範疇。 【圖式簡單說明】 圖1 a係依據先前技術,具有引線及一晶片墊區域的一傳 統引線框之圖式。 126204.doc •55- 1337775 圖lb係依據先前技術,顯示將一晶片附著於晶片墊並將 該晶片上的端子線路至與引線接合的圖^之傳統引線框之 圖式。 圖2 a係依據先前技術,顯示藉由引線與下一位準封裝之 連接的線路接合及引線式(具有引線)接近晶片級封裝(csp) 之斷面圖。 圖2b係依據先前技術,顯示藉由焊料凸塊或球與下一位 準封裝之連接的線路接合及無弓丨線(沒有引線)接近csp之 斷面圖。 圖2c係依據先前技術,顯示藉由引線與下一位準封裝之 連接的覆品及引線式接近CSP之斷面圖。 圖2d係依據先前技術,顯示藉由焊球與下一位準封裝之 連接的覆品及無引線接近CSP之斷面圖。 圖3a係依據先前技術,顯示背面接合晶片與引線框之引 線的線路接合連接之模板狀引線框之俯視圖。 圖3b係依據先前技術,顯示透過一焊料回焊程序覆晶與 引線框之引線的連接之模板狀引線框之俯視圖。 圖4係依據本發明,採用可接合材料在兩側上進行預電 錢之均句厚度的金屬膜之斷面圖。 圖5係依據本發明的圖4之金屬膜的斷面圖,其中僅頂部 表面上的預電鍍已進行圖樣化以對應於兩個晶片地點,其 中每一個地點包含一晶片墊及包圍每—個晶片墊的引線接 點。 圖6係依據本發明,已進行部份圖樣化的圖4之電鍍金屬 126204.doc • 56- ⑴/775 骐的斷面圖。 圖6a係顯示依據本發明之部份圖樣化之引線框的矩陣之 俯視圖。 圖6b及6c顯示圖6&所示之矩陣中的引線框之逐漸放大俯 視圖。 圖7a係依據本發明的圖6之部份圖樣化之金屬膜的斷面 圖,其中已將一晶片附著於兩個晶片地點之每一個上的晶
片塾。 圖7b係依據本發明顯示且包括環氧或焊料之附著的晶片 與晶片墊之間的接合處之放大圖。 圖係依據本發明的圖7a或7b之晶片附著金屬膜之斷面 圖,其中已將每一個晶片上的端子線路接合至如此形成於 每一個晶片地點上的引線框之引線部分。 圖9係依據本發明的圖8之線路接合引線框之斷面圖,其
中已在一囊封物中密封包含晶片及線路接合的金屬膜之頂 部表面。 圖10係據本發明的圖9之密封封裝的斷面圖,該封裝已 從背側加以姓刻以移除該膜中的每一個引線框及衝道形區 阁 甘+ . i封裝的斷面 中已依據本發明在街道形區中分割囊封物以形成兩 個分離封裝。此等封裝可採用鋁線路、鋼線路 或採用任何其他方便的接合技街進行超聲波接合。口何 _依據本發明顯示晶片、接點以及將:片端子與 I26204.doc •57- 1337775 引線接點連接之線路的圖丨丨之分割封裝之一的俯視圖,以 及具有一線路接合的接點之一的放大斷面。 圖1 2b係依據本發明在晶片墊與接點之一之間的區域之 斷面圖,其顯示使用與模製材料接觸之垂直表面上的"唇 狀物”以便提供錨定並預防分層。 圖1 2c係依據本發明在晶片墊與接點之一之間的區域之 斷面圖,其顯示使用與模製材料接觸之垂直表面上的不同 形狀之空腔以便提供錨定並預防分層。 圖1 3 a至1 3 f係各種空腔之圖式,該等空腔可依據本發明 用以為圖12b及12c所示之垂直表面上的模製材料提供錨定 構件。 圖14係依據本發明的一流程圖,其概述形成一部份圖樣 化之封裝的各種程序步驟。 圖15a係依據本發明顯示具有周邊I/C)組態的封裝之俯 視、側視及仰視圖之圖式。 圖15b係依據本發明顯示具有1/0墊之陣列組態的封裝之 俯視、側視及仰視圖之圖式。 圖16係依據本發明的圖4之金屬膜的斷面圖,其中僅頂 部表面上的預電鍍材料已進行圖樣化以對應於兩個覆晶地 點,其中每一個地點包含一晶片接收區域及包圍每一個晶 片接收區域的引線。 圖1 7係依據本發明,已進行部份圖樣化以形成一網狀引 線框(即’網式結構)的圖16之電鍍金屬膜的斷面圖。 圖18係依據本發明,顯示覆晶(FC)接合的晶片接合式引 126204.doc -58- 線框(FCL)之斷面圖。 圓19係依據本發明的圓18之似之斷面圖,|中已在一 囊封物中密封包含晶片的金屬膜之頂部表面。 ,圖20係依據本發明的_之㈣封裝之斷面圖,該封裝 已從背側加以钱刻以還挥,w丨山必μ , J 、擇性地移除個別引線之間以及凹入 的晶片接收區域之間的網式部分。
圖21係依據本發明已從圖2Q之封裝分割㈣個接近晶片 大小的部份圖樣化之封裝的斷面圖。 圖22a係依據本發明的圖21之分割封裝之一的俯視圖, 其顯示晶片以及將晶片端子與引線之端部分連接的引線, 忒等端部分係依次與下一位準封裝連接。 圖22b係依據本發明在覆晶與顯示一引線之兩個端部連 接的下—位準封裝之連接之間的區域之放大斷面圖。 圖23係依據本發明的—流程圖,其概述形成支撐—覆晶 的部份圖樣化之封裝的各種程序步驟。
圖24a及24b顯示依據本發明已進行分割並接著具備用於 、下一位準封裝之連接以形成贴八型封裝的平台栅格陣 列連接個接近晶以小的部㈣樣化之 圖及仰視圖。 圖25a及25b顯示本發明之另一可選具體實施例,盆包括 將本發明之引線框封裝與下—位準封裝線路接合。此等圖 式說明圖243及241)之封裝採用紹線路(顯示在圖…幻或採 用鋼線路球接合技術(顯示在圖25b中)進行超聲波接合。鋼 線路球接合技術可用以將覆晶封裝與引線框連接。 126204.doc •59· 1337775 圖26a及26b係本發明之一具體實施例的透視及斷面圖, 其中晶粒堆疊複數個晶片以形成一半導體封裝 圖27a至27c係本發明之一具體實施例的透視及斷面圖, 其中晶片墊係凹入的以提供改良式晶粒堆疊以及封裝高度 方面的減小。 圖28a及28b顯示具有依據本發明之一具體實施例的凹入 曰曰片堅&域及晶粒堆受晶片的引線框之透視圖。 圖29a至29c顯示具有依據本發明之一態樣且以晶片塾鎖 定特徵之形式的變更之引線框的透視圖。 圖30a至30d說明具有依據本發明之一態樣之若干具體實 施例的變更之若干類型的電引線之俯視及側視圖。圖31a 至3 lb說明依據本發明之另一具體實施例的電引線之俯視 及側視圖’其中引線框或引線之表面已加以粗糙化。 圖32a至32e說明提供在電引線上且依據本發明之另一態 樣之若干類型的變更之透視圖。圖32f說明依據本發明之 另一態樣之一具體實施例的一電引線之俯視及側視圖,其 中已粗糙化引線框之表面以提供一囊封物之改良式黏著。 可結合本發明中呈現的變更來完成此表面粗糙化。 圖33a至33b說明本發明之具體實施例之一態樣,其中使 用一夾子代替線路接合以改良晶片之電源能力。 圊34a至34f說明一部份圖樣化之引線框之一具體實施 例,其中缺少一晶片接收區域,並且將晶片直接放置在引 線框上。在隨後的晶粒附著、線路接合、囊封以及背面圖 樣化與完成步驟之後,移除晶片下面的引線框之部分。此 I26204.doc •60· 1337775 元成步驟會曝露用以將晶片附於引線框的非導電黏著劑 (例如環氧材料或膠帶)。 圖35說明經由圖3乜至3^所示的序列進行製備的晶片級 封裝之仰視圖。 圖36ak供圖34f所示的晶片級封裝之斷面圖。圖361)提 供本發明之另一具體實施例之斷面圖,其中晶片級封裝包 括複數個晶粒堆疊之線路接合晶片。 圖37a說明一引線框,其中在將任何晶片附著於引線框 月J已。卩1¾圖樣化頂部及底部表面。圖37b說明圖37a之引 線框,一晶片已與該引線框連接,並且在背面圖樣化及分 割之前已囊封該引線框。 圖3 8說明包括複數個晶粒堆疊之線路接合晶片的一晶片 級封裝’其中已劃影線之晶粒墊之底部以提供空氣通風。 【主要元件符號說明】 100 金屬帶/金屬膜 107 空腔 110 前側 110' 預電鍍前側 11Γ 區域/底部表面 113 電接點/引線接點/區域 113, 引線部分/引線接點區域 115 晶片塾區域 115' 晶片接收區域/凹入區域 117, 中間區域/凹入區域 126204.doc -61 - 1337775 119' 區域 120 預電鍍材料/可焊預電鍍表面 120' 預電鍍底部表面 121 鋁線路 123 底部特徵/可焊層/接點 125 底部特徵/背面 130 網式結構 130' 覆晶(FC)/晶片 135 網式結構 135' 端子/焊球/晶片墊 136 街道形部分/區域 138 區塊/視窗膜 139 網式結構 140 晶片 140, 囊封物 145 端子 145, 引線 150 環氧 150' 焊料膏/卡或板 160 線路 170 囊封物 200 部份蝕刻引線框 200' 部份圖樣化引線框 210 晶片附者 126204.doc -62- 1337775 210' FC放置 220 環氧固化 220' FC晶片接合 230 線路接合 230' 囊封 240 囊封 240, 背面圖樣化/背面圖樣蝕刻 250 背面圖樣蝕刻 250' 分割 260 分割 300 標準周邊型封裝 305 周邊配置 310 部份圖樣化 320 模製材料 330 背面圖樣蝕刻 400 陣列類型封裝 405 陣列類型配置 410 部份圖樣化 420 模製材料 430 背面圖樣蝕刻 440 内部引線 445 外部引線 450 接地環特徵 460 陣列類型輸入/輸出組態 126204.doc •63 - 1337775 500 引線框 505 晶片 5 10 晶片 515 晶片塾/晶片塾接收區域 520 内部集 525 最外面集 530 囊封物 550 晶片塾區域/引線框 555 晶粒堆豐晶片/最大晶片 560 晶粒堆疊晶片/中間晶片 565 晶粒堆豐晶片/最小晶片 570 引線框 575 外正方形環 580 電引線 585 電引線 590 囊封物 600 引線框 605 晶片塾區域 610 晶片塾區域 615 晶片塾區域 620 晶片塾區域 625 晶片 630 晶片 635 晶片 /最面晶片 126204.doc -64 . 1337775
640 晶片 645 變更 650 囊封物 655 電引線 660 非晶片組件 705 變更 710 變更 715 變更 720 晶片塾區域 725 晶片塾區域 730 晶片塾區域 735 引線 740 引線 745 引線 750 引線 755 内部表面 760 引線 765 引線 770 表面 775 表面 800 引線框 805 晶片塾區域 810 圓形部分 815 電引線 -65 - 126204.doc 1337775 820 825 830 835 840 900 905 907
915 917 920 925 930 935 1000
1005 1010 1015 1020 1025 1030 1035 1040 引線 引線 引線 引線 引線 晶片塾區域 線路接合晶片 單一晶片/覆晶 線路接合晶片 引線 電引線 線路 夾子 焊料 晶片級封裝 膜 電引線部分 晶片安裝區域 黏著劑/非導電環氧/晶片墊 積體電路晶片/第一晶片/下晶片 引線線路/電連接 囊封物 街道形區域 晶片級封裝 126204.doc •66- 1337775
1045 黏性物質 1050 積體電路晶片/第 1070 晶片級封裝 1100 膜/引線框 1105 電引線 1110 晶片塾 1115 黏著劑 1120 晶片 1125 線路接合 1130 囊封物 1135 街道形區 1160 區域 1 165 區域 1205 電引線 1210 晶粒塾 1215 黏著劑 1220 積體電路晶片/下 1225 線路接合 1230 囊封物 1240 晶片級封裝 1245 黏著劑 1250 積體電路晶片/上 1255 影線或通道 片 / Jl晶片 126204.doc -67-

Claims (1)

133^775 7 ^7-______ 为曰修逆)正替换頁 第096140480號專利申請案 J ,中文申凊專利範圍替換本(99年7月) . 十、申請專利範圍: 1. -種形成晶片級封裝之方法,該方法包括下列步驟: 形成部份触刻之引線框之一區塊,該等弓丨線框包括網 式部分、-晶片安裝區域、複數個電引線部分 形部分; 將-積體電路晶片附著於該膜之第一區的該 區域; 在該晶片上的一或多個端子與該引線框上的一或多個 電引線部分之間形成電連接; 藉由在該等引線框及該等街道形部分上應用一囊封物 材料來囊封該引線框; 背面圖樣化該等引線框之該底部表面,以移除該等網 式部分、街道形部分以及該晶片安裝區域,&而移除該 積體電路晶片下面之該引線框的所有或一實質部分;以及 分割佈置在該引線框之該等街道形部分上的該囊封物 材料’以形成個別晶片級封裝。 2. 如吻求項1之方法,其中採用一預電鍍材料選擇性地預 電鍍該等引線框,或在囊封之前採用其頂部側、底部側 或兩者上之一遮罩材料來遮罩該等引線框。 3. 如請求項2之方法,其令使用衝擊型Ni/pd/Au、沈浸 Ag、Sn/Pb、無鉛焊料、沈浸錫無電鍍鎳、銀(Ag)或 Au(金)選擇性地預電鍍該等引線框。 4. 如請求項2之方法,其中使用一可印刷油墨、一模板油 墨、一環氧油墨或一有機物質選擇性地遮罩該等引線 126204-990723.doc U/775 yy]™Y 2c . V h曰修(更)正替痪資, 框。 5,如請求項2之方法,其中在背面圖樣化之後,從該等引 線框之該底部移除預電鍍材料或該遮罩材料。 6.如請求項丨之方法,其中該引線框包括一銅或銅合金之 膜。 月求項1之方法,其中該積體電路晶片係使用一黏著 劑附著於該晶片安裝區域。 月求項7之方法,其中該黏著劑係一樹脂、一環氧樹 脂、一焊料膏或一膠帶。 如1求項1之方法,其中藉由化學蝕刻、衝壓或壓印形 成該等弓丨線框。 10·如請求们之方法’其中該等晶片係使用線路接合與該 等引線框電連接。 U·如請求項1之方法,進一步包括: 將—或多個第二晶片晶粒堆叠至附於該引線框之該等 積體電路晶片的該等頂部上;以及 連接邊-或多個第二晶片與該引線框、附於該引線框 之該等積體電路晶片或兩者。 12=求項1之方法,其中該頂部與底部表面以-互補的 圖案被圖樣化。 13. 如睛求項1之太+,甘士 4 引線框的該底部表面以影 綠、通道或兩者作圖樣化。 14. 如請求項1之方法,盆中 _ . A 八平在4頂部表面的該圖樣化較在 该底部表面的該圖樣化為深。 126204-990723.doc 丄乃7775 厂1?7划- < . 年月日修(更)正替換頁 ‘ 1 5·—種依據請求項丨製造的部份圖樣化的引線框,該引線 框被用以製造一電子封裝,該引線框包括: '4 一膜’其具有一頂部表面及一底部表面; 該膜之該頂部表面具有(a)從該頂部表面但並非完全透 過至該底部表面而部份圖樣化之一第一區,以及(b)未從 該頂部表面部份圖樣化之一第二區,該第二區形成一用 、支撐積體電路(1C)晶片的晶片整區域’以及用以提 • 供與該IC晶片之電連接的複數個電引線,該晶片墊區域 及該複數個電引線係經由該第一區連接但並非透過該頂 部表面連接;以及 該膜之該底部表面,其係從該底部表面但並非完全透 過至該頂部表面而部份圖樣化。 1 6· -種用上乂形成晶片級封裝之方法,該方法包括: 立提供-部份圖樣化之引線框’該引線框具有⑷從該頂 部表面但並非完全透過至該底部表面而部份圖樣化之— Φ 第區,以及未從該頂部表面部份圖樣化之一第二 區’該第二區形成—用以支撐一積體電路(1C)晶片的晶 片塾區域以及用以提供與該IC晶片之電連接的複數個電 引線,該晶片整區域及複數個電引線係經由該第一區連 接但並非透過該頂部表面連接; 將一積體電路晶片附著於該引線框之該第—區的該晶 片整區域; 在該晶片上的一或多個端子與該引線框上的一或多個 電引線部分之間形成電連接; 126204-990723.doc ///^
7· 28 藉由在該等引線框及街道形部 來囊封該引線框; 月曰修(更)王替換頁| 分上應用一囊封物材料 17. 18. 19. 背面圖樣化該等引線框之該底部表面以移除該等網式 部分以及衔道形部分,並且移除該晶片塾區域之該底部 表面之-部分以形成透過其的—或多個通道;以及 ”割佈置在$引線框之該等衝道形部分上的該囊封物 材料’以形成個別晶片級封裝。 如"月求項16之方法,其中該晶片墊區域之該一或多個通 道橫跨整個晶片墊區域之長度而延伸。 °月求項1 6之方法,其中該—或多個通道係採用影線之 形式。 士 Μ求項1 7之方法,其中該一或多個通道功能為排氣 孔0
l26204-990723.doc
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