CN102054717A - 半导体芯片栅格阵列封装及其制造方法 - Google Patents

半导体芯片栅格阵列封装及其制造方法 Download PDF

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CN102054717A
CN102054717A CN200910212100XA CN200910212100A CN102054717A CN 102054717 A CN102054717 A CN 102054717A CN 200910212100X A CN200910212100X A CN 200910212100XA CN 200910212100 A CN200910212100 A CN 200910212100A CN 102054717 A CN102054717 A CN 102054717A
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grid array
conductive sheet
semiconductor chip
column cap
connector pad
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白志刚
陈伟民
王志杰
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NXP USA Inc
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Freescale Semiconductor Inc
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Priority to CN200910212100XA priority Critical patent/CN102054717A/zh
Priority to US12/790,999 priority patent/US20110108967A1/en
Publication of CN102054717A publication Critical patent/CN102054717A/zh
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Abstract

本发明涉及半导体芯片栅格阵列封装及其制造方法。半导体芯片栅格阵列封装包括管芯附接焊盘和多个连接器焊盘。半导体管芯安装在该管芯附接焊盘上，该半导体管芯具有分别电连接到连接器焊盘的外部连接端子。密封材料密封该管芯和连接器焊盘。柱头从每个连接器焊盘凸起，以提供用于半导体芯片栅格阵列封装的外部电接触。连接器焊盘和各柱头中的每一个由导电片材形成。连接器焊盘的厚度至少是该导电片材厚度的60％，并且各柱头的厚度不多于该导电片材厚度的40％。

Description

半导体芯片栅格阵列封装及其制造方法
技术领域
本发明一般涉及半导体封装。更具体来说，本发明涉及用于加工半导体芯片栅格阵列封装的方法以及可以使用该方法制造的半导体芯片栅格阵列封装。
背景技术
一种典型类型的封装半导体是四方扁平封装(Quad Flat Pack，QFP)，其由安装到引线框架的半导体管芯形成。引线框架由金属片材形成，该金属片材包括通常称为标志(flag)的管芯附接焊盘(die attach pad)和将该标志附接到框架的臂。引线框架的引线上的焊盘通过导线接合到管芯的电极，以提供容易地将该管芯电连接到电路板等的手段。在电极和焊盘通过导线接合之后，将该半导体管芯和焊盘密封在诸如塑料材料的化合物(材料)中，只留下部分引线被露出。将这些露出的引线从引线框架的框架上切断(拆分，singulate)并弯曲以使其容易连接到电路板。然而，QFP封装的固有结构导致对引线数量的限制，并且因此限制可用于特定QFP封装尺寸的封装的外部电连接的数量。
作为QFP封装的替代，已经开发出了栅格阵列封装。栅格阵列封装增加了外部电连接的数量，同时保持或者甚至减小封装尺寸。这种栅格阵列封装包括针型栅格阵列(Pin Grid Array)、球型栅格阵列(Ball Grid Array)和基板栅格阵列(Land Grid Array)。典型地，大多数传统栅格阵列封装是基于衬底的，并且相对昂贵。因此，已经开发出较便宜的基于引线框架的栅格阵列封装。然而，由于这种基于引线框架的栅格阵列封装的外部电连接的密度高，因此当将它们焊接到电路板时，相邻的外部电连接之间可能出现焊料短路。此外，基于引线框架的栅格阵列封装的外部电连接典型地由导电材料(例如铜或铝)的薄的单一片材制成，并且这些连接也许不能充分地保持在密封化合物(材料)内并且可能松动。
附图说明
通过参考以下对优选实施例的说明及附图，可以最好地理解本发明及其目的和优点，在附图中：
图1是根据本发明的实施例的导电片材的平面图；
图2是图1的导电片材的通过2-2’的截面图；
图3是根据本发明的实施例在已经进行沟道蚀刻之后的图1的导电片材的通过2-2’的截面图；
图4是根据本发明的实施例在安装半导体管芯之后的导电片材的通过2-2’的截面图；
图5是根据本发明的实施例导线接合之后的导电片材的通过2-2’的截面图；
图6是根据本发明的实施例在进行密封之后的导电片材的通过2-2’的截面图；
图7是根据本发明的实施例在导电片材的面对外部的表面上按阵列布置抗蚀剂材料之后的导电片材的通过2-2’的截面图；
图8是根据本发明的实施例在蚀刻面向外部的表面之后的导电片材的通过2-2’的截面图；
图9是根据本发明的实施例的半导体芯片栅格阵列封装的下侧平面图；
图10是示出根据本发明的实施例的用于制造图9的半导体芯片栅格阵列封装的方法的流程图；以及
图11是根据本发明的实施例包括图9的半导体芯片栅格阵列封装的部分电路板组件的截面图。
具体实施方式
意图将以下结合附图给出的详细说明作为对本发明的当前优选实施例的说明，并且不意味着其代表可以实施本发明的仅有形式。应该理解，通过意图包含在本发明的精神和范围内的不同实施例可以实现相同或等价的功能。在所有附图中，使用相同的标号表示相同的要素。此外，术语“包括”、“包括的”或它的任何其它变体都意图涵盖非排他的包括，使得包括一系列要素或步骤的封装、电路、装置组件及方法步骤不仅包括那些要素，而且还可以包括没有明确列出或者这些封装、电路、装置组件或步骤固有的其他要素或步骤。由“包括一个...”引导的要素或步骤在没有更多约束的情况下，不排除包括该要素或步骤的额外相同要素或步骤的存在。
在一个实施例中，本发明提供一种用于制造半导体芯片栅格阵列封装的方法。该方法包括提供导电片材，该导电片材在一侧具有面向芯片的表面，在另一侧具有面向外部的表面。接下来在该导电片材的面向芯片的表面中进行蚀刻沟道的处理，从而以管芯附接焊盘和多个连接器焊盘(connector pad)的形式定义栅格阵列焊盘。该沟道被蚀刻的深度至少是该导电片材厚度的60％，然后进行将半导体管芯安装在该管芯附接焊盘上的处理。然后该方法进行将所述连接器焊盘电连接到所述管芯上的各外部连接端子的处理。接下来，该方法进行将所述管芯、沟道和连接器焊盘密封在密封材料中的处理。最后，进行蚀刻该导电片材的面向外部的表面的处理以将所述栅格阵列焊盘相互电隔离。蚀刻面向外部的表面的特征在于去除介于相邻的栅格阵列焊盘之间的导电片材的区域，并且其中蚀刻面向外部的表面提供从每个连接器焊盘凸起的柱头(stud)。
在另一个实施例中，本发明提供一种包括管芯附接焊盘和多个连接器焊盘的半导体芯片栅格阵列封装。该半导体芯片栅格阵列封装具有安装在所述管芯附接焊盘上的半导体管芯，所述半导体管芯具有分别电连接到所述连接器焊盘的外部连接端子。具有密封所述管芯和连接器焊盘的密封材料。柱头从每个连接器焊盘凸起以提供用于所述半导体芯片栅格阵列封装的外部电接触。所述连接器焊盘和各柱头中的每一个由导电片材形成。所述连接器焊盘的厚度是所述导电片材厚度的至少60％，并且各柱头的厚度不大于所述导电片材厚度的40％。
参照图1和图2，它们示出了导电片材100的平面图和导电片材100的通过2-2’的截面图。在用于制造半导体芯片栅格阵列封装的方法的第一步骤中提供导电片材100。导电片材100典型地由铜、铝或者任何其它适当的金属制成，这对本领域的技术人员来说是显而易见的。在导电片材100的一侧上有面向芯片的表面110，并且在导电片材100的另一侧上是面向外部的表面210。如所示出的，在导电片材100的面向芯片的表面110上以阵列的形式布置抗蚀剂材料120。
参照图3，其示出在面向芯片的表面110中已经进行了沟道310的蚀刻之后的导电片材100的通过2-2’的截面图。沟道310的蚀刻以管芯附接焊盘320和多个连接器焊盘330的形式定义了栅格阵列焊盘GP。这些沟道310被蚀刻到导电片材100的厚度T的至少60％的深度D。然而，在另一个实施例中，沟道310被蚀刻到导电片材100的厚度T的至少70％的深度的。此外，在另一个实施例中，沟道310被蚀刻到导电片材100的厚度T的70％至80％之间的深度D。
参照图4，其示出了在已经将半导体管芯410安装到管芯附接焊盘320上之后的导电片材100的通过2-2’的截面图。半导体管芯410在上表面上具有外部连接端子420并且下表面通过固化的环氧树脂430接合到管芯附接焊盘320，然而，可以使用焊膏和双面带作为用于接合的替换手段。
参照图5，其示出在已经将连接器焊盘330连接到管芯410上的各外部连接端子420之后的导电片材100的通过2-2’的截面图。典型地，在连接器焊盘330和各外部连接端子420之间通过导线接合用的金线510进行电连接。
在图6中，示出了在将管芯410、沟道310和连接器焊盘330封装在密封材料610中之后的导电片材100的通过2-2’的截面图。该密封材料610是电绝缘材料，通常为塑料，其典型地被模塑到导电片材100。
图7中示出了在抗蚀剂材料710以阵列形式布置在导电片材100的面向外部的表面210上之后的导电片材100的通过2-2’的截面图。抗蚀剂材料710被设置成使得它将蚀刻剂暴露给介于相邻栅格阵列焊盘(GP)之间的导电片材100的区域720。
在图8中示出了在蚀刻导电片材100的面向外部的表面210以将栅格阵列焊盘GP相互电隔离之后的导电片材100的通过2-2’的截面图。更具体来说，对面向外部的表面210的蚀刻去除了介于相邻栅格阵列焊盘(GP)之间的导电片材的区域720。在蚀刻面向外部的表面210之后，基本完成了对半导体芯片栅格阵列封装800的制造。对面向外部的表面210的蚀刻向半导体芯片栅格阵列封装800提供了从每个连接器焊盘330凸起的柱头810和从管芯附接焊盘320延伸的外部底座(mount)820。理想地，并且如所示出的，每个柱头具有与外部底座820的安装表面840在同一平面(平面P中)的安装表面830。
如果沟道310被蚀刻到导电片材100的厚度T的至少60％的深度D，则每个柱头810将具有不大于导电片材厚度的40％的深度，这对本领域的技术人员来说是显而易见的。类似地，如果沟道310被蚀刻到导电片材100的厚度T的至少70％的深度D，则每个柱头810将具有不大于导电片材100的厚度的30％的深度。此外，如果沟道310被蚀刻到导电片材100的厚度T的70％至80％之间的深度D，则每个柱头810将具有导电片材100的厚度的20％至30％之间的深度。
参照图9，其示出了半导体芯片栅格阵列封装800的下侧平面图。如所示出的，从每个连接器焊盘330凸出的柱头810是具有圆形截面的柱R。所述柱R具有比柱头从其凸出的连接器焊盘330的最大宽度Y小至少30％的最大直径X。可以设想该柱头是一般性的，从每个连接器焊盘330凸出的柱头810可以不是具有圆形截面的柱。因此，作为一般规则，柱头810具有比柱头从其凸出的连接器焊盘的最大宽度小至少30％的最大宽度。
图10是总结如通过主要参照图1-8描述的上述步骤执行的用于制造半导体芯片栅格阵列封装800的方法1000的流程图。在提供步骤1010，提供导电片材100。典型地，导电片材100的尺寸足够大，以使得能够制造多个半导体芯片栅格阵列封装800。然而，为了容易示出，上面只示出了并且方法1000将只描述对一个半导体芯片栅格阵列封装800的制造。
在布置步骤1020进行将抗蚀剂材料120布置在导电片材100的面向芯片的表面上的处理，并且蚀刻处理1030以管芯附接焊盘320和连接器焊盘330的形式定义栅格阵列焊盘GP。
然后安装或管芯接合处理1040将半导体管芯410安装到管芯附接焊盘320上并且导线接合处理1050进行将连接器焊盘330电连接到半导体管芯上的各外部连接端子420的处理。接下来，通过密封处理1060密封半导体管芯410，然后在布置步骤1040将抗蚀剂材料710以阵列形式布置在面向外部的表面210上。然后蚀刻处理1070进行蚀刻导电片材100的面向外部的表面210的处理以将栅格阵列焊盘GP相互电隔离。如上所述，典型地，导电片材100的尺寸足够大，以使得能够制造多个半导体芯片栅格阵列封装800。因此，可能需要用锯进行的拆分处理1080以将半导体芯片栅格阵列封装800从在导电片材100上制作的其它半导体芯片栅格阵列封装上拆分(分离)。然后方法1000返回到提供步骤1010并在导电片材100上重复该方法1000。
参照图11，其示出了包括半导体芯片栅格阵列封装800的部分电路板组件1100的截面图。为了容易说明，只示出了芯片栅格阵列封装800的一部分。电路板组件1100具有电路板衬底1110以及焊料焊盘1120和相关的流道(runner，未示出)。柱头810已经通过焊料1130焊接到各自的焊料焊盘1120。如所示出的，由于焊料1130上的表面张力影响(在焊接期间处于熔化状态时)，焊料1130倾向于被吸引到其相关连接器焊盘330的下侧。作为该表面张力影响的结果，焊料1130在相邻焊料焊盘1120之间短路的可能性被减小。
本发明有利地提供一种与大多数类似尺寸的传统QFP封装相比可以促进增加外部电连接(柱头810)的数量的芯片栅格阵列封装。此外，由于上述表面张力的影响，当柱头焊接到电路板时，本发明减小了在相邻柱头810之间焊接短路的可能性。此外，由于沟道310被蚀刻到导电片材100的厚度T的至少60％的深度D，所以连接器焊盘330的相对较大的表面面积可以接合到密封材料610。因此连接器焊盘330的该相对较大的表面面积减小了在密封材料610中连接器焊盘330松动的可能性。
为了图解和描述的目的给出了对本发明的优选实施例的描述，但是该描述不意图是详尽的或者将本发明限制到所公开的形式。本领域的技术人员将意识到，在不偏离本发明的宽泛发明概念的情况下，可以对上述实施例进行变化。因此，应该理解，本发明不局限于所公开的具体实施例，而是覆盖如所附权利要求限定的本发明的精神和范围内的修改。

Claims (12)

1.一种用于制造半导体芯片栅格阵列封装的方法，包括：
提供导电片材，所述导电片材在一侧具有面向芯片的表面，而在另一侧具有面向外部的表面；
在所述导电片材的面向芯片的表面上蚀刻沟道，从而以管芯附接焊盘和多个连接器焊盘的形式定义栅格阵列焊盘，其中所述沟道被蚀刻的深度是所述导电片材厚度的至少60％；
将半导体管芯安装到所述管芯附接焊盘上；
将所述连接器焊盘电连接到所述管芯上的各外部连接端子；
将所述管芯、沟道和连接器焊盘密封在密封材料中；以及
蚀刻所述导电片材的面向外部的表面以将所述栅格阵列焊盘相互电隔离，其中蚀刻面向外部的表面的特征在于去除介于相邻的栅格阵列焊盘之间的所述导电片材的区域，并且其中蚀刻面向外部的表面形成从每个所述连接器焊盘凸起的柱头。
2.根据权利要求1所述的制造半导体芯片栅格阵列封装的方法，其中所述管芯附接焊盘的外部安装表面与从每个所述连接器焊盘凸起的每个所述柱头的安装表面在同一平面。
3.根据权利要求1所述的制造半导体芯片栅格阵列封装的方法，其中所述沟道被蚀刻到所述导电片材厚度的至少70％的深度。
4.根据权利要求1所述的制造半导体芯片栅格阵列封装的方法，其中所述柱头的深度不大于所述导电片材厚度的40％。
5.根据权利要求1所述的制造半导体芯片栅格阵列封装的方法，其中所述柱头的最大宽度比所述柱头从其凸起的所述连接器焊盘的最大宽度小至少30％。
6.根据权利要求1所述的制造半导体芯片栅格阵列封装的方法，其中从每个所述连接器焊盘凸起的所述柱头是具有圆形截面的柱，并且其中所述柱的最大直径比所述柱头从其凸起的所述连接器焊盘的最大宽度小至少30％。
7.根据权利要求1所述的制造半导体芯片栅格阵列封装的方法，其中所述导电片材的尺寸足够大以使得能够制造多个半导体芯片栅格阵列封装，并且所述方法包括从在所述导电片材上制造的其它半导体芯片栅格阵列封装中拆分半导体芯片栅格阵列封装的另外步骤。
8.一种半导体芯片栅格阵列封装，包括：
管芯附接焊盘和多个连接器焊盘；
安装在所述管芯附接焊盘上的半导体管芯，所述半导体管芯具有分别电连接到所述连接器焊盘的外部连接端子；
密封所述管芯和连接器焊盘的密封材料；
从每个所述连接器焊盘凸起的柱头，用来提供用于所述半导体芯片栅格阵列封装的外部电接触，其中所述连接器焊盘和各柱头中的每一个由导电片材形成，并且所述连接器焊盘的厚度是所述导电片材厚度的至少60％，各柱头的厚度不大于所述导电片材厚度的40％。
9.根据权利要求8所述的半导体芯片栅格阵列封装，其中所述管芯附接焊盘的外部安装表面与从每个所述连接器焊盘凸起的每个柱头的安装表面在同一平面。
10.根据权利要求8所述的半导体芯片栅格阵列封装，其中所述连接器焊盘的厚度是所述导电片材厚度的至少70％，并且各柱头的厚度不大于所述导电片材厚度的30％。
11.根据权利要求8所述的半导体芯片栅格阵列封装，其中从每个所述连接器焊盘凸起的所述柱头是具有圆形截面的柱，并且其中所述柱的最大直径比所述柱头从其凸起的所述连接器焊盘的最大宽度小至少30％。
12.根据权利要求8所述的半导体芯片栅格阵列封装，其中所述柱头的最大宽度比所述柱头从其凸起的所述连接器焊盘的最大宽度小至少30％。
CN200910212100XA 2009-11-10 2009-11-10 半导体芯片栅格阵列封装及其制造方法 Pending CN102054717A (zh)

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