CN110783211B - 芯片组件及其制造方法 - Google Patents

芯片组件及其制造方法 Download PDF

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CN110783211B
CN110783211B CN201910681214.2A CN201910681214A CN110783211B CN 110783211 B CN110783211 B CN 110783211B CN 201910681214 A CN201910681214 A CN 201910681214A CN 110783211 B CN110783211 B CN 110783211B
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carrier
grid array
metal grid
chip
electronic chip
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CN110783211A (zh
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A·海因里希
F·达奇
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

本发明公开了一种芯片组件(100)，其包括：载体(102)；包括至少一个开口(108)的金属网格阵列(106)；通过附接材料(104)附接至所述载体(102)的金属网格阵列(106)，所述金属网格阵列(106)和所述载体(102)限定了至少一个腔穴(112)，所述至少一个腔穴(112)中的每者是由所述至少一个开口(108)之一和所述载体(102)形成的；以及安装在所述至少一个腔穴(112)中的每者中的电子芯片(116)。

Description

芯片组件及其制造方法
技术领域
本文公开的主题涉及芯片和芯片组件以及制造芯片和芯片组件的方法。
背景技术
为了处理和/或使用，个体电子芯片典型地可以被放置并且固定在共用载体上，例如，在引线框架、印刷电路板(PCB)或者直接铜接合(DCB)上。为此，电子芯片可以被逐一放置并且固定到载体上。替代地，芯片可以被上下颠倒放置在中间载体上，之后被一起放置在载体上，并且通过(例如)热管芯附接工艺被共同固定。
此外，DE 10 2014 114 982 A1公开了一种形成芯片组件的方法，其包括在载体中形成多个腔穴，将管芯附接液体布置在腔穴中的每者中，将多个芯片布置在管芯附接液体上，蒸发管芯附接液体，并且在蒸发管芯附接液体之后，将多个芯片固定到载体上。
发明内容
可能需要改进芯片组件(并且特别是芯片基底)的制造。
根据本文公开的主题的第一方面，提供了一种制造芯片组件的方法。根据示例性实施例，制造芯片组件的方法包括：提供载体；提供金属网格阵列，所述金属网格阵列包括至少一个开口；通过附接材料将金属网格阵列附接至载体，其中，所述金属网格阵列和所述载体限定了至少一个腔穴，所述腔穴中的每者是由所述至少一个开口之一和所述载体形成的；将电子芯片安装在所述至少一个腔穴中的每者中。根据另一示例性实施例，制造芯片组件的方法包括：提供载体；在所述载体上提供附接材料；提供金属网格阵列，所述金属网格阵列包括至少一个开口；通过附接材料将金属网格阵列附接至载体，其中，所述金属网格阵列和所述载体限定了至少一个腔穴，所述腔穴中的每者是由所述至少一个开口之一和所述载体形成的；将电子芯片安装在所述至少一个腔穴中的每者中。
根据本文公开的主题的第二方面，提供了芯片组件。根据示例性实施例，所述芯片组件包括：载体；包括至少一个开口的金属网格阵列；所述金属网格阵列通过附接材料附接至所述载体；所述金属网格阵列和所述载体限定了至少一个腔穴，所述至少一个腔穴中的每者是由所述至少一个开口之一和所述载体形成的；以及安装在所述至少一个腔穴中的每者中的电子芯片。根据另一示例性实施例，所述芯片组件包括：载体；包括至少一个开口的金属网格阵列；所述金属网格阵列通过附接材料附接至所述载体；所述金属网格阵列和所述载体限定了至少一个腔穴，所述至少一个腔穴中的每者是由所述至少一个开口之一和所述载体形成的；以及安装在所述至少一个腔穴中的每者中的电子芯片。
对其它示例性实施例的描述
在下文中，将描述芯片基底、芯片组件和方法的其它示例性实施例。
在本申请的语境下，术语“封装体”可以特别表示至少一个至少部分包封的电子芯片，所述电子芯片具有至少一个外部电接触部。例如，封装体可以是表面安装器件(SMD)或者通孔安装器件(TMD)。
术语“封装”可以特别表示利用包封物至少部分地包封电子芯片。
术语“电子芯片”可以特别表示在其表面部分中具有至少一个集成电路元件(例如，二极管或晶体管)的半导体芯片。电子芯片可以是裸管芯，或者可以是已经封装的。根据实施例，电子芯片包括(例如，是)半导体芯片，特别是功率半导体芯片，例如垂直电流器件，特别是绝缘栅双极晶体管(IGBT)、金属氧化物场效应晶体管(MOSFET)、碳化硅(SiC)器件或者氮化镓(GaN)器件。根据实施例，功率半导体芯片是具有垂直功率流的芯片(即，垂直电流器件，特别是在芯片的相对侧中的每者上具有负载电极(例如，单个负载电极)的芯片)。根据实施例，功率半导体芯片包括绝缘栅双极晶体管、场效应晶体管(例如，金属氧化物半导体场效应晶体管)、二极管等中的至少一者。借助于这样的构成，有可能提供用于汽车应用、高频应用等的封装体。可以由这样的以及其它的功率半导体电路和封装体构成的电路的示例为半桥、全桥等。
在本申请的语境下，术语“包封物”可以特别表示包围(例如，密封地包围)载体的部分和电子芯片以提供保护、电绝缘并且任选地在操作期间对散热有贡献的基本上电绝缘并且优选导热的材料。在实施例中，包封物可以是模制材料。因而，封装体可以包括至少部分地由模制材料形成的封装体主体。例如，可以通过将电子芯片(特别是连同载体和任选的其它部件)放置到模具中并且向其中注入液体模制材料来提供封装体。在模制材料凝固之后，完成了包封物的形成。如果希望，可以利用改善模制材料的特性的颗粒对模制材料进行填充。在实施例中，包封物包括层合物，特别是印刷电路板层合物。根据实施例，所述方法还包括在电子芯片之上布置层合物。
在本申请的语境下，术语“层合物”或者“层合物结构”可以特别表示由可以通过施加压力而相互连接的导电结构和/或电绝缘结构所形成的整体平直构件。通过按压实施的连接可以任选地伴有热能的供应。因而，层合可以被表示为制造多层中的复合材料的技术。可以通过加热和/或压力和/或焊接和/或粘合剂对层合物进行永久性组装。根据另一实施例，包封物包括具有至少一个电绝缘层和至少一个导电层的层合物。在实施例中，层合物是印刷电路板(PCB)层合物。因而，层合物的材料特别可以基于树脂(特别是环氧树脂)，如果希望可以与颗粒(例如，纤维，如玻璃纤维)混合。用于层合物的适当电介质材料为预浸料或FR4。用于层合物的适当导电材料为铜。
在实施例中，电子芯片包括处于与层合物接触的主表面上的导电接触结构。例如，电子芯片可以布置有面朝向一个或多个外部层合物层(即，面向上)的第一表面(例如，其有效表面或顶表面)。替代地，例如，在实施具有垂直电流流动的电子芯片、功率半导体芯片等时，还有可能使电子芯片的两侧具有电接触部。在这样的情况下，电子芯片可以布置有面朝向一个或多个外部层合物层(即，面向上)的第二表面(例如，其底表面)。
在实施例中，所述方法还包括形成(特别是通过钻孔，更特别是通过激光钻孔)延伸穿过层合物以由此暴露电子芯片的表面的至少一个通孔。穿过层合物材料进行激光钻孔以暴露电子芯片的一个或多个焊盘是用于快速并且精确地限定电接触部的简单且可靠的过程。因而，在这样的情况下，通孔还可以被称为接触孔。
在实施例中，所述方法还包括利用导电材料、特别是通过电镀来填充至少一个通孔。例如，可以在通过激光钻孔或者机械钻孔等形成的通孔中填充铜材料。
在本申请的语境下，术语“衬底”可以特别表示至少部分导电的结构，其充当一个或多个芯片的支撑部，和/或对芯片与至少一个其它部件(例如，内部部件和/或外部部件)之间的电互连有贡献。换言之，载体可以实现机械支撑功能和/或电连接功能。
在本申请的语境下，术语“部件”可以特别表示可以电连接至载体以向封装体提供其电子功能的任何电构件或电子构件。具体而言，部件可以是无源部件，诸如导电迹线、电感器(特别是线圈)、电容器(例如，陶瓷电容器)、欧姆电阻、电感、二极管、变压器等。具体而言，不能通过另一电信号来控制电流的部件可以被表示为无源部件。然而，部件也可以是有源部件，具体而言，可以是能够通过另一电信号来控制电流的部件。有源部件可以是具有放大信号或产生功率增益的能力的模拟电子滤波器、振荡器、晶体管或者另一集成电路元件。
在实施例中，载体是金属载体，特别是引线框架。在本申请的语境下，术语“引线框架”可以特别表示被配置成薄板状金属结构的载体的优选示例，所述薄板状金属结构可以被图案化(例如，冲压或蚀刻)以便形成用于安装芯片的引线框架区段。芯片到载体的电连接可以是通过焊料(例如，焊盘)、导线等建立的。在实施例中，引线框架可以是金属板(即，又可以被称为金属箔的薄金属板，特别是由铜、镍、银、钢或者其它适当材料(特别是适当金属)构成)，可以通过(例如)冲压或蚀刻对该金属板进行图案化。将载体形成为引线框架是经济高效的，并且在机械和电气上是非常有利的配置，其中，能够使芯片和部件的低欧姆连接与引线框架的鲁棒支撑能力相结合。此外，由于引线框架的金属(特别是铜)材料的高热导率，引线框架可以对封装体的热导率有贡献，并且可以去除在芯片和部件的操作期间生成的热。引线框架或者任何其它金属载体因其简单性而可以是优选的。
根据另一实施例，载体是印刷电路板(PCB)。因而，载体可以特别是基于树脂(特别是环氧树脂)而制造的，如果希望，载体可以与颗粒(例如，纤维，如玻璃纤维)混合。用于PCB的适当电介质材料为(例如)预浸料或FR4。用于PCB的适当导电材料为铜。
根据实施例，载体是包括陶瓷部分和金属部分的分层结构。例如，根据实施例，载体是包括陶瓷板和接合至其一侧(或其相对两侧)的铜层的直接铜接合(DCB)。可以通过在铜层和陶瓷板之间形成接合的铜-氧共晶来提供铜层和陶瓷板之间的接合。铜-氧共晶可以是通过在含有20-40ppm的量的氧气的氮气气氛中将铜层和陶瓷板加热到受控温度而形成的。接合至陶瓷的铜层可以被成形为某一图案(例如，铜层可以在被接合至陶瓷板之前被预成形(例如，冲压)，或者铜层可以被结构化(例如，通过蚀刻))。根据实施例，在陶瓷板上形成铜层包括施加晶种层和镀敷晶种层。陶瓷材料可以包括(例如)氧化铝(Al2O3)、氮化铝(AlN)或氧化铍(BeO)中的一者或多者。铜层可以具有处于200微米(μm)和300μm之间的范围内的厚度，并且可以(例如)利用镍、镍合金、铝镍或者铝来镀敷铜层。
在实施例中，至少一个电子芯片包括由控制器电路、驱动器电路和功率半导体电路构成的组中的至少一个。所有这些电路可以被集成到一个电子芯片中，或者可以被单独集成到不同芯片中。例如，可以通过芯片实现对应的功率半导体应用，其中，这样的功率半导体芯片的集成电路元件可以包括至少一个晶体管、至少一个二极管等，所述晶体管例如是至少一个绝缘栅双极晶体管(IGBT)和/或至少一个场效应晶体管和/或至少一个碳化硅(SiC)器件和/或至少一个氮化镓(GaN)器件(特别是MOSFET，金属氧化物半导体场效应晶体管)。具体而言，可以制造实现半桥功能、全桥功能等的电路。根据实施例，(至少一个)电子芯片具有处于至少一个外表面上的金属化(例如，背侧金属化)。根据实施例，金属化包括以下中的至少一种：铝(Al)、钛(Ti)、镍(Ni)、钒(V)、银(Ag)和铜(Cu)、或者这些金属中的一者或多者的至少一种合金。根据实施例，金属化为Al/TiNiV/Ag(4LBSM)层堆叠体。根据另一实施例，金属化为Ti/NiV/Ag层堆叠体。根据另一实施例，金属化为Al/Ti/Cu层堆叠体。
典型的管芯厚度处于60μm到200μm的范围内，例如，处于60μm到110μm的范围内。根据另一实施例，所述厚度甚至更小，例如，大于20μm。根据另一实施例，所述厚度处于200μm和210μm之间，例如，等于或者小于205μm。
根据实施例，金属网格阵列包括多个开口，并且载体和附接至载体的金属网格阵列(作为中间器件制造的)限定了多个腔穴。根据实施例，多个腔穴中的每者是通过多个开口之一和载体形成的。
根据实施例，金属网格阵列和载体被统称为芯片基底，多个电子芯片在多个腔穴中被安装到芯片基底。
通过载体和附接的具有开口的金属网格阵列提供腔穴有助于提供具有镀锡平面底部的腔穴。平面底部提高了相应电子芯片到腔穴的底部的连接的可靠性。此外，通过在金属网格阵列中提供开口而提供腔穴有助于提供具有尺寸精确性的腔穴。
根据实施例，制造芯片组件的方法还包括在载体上提供附接材料。根据另一实施例，制造芯片组件的方法还包括在金属网格阵列上提供附接材料。附接材料可以是通过湿化学方法提供的。具体而言，附接材料可以是通过无电镀、电流电镀提供的。此外，附接材料可以是通过物理气相沉积提供的或者可以被提供为薄预成形件，这里只是举出了一些例子。根据实施例，附接材料层具有处于1μm到50μm的范围内(例如，处于1μm-20μm的范围内)的厚度。根据实施例，所述方法包括在载体上提供作为均匀层的附接材料。根据另一实施例，就成分、厚度中的至少一者而言，附接材料层是均匀的。
根据另一实施例，将金属网格阵列附接至载体包括通过附接材料将金属网格阵列附接至载体。换言之，附接材料可以用于将载体和金属网格阵列相互附接。
根据另一实施例，载体上的附接材料被分配为使得每个腔穴的底部包括附接材料。例如，在这样的实施例中，附接材料可以用于将至少一个电子芯片附接至其相关联的腔穴。根据实施例，针对每个腔穴，提供相关联的电子芯片。例如，在实施例中，在每个腔穴中放置单个电子芯片。
根据实施例，金属网格阵列包括附接材料层，并且提供金属网格阵列包括提供在其上具有附接材料层的金属网格阵列。
根据另一实施例，在至少一个腔穴中的每者中安装电子芯片包括在至少一个腔穴中的每者中安装在其上具有另一附接材料的电子芯片。
因而，如果在金属网格阵列上提供附接材料，那么电子芯片可以包括用于将处于相应腔穴中的电子芯片安装(附接)到载体的另一附接材料。另一附接材料可以具有与本文描述的附接材料相同的类型。具体而言，涉及电子芯片下方或之下的附接材料的任何实施例可以被视为包括另一实施例，其中，电子芯片下方或之下的“附接材料”是另一附接材料。根据实施例，另一附接材料的属性可以与针对附接材料所指定的一种或多种属性(例如，材料类型、层厚度等)等同。
根据实施例，金属网格阵列和电子芯片可以具有大致相等的厚度。如果附接材料被提供到金属网格阵列下方以及电子芯片下方，如果外部压力是通过平面压力施加表面施加的，那么通过金属网格阵列和电子芯片对附接材料施加的压力可以相等或者至少相似。此外，在该情况下，金属网格阵列之下和电子芯片之下的附接材料的形变也可以是等同或至少相似的。根据另一实施例，施加在芯片上的压力小于施加在金属网格阵列上的压力。这是通过芯片之上的有回弹力的按压工具部分和金属网格阵列之上的回弹力较差的按压工具部分而实现的。换言之，在实施例中，芯片之上的按压工具的回弹力低于金属网格阵列之上的按压工具的回弹力。根据另一实施例，施加在芯片上的压力小于施加在金属网格阵列上的压力，因为芯片的厚度小于金属网格阵列的厚度。典型的管芯厚度处于60μm到200μm的范围内，例如，处于60μm到110μm的范围内。根据另一实施例，所述厚度甚至更小，例如，大于20μm。根据另一实施例，所述厚度处于200μm和210μm之间，例如，等于或者小于205μm。具体而言，可以在批量级上执行将电子芯片和/或金属网格阵列附接在载体上。因此，例如，可以通过机械切割(例如，锯切)、蚀刻或者激光切割在批量级上对由芯片、载体和金属网格阵列的多重布置构成的结构、横向包围结构(金属网格阵列和载体)进行单个化。这允许以高吞吐量尤为高效地制造多个封装体。根据实施例，所述方法包括在将电子芯片安装到多个腔穴中之后使多个腔穴单个化。根据实施例，每个电子芯片是多个电子芯片之一。
根据实施例，将附接材料提供成载体上的附接材料层。具体而言，附接材料层在载体的区域之上具有基本上恒定的厚度。例如，根据实施例，附接材料层的厚度变化小于附接材料层的平均厚度的10％(或者小于5％)。
根据实施例，每个电子芯片包括安装表面。根据实施例，电子芯片的安装表面由金属构成。例如，根据实施例，电子芯片的安装表面是通过电子芯片的后侧金属化(又称为背侧金属化)提供的。根据实施例，安装表面包括金。根据另一实施例，安装表面是通过包括至少一层(例如，至少两层、或甚至至少三层)的金属化层堆叠体而提供的。根据实施例，金属化包括以下中的至少一种：铝(Al)、钛(Ti)、镍(Ni)、钒(V)、银(Ag)和铜(Cu)、或者这些金属中的一者或多者的至少一种合金。根据实施例，金属化为Al/TiNiV/Ag(4LBSM)层堆叠体。根据另一实施例，金属化为Ti/NiV/Ag层堆叠体。根据另一实施例，金属化是Al/Ti/Cu层堆叠体。根据另一实施例，附接材料包括金属，例如，可焊接金属。根据另一实施例，附接材料是焊料(例如，软焊料或者扩散焊料)或者烧结材料。根据另一实施例，附接材料包括锡(Sn)、锡合金、锑(Sb)、锑合金、银(Ag)、银合金、金(Au)和金合金(例如，金锡合金或者金银合金)中的至少一者。具体而言，烧结材料可以包括银(Ag)、铜(Cu)和/或锡(Sn)或其合金。根据实施例，附接材料包括银、铜、锡、锑和/或铟、和/或它们的合金作为烧结材料，或者包括铅-锡焊料、镍-金焊料、锡-银焊料、锡-铟焊料、锡-银-铜焊料(SAC＝Sn-Ag-Cu焊料)、钯-金焊料、镍-钯-金-银焊料中的至少一者作为焊料材料，特别是扩散焊料材料。根据实施例，以150μm的厚度提供烧结材料(作为附接材料)。
根据实施例，在芯片组件的制造方法中，安装电子芯片包括在所述至少一个腔穴内提供管芯附接液体并将电子芯片置于管芯附接液体中或者管芯附接膜上。根据实施例，在将电子芯片放置于腔穴中之前，将管芯附接液体提供在腔穴中。根据实施例，管芯附接液体是易挥发的非反应性液体，例如，有或没有其它添加剂的甲醇、乙醇、异丙醇或其混合物。根据实施例，管芯附接液体为基于碳氟化合物的流体。根据另一实施例，管芯附接液体是(例如)FC-43或者FC-70(市售产品)。根据实施例，在将管芯附接至腔穴之前，将管芯附接液体(或者管芯附接膜)从腔穴中去除。例如，去除管芯附接液体可以包括使管芯附接液体蒸发或者燃烧。例如，在实施例中，提供管芯附接液体表面，其用于使电子芯片保持在腔穴中，直到电子芯片附接至芯片基底为止(例如，直到具有芯片基底和电子芯片的芯片组件受到(例如)热管芯附接工艺的加热和/或压力为止)。然而，将电子芯片放置在腔穴中并且使电子芯片附接至芯片基底也可以是在没有管芯附接液体的情况下执行的(一般没有要在将电子芯片附接至芯片基底之前被去除的任何中间附接材料)。
根据实施例，将电子芯片安装到相关联的腔穴中的芯片基底包括在高温下(例如，在超过室温的温度下)将电子芯片(位于相关联的腔穴中)和载体朝向彼此按压，所述温度例如是足以形成热力学稳定的金属间相的温度，所述温度例如是足以形成扩散焊料互连(例如，铜-锡-铜(Cu-Sn-Cu)互连或者金-锡-铜(Au-Sn-Cu)互连)的温度，例如，所述温度是处于200℃和400℃之间的范围内的温度。
根据实施例，将电子芯片安装到相关联的腔穴中的芯片基底包括在高温下(例如，在足以形成软焊料互连或者烧结互连的温度下)将电子芯片(位于相关联的腔穴中)和载体朝向彼此按压。
根据实施例，将电子芯片安装至芯片基底包括在高温下将电子芯片和金属网格阵列两者(一方面)与载体(另一方面)朝向彼此按压。根据实施例，使电子芯片和芯片基底经受加热和/或压力包括使电子芯片和芯片基底经受加热和/或压力，以便在电子芯片和载体之间形成第一扩散焊料互连，并且在金属网格阵列和载体之间形成第二扩散焊料互连。因而，根据实施例，电子芯片到载体的附接以及金属网格阵列到载体的附接是在公共处理步骤中执行的，所述步骤可以包括使芯片组件经受加热和/或压力。
根据实施例，金属网格阵列是受到冲压的金属薄板。换言之，根据实施例，金属网格阵列的至少一个开口是通过冲压形成的。然而，也可以设想其它用于提供开口的方法，例如，切割，例如，激光切割等。
根据实施例，载体包括金属。根据实施例，金属网格阵列是由金属薄板构成的。薄板金属或者金属薄板又可以被称为金属箔。
根据另一实施例，载体和金属网格阵列中的至少一者包括铜或铜合金。根据另一实施例，载体和金属网格阵列中的至少一者包括具有涂覆层的铜(或者铜合金)。根据实施例，涂层包括镍或镍磷。根据另一实施例，载体包括处于在上面提供附接材料的表面上的金属层。根据实施例，载体是引线框架。根据另一实施例，载体是印刷电路板(PCB)。根据另一实施例，载体是如上文所述的直接铜接合(DCB)。
根据实施例，在垂直于金属网格阵列的前表面的方向上，安装在腔穴中的电子芯片的前表面与金属网格阵列的前表面间隔开金属网格阵列的厚度的10％或更低(或者，在另一实施例中为5％或更低，或甚至1％或更低)，其中，金属网格阵列的前表面背离载体，并且所安装的电子芯片的前表面背离载体。根据实施例，金属网格阵列的厚度处于20μm到250μm的范围内，例如，处于20μm到110μm的范围内。根据另一实施例，金属网格阵列的厚度处于60μm到110μm的范围内，例如，为100μm。例如，对于100微米(μm)的金属网格阵列厚度而言，所安装的电子芯片的前表面在垂直于金属网格阵列的前表面的方向上与金属网格阵列的前表面间隔开10μm或更低。
金属网格阵列和所安装的电子芯片的这种基本上水平的前表面具有如下优点：包括电绝缘层和至少一个导电层的层合物更易于被布置在金属网格阵列和所安装的电子芯片的前表面之上。此外，在层合物中生成通往电子芯片的表面和金属网格阵列的表面的接触孔不需要调整孔生成激光束在射束方向上的聚焦位置。
根据实施例，载体和金属网格阵列中的至少一者包括至少一个对准元件，其用于将载体和金属网格阵列相对于彼此对准和/或固定。相应地，在实施例中，所述方法包括将载体和金属网格阵列相对于彼此对准。根据另一实施例，至少一个对准元件包括对准引脚、突起、凹槽、孔等中的至少一个。至少一个对准元件可以包括配合对准元件，例如，处于载体和金属网格阵列之一中的对准引脚以及处于载体和金属网格阵列中的另一个中的引脚容纳凹陷。
在上文中已经描述并且在下文还将参考芯片组件及其制造方法描述本文公开的主题的示例性实施例。应当指出，与本文公开的主题的不同方面有关的特征的任何组合当然也是可能的。具体而言，一些特征已经或者将参考器件类型实施例予以描述，而其它特征已经或将参考方法类型实施例予以描述。然而，从上文和下文的描述可以理解，除非另行指出，否则除了属于一个方面的特征的任何组合之外，涉及不同方面或实施例的特征的任何组合，甚至例如器件类型实施例的特征与方法类型实施例的特征的组合也被视为随本申请得到公开。就此而言，应当理解，可以从对应的明确公开的器件特征导出的任何方法特征应当基于器件特征的相应功能，并且不应被认为局限于结合器件特征所公开的器件特定的要素。此外，应当理解，可从对应的明确公开的方法特征导出的任何器件特征可以借助于本文公开的或者本领域已知的任何适当器件特征、基于所述方法中描述的相应功能来实现的。
结合附图根据以下描述和所附权利要求，本文公开的主题的上述和其它目的、特征和优点将变得显而易见，在附图中，类似的部分或要素由类似的附图标记表示。
附图说明
附图被包括以提供对本文公开的主题的示例性实施例的进一步理解，并且构成了说明书的部分。具体而言，附图示出了本文公开的主题的实施例的示例性组合。
在附图中：
图1到图6示出了根据本文公开的主题的实施例的在图6中所示的芯片组件的制造期间获得的结构的截面图。
图7以更多的细节示出了图6的芯片组件100的部分。
图8示出了根据本文公开的主题的实施例的处于替代的制造阶段中的芯片组件100。
图9到图11示出了在芯片组件的制造期间获得的结构的截面图，其是图2到图4中所示的制造的替代物。
具体实施方式
附图中的图示只是示意性的而未必是按比例绘制的。
在参考附图更加详细地描述示例性实施例之前，将对开发示例性实施例所基于的一些一般考虑事项加以总结。
图1到图6示出了根据本文公开的主题的实施例的在图6中所示的芯片组件的制造期间获得的结构的截面图。
图1示出了根据本文公开的主题的实施例的芯片组件100的部分。
根据实施例，提供芯片组件100的载体102，并且在载体102上提供附接材料104层，例如，锡层、锡合金层、银层、银合金层、金层或者金合金层，例如，金-锡合金层或者金-银合金层。根据实施例，载体102是引线框架，例如，铜引线框架，根据实施例，其可以涂覆有(或者部分地涂覆有)诸如镍或镍磷的涂覆材料。在其它实施例中，载体102是DCB或者PCB。根据实施例，通过镀敷将附接材料104层提供在载体102上。
图2示出了根据本文公开的主题的实施例的处于另一制造阶段的芯片组件100。
根据实施例，在载体102之上提供金属网格阵列106。根据实施例，在附接材料104层上提供金属网格阵列106。根据实施例，在载体102上提供作为均匀层的附接材料104。可以通过例如湿化学方法、电镀、无电镀、物理气相沉积、化学气相沉积等的任何适当工艺来施加附接材料。
替代地(如图2所示)，还可以在金属网格阵列106上提供附接材料104。然而，这具有如下缺点：在金属网格阵列的开口区域中的载体上可能需要另外的附接材料。根据实施例，金属网格阵列106是金属箔，并且包括多个开口108。根据实施例，金属网格阵列106是受到冲压的铜箔。
图3示出了根据本文公开的主题的实施例的处于另一制造阶段的芯片组件100。
根据实施例，金属网格阵列106通过附接材料104附接至载体102。此外，还在由载体102和金属网格阵列106限定的腔穴112的底部110上提供附接材料104。根据实施例，底部110由载体102形成。根据实施例，载体102和金属网格阵列106是芯片基底113的部分。
进一步地，根据实施例，在处于腔穴112的底部110上的附接材料104上提供管芯附接液体114。
图4示出了根据本文公开的主题的实施例的处于另一制造阶段的芯片组件100。
根据实施例，多个电子芯片116(图4示出了其中的两个)被放置于相关联的腔穴112中的管芯附接液体114上。
图5示出了根据本文公开的主题的实施例的处于另一制造阶段的芯片组件100。
根据实施例，作为多个电子芯片的部分的电子芯片116已经被放置在腔穴112中的每者中，腔穴112由载体102和金属网格阵列106限定。
根据实施例，芯片组件100被放置于按压工具118中且在第一按压部分120和第二按压部分122之间。根据实施例，由箭头124指示的力被施加到芯片组件100上，所述力具有至少1牛顿每平方毫米(N/mm2)的值。根据实施例，所述力处于1N/mm2和100N/mm2之间的范围内，例如，处于1N/mm2和20N/mm2之间的范围内。根据另一实施例，芯片组件100例如在温度超过所施加的附接材料104的熔化温度的回流炉中经受由图5中的箭头126指示的高温，即加热。根据实施例，(至少一个)芯片和金属网格阵列在载体上的附接产生了正面物质连结(positive substance jointing)(德语：stoffschlüssige Verbindung)。
根据实施例，通过将芯片组件加热126到第一温度，管芯附接液体114从腔穴112中蒸发，特别是被蒸发到在腔穴中没有残留。在另一实施例中，不使用管芯附接液体等。换言之，在实施例中，芯片被直接放置于附接材料上(其间没有任何其它材料)。
根据实施例，还在处于金属网格阵列和芯片之间的横向空间中提供附接材料。例如，根据实施例，通过对芯片施加压力并且因而对附接材料施加压力，附接材料的部分被按压到金属网格阵列和芯片之间的空间中。可以从附接材料在金属网格阵列的表面和/或芯片上的均等分布(例如，从开口的拐角附近的附接材料的均等分布)看到附接材料的均匀厚度和/或作用于芯片的均匀压力。
此外，根据实施例，芯片组件100的温度被升高到适于通过附接材料104将芯片116附接至载体102和/或金属网格阵列106的第二温度。例如，如果附接材料104是包括(例如)银(Ag)、锡(Sn)和铜(Cu)中的至少一者的烧结材料，那么第二温度被选择为使得烧结过程发生并且在预期时间段内完成。如果(例如)附接材料104是软焊料材料，那么第二温度被选择为使得软焊料材料液化。如果(例如)附接材料104是扩散焊料材料，那么第二温度被选择为使得扩散焊料材料在预期时间段内形成预期的金属间相。
图6示出了根据本文公开的主题的实施例的处于另一制造阶段的芯片组件100。
具体而言，取决于所使用的附接材料，至少在使芯片组件100冷却到室温之后，芯片组件100包括位于通过第一部分102和第二部分106限定的腔穴中并且附接至芯片基底113的多个电子芯片116。
图7以更多的细节示出了图6的芯片组件100的部分。
根据实施例，电子芯片116是功率半导体器件，其包括第一负载电极130和第二负载电极132。例如，根据实施例，功率半导体器件是二极管。根据另一实施例，功率半导体器件是晶体管，其还包括用于控制第一负载电极130和第二负载电极132之间的导电性的栅电极(图7中未示出)。
根据实施例，在芯片组件100之上提供层合物134以形成封装体。层合物134可以包括至少一个电绝缘层136和至少一个导电层138的堆叠体，例如，如图7所示。根据实施例，层合物134，例如，其绝缘层(例如，绝缘层136)包括延伸至负载电极130、132的通孔140。通过提供层合物的导电层138(例如，铜层)，利用导电层的材料填充通孔140，从而在导电层138和负载电极130、132之间建立电接触。根据实施例，通过镀敷提供导电层138。根据另一实施例，层合物134是预成形中间元件，该元件在被施加至电子芯片116和芯片基底113时包括至少一个电绝缘层136和至少一个导电层138。在这样的情况下，利用导电材料填充通孔与提供导电层是分开的。
根据实施例，附接材料104可以延伸到电子芯片116和芯片基底113之间的横向空间128中。换言之，在实施例中，附接材料104延伸到电子芯片116和金属网格阵列106之间的空间128中。
进一步地，图7指示了可能的单个化线，可以沿所述线对芯片组件100进行单个化。根据实施例，单个化线142延伸穿过金属网格阵列106，例如，如图7所示。
图8示出了根据本文公开的主题的实施例的处于替代的制造阶段的芯片组件100。
根据实施例，不使用管芯附接液体，即，在相关联的腔穴112中，电子芯片116被直接放置于附接材料104上，其间没有中间材料。除去该特征，图8对应于图4。
图9到图11示出了在芯片组件的制造期间获得的结构的截面图，其是图2到图4中所示的制造的替代物。
具体而言，图9到图11所示的制造方法与图2到图4的区别特别在于，附接材料104层被提供在金属网格阵列106上。此外，根据实施例，附接材料104被提供在电子芯片116上，以允许将电子芯片附接在腔穴112中的载体102上。
图11中所示的结构可以被进一步处理，如联系图5和图6所图示和描述的。
应当指出，术语“包括”不排除其它元件或特征，并且“一”不排除复数个。此外，术语“包括”含有“特别包括”的含义以及“由……构成”的含义。换言之，术语“包括铜”含有“特别包括铜”和“由铜构成”的含义。也可以使与不同实施例相关联描述的元件组合。还应当指出，附图标记不被解释为限制权利要求的范围。此外，本申请的范围并非旨在局限于说明书中描述的过程、机器、制造、物质的成分、手段、方法和步骤的特定实施例。相应地，所附权利要求旨在将这种过程、机器、制造、物质的成分、手段、方法或步骤包括在其范围内。

Claims (28)

1.一种制造芯片组件(100)的方法，所述方法包括：
提供载体(102)；
在所述载体(102)上提供附接材料(104)的连续层，其中，所述附接材料包括焊料材料或烧结材料；
提供金属网格阵列(106)，所述金属网格阵列(106)包括至少一个开口(108)；
通过所述附接材料(104)将所述金属网格阵列(106)附接到所述载体(102)，其中，所述金属网格阵列(106)和所述载体(102)限定了至少一个腔穴(112)，所述至少一个腔穴(112)中的每者是由所述至少一个开口(108)之一和所述载体(102)形成的；
通过所述附接材料(104)将电子芯片(116)安装在所述至少一个腔穴(112)中的每者中，其中，所述附接材料的连续层在所述金属网格阵列(106)和所述电子芯片(116)下方延伸。
2.根据权利要求1所述的方法，其中，所述附接材料(104)包括银、铜、锡、锑和/或铟、和/或它们的合金作为所述烧结材料，或者包括铅-锡焊料、镍-金焊料、锡-银焊料、锡-铟焊料、锡-银-铜焊料、钯-金焊料、镍-钯-金-银焊料中的至少一者作为所述焊料材料，特别是扩散焊料材料。
3.根据前述权利要求中的任何一项所述的方法，其中，所述金属网格阵列(106)是冲压的金属箔(106)，其中，所述至少一个开口(108)是通过冲压形成的。
4.根据前述权利要求中的任何一项所述的方法，其中，所述载体(102)包括铜，特别是具有镍或镍磷的涂层的铜，特别是，其中，所述载体(102)是引线框架或直接铜接合。
5.根据前述权利要求中的任何一项所述的方法，其中，所述金属网格阵列(106)包括铜，特别是具有镍或镍磷的涂层的铜。
6.根据前述权利要求中的任何一项所述的方法，其中，安装所述电子芯片(116)包括：
在所述至少一个腔穴(112)中提供管芯附接液体(114)或管芯附接膜；以及
将所述电子芯片(116)放置于所述管芯附接液体(114)中或者所述管芯附接膜上。
7.根据前述权利要求中的任何一项所述的方法，其中，安装所述电子芯片(116)包括在处于200℃和400℃之间的范围内的温度下将所述电子芯片(116)和所述载体(102)朝向彼此按压。
8.根据前述权利要求中的任何一项所述的方法，其中，安装所述电子芯片(116)包括在处于200℃和400℃之间的范围内的温度下将所述电子芯片(116)和所述金属网格阵列(106)两者与所述载体(102)朝向彼此按压。
9.根据前述权利要求中的任何一项所述的方法，其中，所述电子芯片(116)包括面向朝向所述载体(102)的方向的安装表面。
10.根据前述权利要求中的任何一项所述的方法，还包括使所述载体(102)和所述金属网格阵列(106)相对于彼此对准。
11.根据前述权利要求中的任何一项所述的方法，还包括将层合物布置在所述电子芯片(116)之上。
12.根据前述权利要求中的任何一项所述的方法，其中，所述金属网格阵列包括多个开口(108)，因而所述金属网格阵列和所述载体限定了多个腔穴(112)，所述方法还包括：
在将所述电子芯片(116)安装在所述多个腔穴(112)中之后将所述多个腔穴单个化。
13.一种芯片组件(100)，包括：
载体(102)；
包括至少一个开口(108)的金属网格阵列(106)；
所述金属网格阵列(106)通过附接材料(104)附接至所述载体(102)，其中，所述附接材料包括焊料材料或烧结材料；
所述金属网格阵列(106)和所述载体(102)限定了至少一个腔穴(112)，所述至少一个腔穴(112)中的每者是由所述至少一个开口(108)之一和所述载体(102)形成的；以及
通过所述附接材料(104)安装在所述至少一个腔穴(112)中的每者中的电子芯片(116)，所述附接材料(104)形成处于所述金属网格阵列(106)和所述芯片(116)之下的连续层。
14.根据权利要求13所述的芯片组件(100)，还包括：所述附接材料(104)处于所述金属网格阵列(106)和所述芯片(116)之间的横向空间中。
15.根据权利要求13或权利要求14中的任何一项所述的芯片组件(100)，其中，所述载体(102)是引线框架、印刷电路板和直接铜接合之一。
16.根据权利要求13到15中的任何一项所述的芯片组件(100)，其中，所述金属网格阵列(106)是冲压的金属箔。
17.根据权利要求13到16中的任何一项所述的芯片组件(100)，其中，所述电子芯片(116)是功率半导体器件，特别是，其中，所述电子芯片(116)包括至少一个外侧金属化层。
18.根据权利要求13到17中的任何一项所述的芯片组件(100)，其中，所述附接材料(104)包括扩散焊料材料。
19.根据权利要求13到18中的任何一项所述的芯片组件(100)，其中，所述载体(102)和所述金属网格阵列(106)中的至少一者包括铜，特别是具有镍或镍磷的涂层的铜。
20.根据权利要求13到19中的任何一项所述的芯片组件(100)，其中
所述电子芯片(116)包括背离所述载体(102)的前表面；
所述金属网格阵列(106)包括背离所述载体(102)的前表面；并且所安装的电子芯片(116)的前表面和所述金属网格阵列(106)的前表面相对于彼此平齐。
21.根据权利要求13到20中的任何一项所述的芯片组件(100)，还包括布置在所述电子芯片(116)之上的层合物。
22.根据权利要求13到21中的任何一项所述的芯片组件(100)，所述载体(102)和所述金属网格阵列(106)中的至少一者包括至少一个对准元件，所述至少一个对准元件用于所述载体(102)和所述金属网格阵列(106)相对于彼此的对准和/或固定。
23.根据权利要求22所述的芯片组件(100)，其中，所述至少一个对准元件包括对准引脚、突起、凹槽和孔中的至少一者。
24.根据权利要求13到23中的任何一项所述的芯片组件(100)，其中，所述金属网格阵列包括多个开口(108)，因而所述金属网格阵列和所述载体限定了多个腔穴(112)。
25.一种制造芯片组件(100)的方法，所述方法包括：
提供载体(102)；
提供金属网格阵列(106)，所述金属网格阵列(106)包括至少一个开口(108)；
通过附接材料(104)将所述金属网格阵列(106)附接到所述载体(102)，其中，所述金属网格阵列(106)和所述载体(102)限定了至少一个腔穴(112)，所述至少一个腔穴(112)中的每者是由所述至少一个开口(108)之一和所述载体(102)形成的，其中，所述附接材料包括焊料材料或烧结材料；
将电子芯片(116)安装在所述至少一个腔穴(112)中的每者中。
26.根据权利要求25所述的方法，其中，所述金属网格阵列(106)包括所述附接材料的层，并且提供金属网格阵列(106)包括提供在其上具有所述附接材料的层的所述金属网格阵列(106)。
27.根据权利要求25或26所述的方法，其中，将电子芯片(116)安装在所述至少一个腔穴中的每者中包括将在其上具有另一附接材料的电子芯片(116)安装在所述至少一个腔穴中的每者中。
28.一种芯片组件(100)，包括：
载体(102)；
包括至少一个开口(108)的金属网格阵列(106)；
所述金属网格阵列(106)通过附接材料(104)附接至所述载体(102)，其中，所述附接材料包括焊料材料或烧结材料；
所述金属网格阵列(106)和所述载体(102)限定了至少一个腔穴(112)，所述至少一个腔穴(112)中的每者是由所述至少一个开口(108)之一和所述载体(102)形成的；以及
安装在所述至少一个腔穴(112)中的每者中的电子芯片(116)。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1616579A (zh) * 2003-09-18 2005-05-18 日东电工株式会社 半导体密封用树脂组成物
CN102054717A (zh) * 2009-11-10 2011-05-11 飞思卡尔半导体公司 半导体芯片栅格阵列封装及其制造方法
CN103681542A (zh) * 2012-09-04 2014-03-26 英飞凌科技股份有限公司 芯片封装和用于制作芯片封装的方法
CN106449421A (zh) * 2015-08-07 2017-02-22 新光电气工业株式会社 引线框、半导体装置以及引线框的制造方法
CN107424971A (zh) * 2016-04-29 2017-12-01 英飞凌科技股份有限公司 芯片载体上基于腔体的特征

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6838776B2 (en) * 2003-04-18 2005-01-04 Freescale Semiconductor, Inc. Circuit device with at least partial packaging and method for forming
DE10325559B3 (de) 2003-06-05 2004-12-09 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren und Vorrichtung zum Herstellen eines Systems mit einer an einer vorbestimmten Stelle einer Oberfläche eines Substrats aufgebrachten Komponente
US20080318054A1 (en) * 2007-06-21 2008-12-25 General Electric Company Low-temperature recoverable electronic component
US20080313894A1 (en) 2007-06-21 2008-12-25 General Electric Company Method for making an interconnect structure and low-temperature interconnect component recovery process
DE102008011153B4 (de) 2007-11-27 2023-02-02 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Verfahren zur Herstellung einer Anordnung mit mindestens zwei lichtemittierenden Halbleiterbauelementen
US7855439B2 (en) * 2008-08-28 2010-12-21 Fairchild Semiconductor Corporation Molded ultra thin semiconductor die packages, systems using the same, and methods of making the same
DE102011056700A1 (de) 2011-12-20 2013-06-20 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung von optoelektronischen Halbleiterbauteilen, Leiterrahmenverbund und optoelektronisches Halbleiterbauteil
ITMI20130473A1 (it) * 2013-03-28 2014-09-29 St Microelectronics Srl Metodo per fabbricare dispositivi elettronici
DE102014114982B4 (de) * 2014-10-15 2023-01-26 Infineon Technologies Ag Verfahren zum Bilden einer Chip-Baugruppe
CN107924890A (zh) * 2015-08-06 2018-04-17 奥斯兰姆奥普托半导体有限责任公司 电子装置
US11462669B2 (en) * 2017-03-17 2022-10-04 Sheetak, Inc. Thermoelectric device structures
US10410979B2 (en) * 2017-06-14 2019-09-10 Win Semiconductors Corp. Structure for reducing compound semiconductor wafer distortion

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1616579A (zh) * 2003-09-18 2005-05-18 日东电工株式会社 半导体密封用树脂组成物
CN102054717A (zh) * 2009-11-10 2011-05-11 飞思卡尔半导体公司 半导体芯片栅格阵列封装及其制造方法
CN103681542A (zh) * 2012-09-04 2014-03-26 英飞凌科技股份有限公司 芯片封装和用于制作芯片封装的方法
CN106449421A (zh) * 2015-08-07 2017-02-22 新光电气工业株式会社 引线框、半导体装置以及引线框的制造方法
CN107424971A (zh) * 2016-04-29 2017-12-01 英飞凌科技股份有限公司 芯片载体上基于腔体的特征

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