TW377495B - Method of manufacturing semiconductor memory cells and the same apparatus - Google Patents

Method of manufacturing semiconductor memory cells and the same apparatus

Info

Publication number
TW377495B
TW377495B TW086113459A TW86113459A TW377495B TW 377495 B TW377495 B TW 377495B TW 086113459 A TW086113459 A TW 086113459A TW 86113459 A TW86113459 A TW 86113459A TW 377495 B TW377495 B TW 377495B
Authority
TW
Taiwan
Prior art keywords
height
periphery
trench isolation
shallow trench
memory cells
Prior art date
Application number
TW086113459A
Other languages
English (en)
Inventor
Hideyuki Matsuoka
Shinichiro Kimura
Toshiaki Yamanaka
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of TW377495B publication Critical patent/TW377495B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
TW086113459A 1996-10-04 1997-09-17 Method of manufacturing semiconductor memory cells and the same apparatus TW377495B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26407596 1996-10-04

Publications (1)

Publication Number Publication Date
TW377495B true TW377495B (en) 1999-12-21

Family

ID=17398178

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086113459A TW377495B (en) 1996-10-04 1997-09-17 Method of manufacturing semiconductor memory cells and the same apparatus

Country Status (3)

Country Link
US (2) US6130449A (zh)
KR (1) KR100704244B1 (zh)
TW (1) TW377495B (zh)

Families Citing this family (70)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4167727B2 (ja) * 1995-11-20 2008-10-22 株式会社日立製作所 半導体記憶装置
JPH10135425A (ja) * 1996-11-05 1998-05-22 Hitachi Ltd 半導体集積回路装置およびその製造方法
JP3869089B2 (ja) * 1996-11-14 2007-01-17 株式会社日立製作所 半導体集積回路装置の製造方法
JP3749776B2 (ja) * 1997-02-28 2006-03-01 株式会社東芝 半導体装置
US6838320B2 (en) * 2000-08-02 2005-01-04 Renesas Technology Corp. Method for manufacturing a semiconductor integrated circuit device
JP3599548B2 (ja) * 1997-12-18 2004-12-08 株式会社日立製作所 半導体集積回路装置の製造方法
KR19990055776A (ko) * 1997-12-27 1999-07-15 김영환 반도체 소자의 미세콘택 형성방법
US6906370B1 (en) * 1998-04-09 2005-06-14 Infineon Technologies Ag Semiconductor component having a material reinforced contact area
JP2000156480A (ja) * 1998-09-03 2000-06-06 Hitachi Ltd 半導体集積回路装置およびその製造方法
DE69828968D1 (de) * 1998-09-25 2005-03-17 St Microelectronics Srl Verbindungsstruktur in mehreren Ebenen
JP3230667B2 (ja) * 1998-11-17 2001-11-19 日本電気株式会社 半導体装置の配線構造
JP4406945B2 (ja) * 1998-11-24 2010-02-03 ソニー株式会社 半導体記憶装置の製造方法
JP4322347B2 (ja) * 1999-03-15 2009-08-26 エルピーダメモリ株式会社 半導体装置およびその製造方法
US6404004B1 (en) * 1999-04-30 2002-06-11 Fujitsu Quantum Devices Limited Compound semiconductor device and method of manufacturing the same
JP2000332216A (ja) * 1999-05-18 2000-11-30 Sony Corp 半導体装置及びその製造方法
JP4807894B2 (ja) 1999-05-31 2011-11-02 ルネサスエレクトロニクス株式会社 半導体装置
JP2000349258A (ja) * 1999-06-08 2000-12-15 Mitsubishi Electric Corp メモリセル並びにその制御方法及び製造方法
JP4063450B2 (ja) * 1999-06-14 2008-03-19 エルピーダメモリ株式会社 半導体集積回路装置
KR100309077B1 (ko) * 1999-07-26 2001-11-01 윤종용 삼중 금속 배선 일 트랜지스터/일 커패시터 및 그 제조 방법
US6333225B1 (en) * 1999-08-20 2001-12-25 Micron Technology, Inc. Integrated circuitry and methods of forming circuitry
KR100335121B1 (ko) * 1999-08-25 2002-05-04 박종섭 반도체 메모리 소자 및 그의 제조 방법
US6159818A (en) * 1999-09-02 2000-12-12 Micron Technology, Inc. Method of forming a container capacitor structure
TW432689B (en) * 1999-10-18 2001-05-01 Taiwan Semiconductor Mfg Fabricating method of stacked capacitor
KR100343291B1 (ko) * 1999-11-05 2002-07-15 윤종용 반도체 장치의 커패시터 형성 방법
JP2001185614A (ja) * 1999-12-22 2001-07-06 Mitsubishi Electric Corp 半導体装置およびその製造方法
KR100333058B1 (ko) * 2000-03-09 2002-04-22 윤종용 반도체 메모리 장치의 캐패시터 하부전극 제조 방법 및 그구조
US6232168B1 (en) * 2000-08-25 2001-05-15 Micron Technology, Inc. Memory circuitry and method of forming memory circuitry
KR100338958B1 (ko) * 2000-08-31 2002-06-01 박종섭 반도체 소자의 커패시터 형성 방법
US6383868B1 (en) * 2000-08-31 2002-05-07 Micron Technology, Inc. Methods for forming contact and container structures, and integrated circuit devices therefrom
KR100338781B1 (ko) * 2000-09-20 2002-06-01 윤종용 반도체 메모리 소자 및 그의 제조방법
US6590255B2 (en) * 2000-09-29 2003-07-08 Kabushiki Kaisha Toshiba Semiconductor memory device having memory cell section and peripheral circuit section and method of manufacturing the same
US6350649B1 (en) * 2000-10-30 2002-02-26 Samsung Electronics Co., Ltd. Bit line landing pad and borderless contact on bit line stud with etch stop layer and manufacturing method thereof
JP2002231721A (ja) * 2001-02-06 2002-08-16 Mitsubishi Electric Corp 半導体装置
US6468858B1 (en) * 2001-03-23 2002-10-22 Taiwan Semiconductor Manufacturing Company Method of forming a metal insulator metal capacitor structure
JP3895126B2 (ja) * 2001-04-23 2007-03-22 株式会社東芝 半導体装置の製造方法
DE10127888A1 (de) * 2001-06-08 2002-12-19 Infineon Technologies Ag Verfahren zur Bildung von Kontaktregionen von in einem Substrat integrierten Bauelementen
US6475906B1 (en) * 2001-07-05 2002-11-05 Promos Technologies, Inc. Gate contact etch sequence and plasma doping method for sub-150 NM DT-based DRAM devices
US6642564B2 (en) * 2001-07-18 2003-11-04 Matsushita Electric Industrial Co., Ltd. Semiconductor memory and method for fabricating the same
DE10137678A1 (de) * 2001-08-01 2003-02-27 Infineon Technologies Ag Verfahren zur Herstellung eines Halbleiterprodukts mit einem Speicher- und einem Logikbereich
US6528367B1 (en) * 2001-11-30 2003-03-04 Promos Technologies, Inc. Self-aligned active array along the length direction to form un-biased buried strap formation for sub-150 NM BEST DRAM devices
JP3741053B2 (ja) * 2002-02-18 2006-02-01 ソニー株式会社 画像処理装置
US6809027B2 (en) * 2002-06-06 2004-10-26 International Business Machines Corporation Self-aligned borderless contacts
DE10229188A1 (de) * 2002-06-28 2004-01-29 Infineon Technologies Ag Verfahren zur Herstellung von Kontakten zu Teilen eines in einem Halbleitersubstrat integrierten Bauelementes
JP4037711B2 (ja) * 2002-07-26 2008-01-23 株式会社東芝 層間絶縁膜内に形成されたキャパシタを有する半導体装置
US7217601B1 (en) * 2002-10-23 2007-05-15 Massachusetts Institute Of Technology High-yield single-level gate charge-coupled device design and fabrication
JP4173374B2 (ja) * 2003-01-08 2008-10-29 株式会社ルネサステクノロジ 半導体装置の製造方法
JP3897730B2 (ja) * 2003-04-23 2007-03-28 松下電器産業株式会社 半導体記憶装置および半導体集積回路
US7675174B2 (en) * 2003-05-13 2010-03-09 Stmicroelectronics, Inc. Method and structure of a thick metal layer using multiple deposition chambers
JP4658486B2 (ja) * 2003-06-30 2011-03-23 ルネサスエレクトロニクス株式会社 半導体装置とその製造方法
KR20050051140A (ko) * 2003-11-27 2005-06-01 삼성에스디아이 주식회사 커패시터 및 이를 구비한 평판표시장치
KR100570060B1 (ko) * 2003-12-29 2006-04-10 주식회사 하이닉스반도체 반도체소자의 랜딩플러그콘택 형성 방법
JP4897201B2 (ja) * 2004-05-31 2012-03-14 ルネサスエレクトロニクス株式会社 半導体装置
JP4798979B2 (ja) * 2004-09-28 2011-10-19 Ｏｋｉセミコンダクタ株式会社 強誘電体メモリの製造方法
US7189613B2 (en) * 2005-02-23 2007-03-13 Taiwan Semiconductor Manufacturing Co., Ltd. Method and structure for metal-insulator-metal capacitor based memory device
JP2006245113A (ja) * 2005-03-01 2006-09-14 Elpida Memory Inc 半導体記憶装置の製造方法
DE102005052000B3 (de) * 2005-10-31 2007-07-05 Advanced Micro Devices, Inc., Sunnyvale Halbleiterbauelement mit einer Kontaktstruktur auf der Grundlage von Kupfer und Wolfram
JP4791191B2 (ja) * 2006-01-24 2011-10-12 富士通セミコンダクター株式会社 半導体装置及びその製造方法
JP2008042085A (ja) * 2006-08-09 2008-02-21 Matsushita Electric Ind Co Ltd 半導体記憶装置およびその製造方法
US20080116496A1 (en) * 2006-11-21 2008-05-22 Kuo-Chyuan Tzeng Integrating a DRAM with an SRAM having butted contacts and resulting devices
JP2008270277A (ja) * 2007-04-16 2008-11-06 Nec Electronics Corp 位置ずれ検出パターン、位置ずれ検出方法および半導体装置
JP4637872B2 (ja) * 2007-06-12 2011-02-23 シャープ株式会社 配線構造およびその製造方法
JP2009016596A (ja) * 2007-07-05 2009-01-22 Elpida Memory Inc 半導体装置及び半導体装置の製造方法
US8021974B2 (en) * 2009-01-09 2011-09-20 Internatioanl Business Machines Corporation Structure and method for back end of the line integration
WO2011158319A1 (ja) * 2010-06-14 2011-12-22 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US8586472B2 (en) 2010-07-14 2013-11-19 Infineon Technologies Ag Conductive lines and pads and method of manufacturing thereof
JP2015179727A (ja) * 2014-03-19 2015-10-08 ルネサスエレクトロニクス株式会社 半導体集積回路装置およびその製造方法
JP6359332B2 (ja) * 2014-05-09 2018-07-18 ルネサスエレクトロニクス株式会社 半導体装置
US10847651B2 (en) * 2018-07-18 2020-11-24 Micron Technology, Inc. Semiconductor devices including electrically conductive contacts and related systems and methods
US11626397B2 (en) 2020-08-28 2023-04-11 Sandisk Technologies Llc Gate material-based capacitor and resistor structures and methods of forming the same
US11322597B2 (en) * 2020-08-28 2022-05-03 Sandisk Technologies Llc Gate material-based capacitor and resistor structures and methods of forming the same

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2528731B2 (ja) * 1990-01-26 1996-08-28 三菱電機株式会社 半導体記憶装置およびその製造方法
JP2519569B2 (ja) * 1990-04-27 1996-07-31 三菱電機株式会社 半導体記憶装置およびその製造方法
JPH04342164A (ja) * 1991-05-20 1992-11-27 Hitachi Ltd 半導体集積回路装置の形成方法
JP2769664B2 (ja) * 1992-05-25 1998-06-25 三菱電機株式会社 半導体記憶装置およびその製造方法
DE4221432C2 (de) * 1992-06-30 1994-06-09 Siemens Ag Globales Planarisierungsverfahren für integrierte Halbleiterschaltungen oder mikromechanische Bauteile
JP3197064B2 (ja) * 1992-07-17 2001-08-13 株式会社東芝 半導体記憶装置
US5838038A (en) * 1992-09-22 1998-11-17 Kabushiki Kaisha Toshiba Dynamic random access memory device with the combined open/folded bit-line pair arrangement
JPH07142597A (ja) * 1993-11-12 1995-06-02 Mitsubishi Electric Corp 半導体記憶装置およびその製造方法
JP2682455B2 (ja) * 1994-07-07 1997-11-26 日本電気株式会社 半導体記憶装置およびその製造方法
JPH0855968A (ja) * 1994-08-10 1996-02-27 Hitachi Ltd 半導体集積回路装置の製造方法
JPH09107082A (ja) * 1995-08-09 1997-04-22 Hitachi Ltd 半導体集積回路装置の製造方法
JP2845176B2 (ja) * 1995-08-10 1999-01-13 日本電気株式会社 半導体装置
US5748521A (en) * 1996-11-06 1998-05-05 Samsung Electronics Co., Ltd. Metal plug capacitor structures for integrated circuit devices and related methods

Also Published As

Publication number Publication date
KR100704244B1 (ko) 2009-01-12
US6376304B1 (en) 2002-04-23
US6130449A (en) 2000-10-10
KR19980032540A (ko) 1998-07-25

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