DE69828968D1 - Verbindungsstruktur in mehreren Ebenen - Google Patents
Verbindungsstruktur in mehreren EbenenInfo
- Publication number
- DE69828968D1 DE69828968D1 DE69828968T DE69828968T DE69828968D1 DE 69828968 D1 DE69828968 D1 DE 69828968D1 DE 69828968 T DE69828968 T DE 69828968T DE 69828968 T DE69828968 T DE 69828968T DE 69828968 D1 DE69828968 D1 DE 69828968D1
- Authority
- DE
- Germany
- Prior art keywords
- connection structure
- several levels
- levels
- several
- connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP98830562A EP0989609B1 (de) | 1998-09-25 | 1998-09-25 | Verbindungsstruktur in mehreren Ebenen |
Publications (1)
Publication Number | Publication Date |
---|---|
DE69828968D1 true DE69828968D1 (de) | 2005-03-17 |
Family
ID=8236802
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69828968T Expired - Lifetime DE69828968D1 (de) | 1998-09-25 | 1998-09-25 | Verbindungsstruktur in mehreren Ebenen |
Country Status (3)
Country | Link |
---|---|
US (1) | US6815328B2 (de) |
EP (1) | EP0989609B1 (de) |
DE (1) | DE69828968D1 (de) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10034020A1 (de) * | 2000-07-07 | 2002-02-07 | Infineon Technologies Ag | Metallisierungsanordnung für Halbleiterstruktur und entsprechendes Herstellungsverfahren |
DE10142690A1 (de) * | 2001-08-31 | 2003-03-27 | Infineon Technologies Ag | Kontaktierung des Emitterkontakts einer Halbleitervorrichtung |
DE10305365B4 (de) * | 2003-02-10 | 2005-02-10 | Infineon Technologies Ag | Verfahren und Anordnung zum Kontaktieren von Anschlüssen eines Bipolartransistors |
JP3811473B2 (ja) * | 2003-02-25 | 2006-08-23 | 富士通株式会社 | 半導体装置 |
KR100549002B1 (ko) * | 2004-02-04 | 2006-02-02 | 삼성전자주식회사 | 복층 엠아이엠 커패시터를 갖는 반도체소자 및 그것을제조하는 방법 |
JP5172069B2 (ja) * | 2004-04-27 | 2013-03-27 | 富士通セミコンダクター株式会社 | 半導体装置 |
KR100809321B1 (ko) * | 2005-02-01 | 2008-03-05 | 삼성전자주식회사 | 다중 mim 캐패시터 및 이의 제조 방법 |
US7728390B2 (en) * | 2005-05-06 | 2010-06-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-level interconnection memory device |
CN102057390A (zh) * | 2008-06-03 | 2011-05-11 | 发现控股有限公司 | 管理保险方案的系统和方法 |
FR2935196B1 (fr) * | 2008-08-19 | 2011-03-18 | St Microelectronics Rousset | Circuit integre a dimensions reduites |
EP3007224A1 (de) * | 2014-10-08 | 2016-04-13 | Nxp B.V. | Metallisierung für Halbleiterbauelement |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5328553A (en) * | 1993-02-02 | 1994-07-12 | Motorola Inc. | Method for fabricating a semiconductor device having a planar surface |
KR0136684B1 (en) | 1993-06-01 | 1998-04-29 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
JP2845176B2 (ja) * | 1995-08-10 | 1999-01-13 | 日本電気株式会社 | 半導体装置 |
JP2785768B2 (ja) * | 1995-09-14 | 1998-08-13 | 日本電気株式会社 | 半導体装置の製造方法 |
US5834845A (en) * | 1995-09-21 | 1998-11-10 | Advanced Micro Devices, Inc. | Interconnect scheme for integrated circuits |
US5846876A (en) | 1996-06-05 | 1998-12-08 | Advanced Micro Devices, Inc. | Integrated circuit which uses a damascene process for producing staggered interconnect lines |
US5990507A (en) * | 1996-07-09 | 1999-11-23 | Kabushiki Kaisha Toshiba | Semiconductor device having ferroelectric capacitor structures |
US5854515A (en) * | 1996-07-23 | 1998-12-29 | Advanced Micro Devices, Inc. | Integrated circuit having conductors of enhanced cross-sectional area |
TW377495B (en) * | 1996-10-04 | 1999-12-21 | Hitachi Ltd | Method of manufacturing semiconductor memory cells and the same apparatus |
FR2754391B1 (fr) * | 1996-10-08 | 1999-04-16 | Sgs Thomson Microelectronics | Structure de contact a facteur de forme eleve pour circuits integres |
US5773314A (en) * | 1997-04-25 | 1998-06-30 | Motorola, Inc. | Plug protection process for use in the manufacture of embedded dynamic random access memory (DRAM) cells |
US5891799A (en) * | 1997-08-18 | 1999-04-06 | Industrial Technology Research Institute | Method for making stacked and borderless via structures for multilevel metal interconnections on semiconductor substrates |
US6239491B1 (en) * | 1998-05-18 | 2001-05-29 | Lsi Logic Corporation | Integrated circuit structure with thin dielectric between at least local interconnect level and first metal interconnect level, and process for making same |
US6165839A (en) * | 1998-06-08 | 2000-12-26 | Taiwan Semiconductor Manufacturing Company | Process to fabricate a cylindrical, capacitor structure under a bit line structure for a dynamic random access memory cell |
US6165880A (en) * | 1998-06-15 | 2000-12-26 | Taiwan Semiconductor Manufacturing Company | Double spacer technology for making self-aligned contacts (SAC) on semiconductor integrated circuits |
KR100267108B1 (ko) * | 1998-09-16 | 2000-10-02 | 윤종용 | 다층배선을구비한반도체소자및그제조방법 |
-
1998
- 1998-09-25 DE DE69828968T patent/DE69828968D1/de not_active Expired - Lifetime
- 1998-09-25 EP EP98830562A patent/EP0989609B1/de not_active Expired - Lifetime
-
2001
- 2001-10-24 US US10/001,625 patent/US6815328B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0989609A1 (de) | 2000-03-29 |
US6815328B2 (en) | 2004-11-09 |
EP0989609B1 (de) | 2005-02-09 |
US20020055249A1 (en) | 2002-05-09 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8332 | No legal effect for de |