TW201630185A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TW201630185A
TW201630185A TW104134882A TW104134882A TW201630185A TW 201630185 A TW201630185 A TW 201630185A TW 104134882 A TW104134882 A TW 104134882A TW 104134882 A TW104134882 A TW 104134882A TW 201630185 A TW201630185 A TW 201630185A
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region
dummy
gate
trench
electrode
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TW104134882A
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TWI575737B (zh
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妹尾賢
平林康弘
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豐田自動車股份有限公司
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Abstract

本發明是在於提供一種IGBT的ON電壓低，二極體的逆回復電流小的半導體裝置。具有半導體基板的半導體裝置，該半導體基板是具有形成於表面的閘極溝槽及虛擬溝槽。半導體基板是在閘極溝槽與虛擬溝槽之間具有射極領域、本體領域、阻障領域、及支柱領域。射極領域是接觸於閘極絕緣膜，且露出於表面的n型領域。本體領域是在射極領域的背面側接觸於閘極絕緣膜的p型領域。阻障領域是在本體領域的背面側接觸於閘極絕緣膜，且接觸於虛擬絕緣膜的n型的領域。支柱領域是被連接至表面電極，與阻障領域連繫的n型領域。

Description

半導體裝置 (關聯申請案的互相參照)
本申請案是2014年11月4日申請的日本專利申請案特願2014-224247的關聯申請案，根據此日本專利申請案主張優先權，並援用此日本專利申請案所記載的全部內容作為構成本說明書者。
本說明書是揭示有關兼有IGBT及二極體的機能之半導體裝置(RC-IGBT Reverse Conducting-Insulated Gate Bipolar Transistor)的技術。
在日本特開2013-48230號公報(以下稱為專利文獻1)中揭示有RC-IGBT。
此RC-IGBT是具備以n型射極領域、p型本體(body)領域、n型漂移領域、n型集極領域、溝槽式閘極(trench gate)電極等所構成的IGBT構造，其p型本體領域成為陽極領域，亦提供二極體構造。此RC-IGBT 是在兼用陽極領域的本體領域的下側形成有n型的阻障領域，且形成有連接該阻障(barrier)領域與表面電極(射極電極兼陽極電極)的n型的支柱領域。該支柱領域是形成鄰接的閘極溝槽間的間隔。此RC-IGBT是阻障領域的電位被維持於接近表面電極的電位的電位，因此藉由本體領域與阻障領域間的pn接合所構成的二極體難開啟。此二極體是在表面電極的電位更上昇時開啟。專利文獻1的RC-IGBT是利用阻障領域及支柱領域來抑制電洞從p型的本體領域流入至n型的阻障領域及n型的漂移領域，抑制二極體的逆回復電流。
在日本特開2008-21930號公報(以下稱為專利文獻2)中揭示有除了閘極溝槽以外還附加虛擬溝槽的半導體裝置。此半導體裝置是在鄰接的閘極溝槽間的間隔設置一對的虛擬溝槽。虛擬溝槽內的虛擬電極是與閘極溝槽內的閘極電極絕緣，被連接至源極電位。此半導體裝置是在閘極溝槽與虛擬溝槽間的間隔形成以p型本體領域及n型汲極領域所構成的pn二極體。並且，在一對的虛擬溝槽之間形成與漂移層連繫的同時蕭特基連接至表面電極(源極兼陽極電極)的n型領域。此半導體裝置是漂移領域與表面電極會藉由n型領域來蕭特基接觸，因此抑制pn二極體的逆回復電流。
專利文獻1的情況，需要在鄰接的閘極溝槽間的間隔形成支柱領域。一旦支柱領域被配置於接近閘極溝槽的位置，則二極體的特性會因被施加於閘極電極的電壓而容易變化，難以使二極體安定動作。因此，需要在支柱領域與閘極溝槽之間設置預定的間隔。如專利文獻1般，若在鄰接的閘極溝槽間的間隔配置支柱領域，則必須擴大鄰接的閘極溝槽之間的間隔。一旦擴大鄰接的閘極溝槽之間的間隔，則IGBT的特性會降低。溝槽式閘極型的IGBT是當開啟時電流會避開溝槽而流動，因此在鄰接的溝槽間的間隔，電洞濃度會變高。在溝槽間的間隔，電洞濃度變高之下，電子可低損失流動於其領域內，IGBT的ON電壓會被減低。以下，將在溝槽間的間隔儲存載流子之下IGBT的ON電壓減低的效應稱為載流子儲存效應。載流子儲存效應是溝槽間的間隔越窄越顯著。
專利文獻2的半導體裝置是蕭特基接觸於表面電極的n型領域會藉由虛擬溝槽來形成於從pn二極體分離的位置。亦即，蕭特基接觸的n型領域會形成於離開pn二極體的位置。因此，當pn二極體開啟時，無法充分地抑制電洞從pn二極體的p型領域流入n型領域(漂移領域)。因此，會有二極體的逆回復電流大的問題。
本說明書是揭示一種即使窄化鄰接的溝槽間的間隔，還是可使二極體安定動作之技術。亦即，揭示一 邊實現二極體的安定的動作，一邊改善IGBT的特性之技術。
本說明書所揭示的半導體裝置具備：半導體基板，其係於表面形成有閘極溝槽及虛擬溝槽；表面電極，其係被配置於半導體基板的表面；及背面電極，其係被配置於半導體基板的背面。
在閘極溝槽內配置有閘極絕緣膜、及藉由閘極絕緣膜來與半導體基板絕緣的閘極電極。
在虛擬溝槽內配置有虛擬絕緣膜、及藉由虛擬絕緣膜來與半導體基板絕緣，且自閘極電極電性分離的虛擬電極。
在半導體基板形成有下述的領域。
n型的射極領域：配置於閘極溝槽與虛擬溝槽之間，接觸於閘極絕緣膜，露出於半導體基板的表面。
p型的本體領域：配置於閘極溝槽與虛擬溝槽之間，在射極領域的背面側接觸於閘極絕緣膜。
p型的本體領域係兼用陽極領域。
n型的阻障領域：配置於閘極溝槽與虛擬溝槽之間，在本體領域的背面側接觸於閘極絕緣膜及虛擬絕緣膜。
n型的支柱領域：配置於閘極溝槽與虛擬溝槽之間，連接至表面電極，與阻障領域連繫。
n型的漂移領域：其係配置於比阻障領域更靠背面側，藉由阻障領域來從本體領域分離，n型雜質濃度比阻 障領域更低。
另外，亦可在阻障領域與漂移領域之間中介存在其他的領域。
p型的集極領域：露出於半導體基板的背面。
n型的陰極領域：露出於半導體基板的背面，n型雜質濃度比漂移領域更高。
上述的半導體裝置係藉由射極領域、本體領域、阻障領域、漂移領域、集極領域及閘極溝槽等來形成IGBT。又，藉由本體領域、阻障領域、漂移領域及陰極領域等來形成pn二極體。
此半導體裝置，在閘極溝槽與虛擬溝槽之間形成有構成pn二極體的pn接合(本體領域與阻障領域的境界)。並且，在閘極溝槽與虛擬溝槽之間形成有連接阻障領域與表面電極的支柱領域。與專利文獻2的情況不同，在藉由2個溝槽所區劃的1個範圍內形成有pn接合及支柱領域。亦即與pn接合鄰接而形成有支柱領域。因此，與專利文獻1的情況同樣，可有效地抑制電洞從pn二極體的p型領域(本體領域)流入n型領域(阻障領域及漂移領域)。因此，在此半導體裝置中，二極體的逆回復電流小。並且，在此半導體裝置中，區劃形成有前述pn接合及支柱領域的範圍之2個溝槽的其中一方為閘極溝槽，另一方為虛擬溝槽。由於虛擬溝槽內的虛擬電極是自閘極電極電性分離，因此虛擬電極的電位安定。所以，可將支柱領域配置於虛擬溝槽的附近，亦可使支柱領域接 觸於虛擬溝槽。亦即，不需要在支柱領域與虛擬溝槽之間設置寬的間隔。若根據此半導體裝置，則可一面抑制閘極電位影響支柱領域，一面使閘極溝槽與虛擬溝槽間的間隔形成比專利文獻1記載的鄰接的溝槽間的間隔更窄。藉由窄化溝槽間的間隔，可在IGBT的動作時充分地取得載流子儲存效應。因此，此半導體裝置的IGBT是ON電壓低。
10‧‧‧半導體裝置
12‧‧‧半導體基板
12a‧‧‧上面
12b‧‧‧下面
14‧‧‧溝槽
14a‧‧‧閘極溝槽
14b‧‧‧虛擬溝槽
14c‧‧‧中間位置
16‧‧‧閘極絕緣膜
18‧‧‧閘極電極
19‧‧‧閘極配線
20‧‧‧層間絕緣膜
22‧‧‧上部電極
26‧‧‧下部電極
30‧‧‧射極領域
32‧‧‧本體領域
34‧‧‧阻障領域
35‧‧‧支柱領域
38‧‧‧漂移領域
40‧‧‧集極領域
42‧‧‧陰極領域
44‧‧‧緩衝領域
56‧‧‧虛擬絕緣膜
58‧‧‧虛擬電極
59‧‧‧多晶矽配線
60‧‧‧接觸部
200‧‧‧半導體裝置
210‧‧‧中間領域
210a‧‧‧高濃度領域
210b‧‧‧低濃度領域
300‧‧‧半導體裝置
圖1是實施例1的半導體裝置10的縱剖面圖。
圖2是實施例1的半導體裝置10的上面圖(但只顯示說明所必要的要素)。
圖3是變形例的半導體裝置的上面圖(但只顯示說明所必要的要素)。
圖4是變形例的半導體裝置的上面圖(但只顯示說明所必要的要素)。
圖5是變形例的半導體裝置的縱剖面圖。
圖6是變形例的半導體裝置的縱剖面圖。
圖7是變形例的半導體裝置的縱剖面圖。
圖8是變形例的半導體裝置的縱剖面圖。
圖9是變形例的半導體裝置的上面圖(但只顯示說明所必要的要素)。
圖10是變形例的半導體裝置的上面圖(但只顯示說 明所必要的要素)。
圖11是變形例的半導體裝置的上面圖(但只顯示說明所必要的要素)。
圖12是變形例的半導體裝置的上面圖(但只顯示說明所必要的要素)。
圖13是變形例的半導體裝置的縱剖面圖。
圖14是實施例2的半導體裝置200的縱剖面圖。
圖15是實施例2的半導體裝置200的縱剖面圖(顯示與圖14同一剖面的圖)。
圖16是變形例的半導體裝置的上面圖(但只顯示說明所必要的要素)。
圖17是變形例的半導體裝置的上面圖(但只顯示說明所必要的要素)。
圖18是變形例的半導體裝置的上面圖(但只顯示說明所必要的要素)。
圖19是實施例3的半導體裝置300的縱剖面圖。
圖20是變形例的半導體裝置的縱剖面圖。
圖21是變形例的半導體裝置的上面圖(但只顯示說明所必要的要素)。
[實施例1]
圖1所示的實施例1的半導體裝置10是具備IGBT及二極體的RC-IGBT。半導體裝置10是具有藉由 Si所構成的半導體基板12。
在半導體基板12的上面12a是形成有上部電極22。上部電極22是藉由Al或AlSi所構成。或，上部電極22是亦可為在上面12a層疊Al(或AlSi)、Ti、Ni及Au的層疊電極。上部電極22的厚度是5~30μm程度。
在半導體基板12的下面12b是形成有下部電極26。下部電極26是亦可為在下面12b層疊Al(或AlSi)、Ti、Ni及Au的層疊電極。或，下部電極26是亦可為在下面12b層疊Ti、Ni及Au的層疊電極。下部電極26的厚度是1~30μm程度。
在半導體基板12的上面12a是形成有複數的溝槽14(14a、14b)。各溝槽14的深度是大致相等。各溝槽的深度是可設為4~6μm程度。複數的溝槽14之中的溝槽14a是在內部配置有閘極電極18的閘極溝槽。複數的溝槽14之中的溝槽14b是在內部配置有虛擬電極58的虛擬溝槽。如圖2所示般，閘極溝槽14a及虛擬溝槽14b是在上面12a彼此平行形成。閘極溝槽14a及虛擬溝槽14b是在上面12a交替配置。
如圖1所示般，各閘極溝槽14a的內面是藉由閘極絕緣膜16所覆蓋。在各閘極溝槽14a內是配置有閘極電極18。各閘極電極18是藉由閘極絕緣膜16來與半導體基板12絕緣。各閘極電極18的上面是藉由層間絕緣膜20所覆蓋。各閘極電極18是藉由層間絕緣膜20來與上部電極22絕緣。如圖2所示般，閘極電極18的長度 方向的端部是延伸至閘極配線19的下側。閘極電極18是經由未圖示的接觸部來電性連接至閘極配線19。
如圖1所示般，各虛擬溝槽14b的內面是藉由虛擬絕緣膜56所覆蓋。在各虛擬溝槽14b內配置有虛擬電極58。在虛擬溝槽14b內，虛擬電極58是藉由虛擬絕緣膜56來與半導體基板12絕緣。各虛擬電極58的上面是藉由層間絕緣膜20所覆蓋。在虛擬溝槽14b的上部，各虛擬電極58是藉由層間絕緣膜20來與上部電極22絕緣。但，如圖2所示般，在虛擬電極58的長度方向的端部是形成有多晶矽配線59及接觸部60。虛擬電極58是經由多晶矽配線59及接觸部60來電性連接至上部電極22。虛擬電極58是被連接至閘極電極18。亦即，虛擬電極58是對於閘極電極18在哪個的位置皆未導通，與閘極電極18電性分離。
在半導體基板12的內部是形成有射極領域30、本體領域32、阻障領域34、支柱領域35、漂移領域38、集極領域40及陰極領域42。射極領域30、本體領域32、阻障領域34及支柱領域35是被形成於閘極溝槽14a與虛擬溝槽14b之間的半導體領域(以下稱為晶格領域)。
射極領域30是含砷或磷作為雜質的n型的半導體領域。射極領域30是露出於半導體基板12的上面12a。射極領域30是對於上部電極22歐姆接觸。射極領域30是接觸於閘極絕緣膜16。射極領域30的n型雜質 濃度是1×1018~1×1021/cm3程度。射極領域30的厚度是0.2~1.5μm程度。
本體領域32是含硼作為雜質的p型的半導體領域。本體領域32是形成於射極領域30的側方及下側，接觸於射極領域30。本體領域32是在射極領域30的側方露出於半導體基板12的上面12a。本體領域32內的p型雜質濃度是在上部電極22的附近高，其他的領域低。本體領域32是對於上部電極22歐姆接觸。本體領域32是在射極領域30的下側接觸於閘極絕緣膜16。本體領域32的p型雜質濃度是1×1016~1×1019/cm3程度。本體領域32的厚度是0.2~5.0μm程度。
阻障領域34是含磷作為雜質的n型的半導體領域。阻障領域34是形成於本體領域32的下側，接觸於本體領域32。阻障領域34是在本體領域32的下側接觸於閘極絕緣膜16。阻障領域34是從接觸於閘極絕緣膜16的位置延伸至虛擬溝槽14b，接觸於虛擬絕緣膜56。阻障領域34是藉由本體領域32來從射極領域30分離。阻障領域34的n型雜質濃度是1×1015~1×1018/cm3程度。阻障領域34的厚度是0.2~3.0μm程度。
支柱領域35是含磷作為雜質的n型的半導體領域。支柱領域35是形成於本體領域32的側方，接觸於本體領域32。並且，支柱領域35是形成於與虛擬溝槽14b鄰接的位置。支柱領域35是從半導體基板12的上面12a沿著下方向(半導體基板12的厚度方向)來延伸至 阻障領域34。支柱領域35是在其深度範圍的大致全域接觸於虛擬絕緣膜56。藉由如此支柱領域35形成在接觸於虛擬絕緣膜56的位置，虛擬溝槽14b與閘極溝槽14a之間的間隔會變窄(亦即，比專利文獻1的RC-IGBT的閘極溝槽之間的間隔更窄)。支柱領域35的上端部是露出於半導體基板12的上面12a。支柱領域35是對於上部電極22蕭特基接觸。支柱領域35的下端是被連接至阻障領域34。亦即，支柱領域35是與阻障領域34連接。支柱領域35的n型雜質濃度是8×1013~1×1018/cm3程度。
漂移領域38是含磷作為雜質的n型的半導體領域。漂移領域38的n型雜質濃度是比阻障領域34的n型雜質濃度更低。漂移領域38是跨越複數的晶格領域的下側的領域延伸。漂移領域38是接觸於阻障領域34。漂移領域38是在阻障領域34的下側接觸於閘極絕緣膜16。漂移領域38是在阻障領域34的下側接觸於虛擬絕緣膜56。漂移領域38是藉由阻障領域34來從本體領域32分離。漂移領域38的厚度是80~165μm，漂移領域38的比電阻是40~100Ωcm程度。
集極領域40是含硼作為雜質的p型的半導體領域。集極領域40是形成於漂移領域38的下側，接觸於漂移領域38。集極領域40是露出於半導體基板12的下面12b。集極領域40是對於下部電極26歐姆接觸。集極領域40的p型雜質濃度是1×1015~1×1019cm3程度。集極領域40的厚度是0.2~3.0μm程度。
陰極領域42是含磷作為雜質的n型的半導體領域。陰極領域42是具有比漂移領域38、阻障領域34及支柱領域35的n型雜質濃度更高的n型雜質濃度。陰極領域42是形成於漂移領域38的下側，接觸於漂移領域38。陰極領域42是在與集極領域40鄰接的位置，露出於半導體基板12的下面12b。陰極領域42是對於下部電極26歐姆接觸。陰極領域42的n型雜質濃度是1×1018~1×1021cm3程度。陰極領域42的厚度是0.2~3.0μm程度。
在半導體基板12中，藉由射極領域30、本體領域32、阻障領域34、漂移領域38、集極領域40、閘極電極18及閘極絕緣膜16，形成被連接於上部電極22與下部電極26之間的IGBT。當IGBT動作時，上部電極22是作為IGBT的射極電極的機能，下部電極26是作為IGBT的集極電極的機能。並且，在半導體基板12中，藉由本體領域32、阻障領域34、漂移領域38及陰極領域42，形成被連接於上部電極22與下部電極26之間的pn二極體。當pn二極體動作時，上部電極22是作為pn二極體的陽極電極的機能，下部電極26是作為pn二極體的陰極電極的機能。在半導體基板12中，藉由支柱領域35、阻障領域34、漂移領域38及陰極領域42，形成被連接於上部電極22與下部電極26之間的蕭特基阻障二極體(以下稱為SBD)。當SBD動作時，上部電極22是作為SBD的陽極的機能，下部電極26是作為SBD的陰極的機能。
針對IGBT的動作進行說明。在使IGBT開啟(ON)時，比上部電極22更高的電位會被施加於下部電極26。一旦對閘極電極18施加臨界值以上的電位，則在閘極絕緣膜16附近的本體領域32形成通道。於是，電子會從上部電極22經由射極領域30、本體領域32的通道、阻障領域34、漂移領域38及集極領域40來朝下部電極26流動。又，電洞會從下部電極26經由集極領域40、漂移領域38、阻障領域34及本體領域32來朝上部電極22流動。在圖1中如箭號X1所示般，流動於漂移領域38內的電洞是避開閘極溝槽14a及虛擬溝槽14b而流動。因此，電洞會集中於漂移領域38內的閘極溝槽14a與虛擬溝槽14b之間的領域(在圖1中以虛線所示的領域)。在此，若假使閘極溝槽14a與虛擬溝槽14b之間的間隔擴大，則電洞的濃度變高的是僅以虛線所示的領域中的閘極溝槽14a及虛擬溝槽14b附近的領域。但，在半導體裝置10中，由於閘極溝槽14a與虛擬溝槽14b之間的間隔窄，因此在以虛線所示的領域全體中電洞的濃度會變高。所以，在虛線的領域內的漂移領域38，電阻會變極低，電子可低損失通過漂移領域38。如此，此半導體裝置10的IGBT是可充分地取得載流子儲存效應。因此，此IGBT的ON電壓低。並且，此半導體裝置10是閘極溝槽14a與虛擬溝槽14b會被交替地配置，在該等之間的各晶格領域內形成射極領域30及本體領域32。因此，在各晶格領域內，IGBT會動作，在各晶格領域的下部的漂移 領域38(亦即以虛線所示的領域)大致均等地儲存載流子。不會有只在特定的晶格領域的下部儲存載流子的情形，電流集中於特定的晶格領域的情形會被抑制。藉此，實現開關耐量的提升。
之後，一旦使閘極電極18的電位降低至未滿臨界值，則通道會消失，電流會停止。亦即，IGBT會關閉(OFF)。
其次，說明有關pn二極體及SBD的動作。在使pn二極體及SBD開啟時，在上部電極22與下部電極26之間施加上部電極22會成為高電位的電壓(順電壓)。以下，思考有關使上部電極22的電位從與下部電極26同等的電位慢慢地上昇的情況。一旦使上部電極22的電位上昇，則支柱領域35與上部電極22的界面的蕭特基接觸部會導通。亦即，SBD開啟。於是，電子會從下部電極26經由漂移領域38、阻障領域34及支柱領域35來朝上部電極22流動。一旦如此SBD開啟，則阻障領域34的電位會成為接近上部電極22的電位的電位。因此，在本體領域32與阻障領域34的境界的pn接合難產生電位差。因此，之後即使使上部電極22的電位上昇，暫時之間，pn二極體是不開啟。若使上部電極22的電位更上昇，則流至SBD的電流會增加。流至SBD的電流越增加，上部電極22與阻障領域34之間的電位差越大，在本體領域32與阻障領域34的境界的pn接合產生的電位差也變大。因此，若使上部電極22的電位上昇至預定的電 位以上，則pn二極體會開啟。亦即，電洞會從上部電極22經由本體領域32、阻障領域34、漂移領域38及陰極領域42朝下部電極26流動。又，電子會從下部電極26經由陰極領域42、漂移領域38、阻障領域34及本體領域32朝上部電極22流動。如此，半導體裝置10是在上部電極22的電位上昇時，SBD會先開啟，而pn二極體開啟的時機延遲。藉此，抑制電洞從本體領域32流入漂移領域38。
在pn二極體開啟後，若在上部電極22與下部電極26之間施加逆電壓(上部電極22成為低電位的電壓)，則pn二極體會進行逆回復動作。亦即，在pn二極體開啟時，是在漂移領域38內存在電洞。一旦逆電壓被施加，則漂移領域38內的電洞會通過本體領域32而被排出至上部電極22。藉由此電洞的流動，在pn二極體瞬間地產生逆電流。然而，半導體裝置10是在pn二極體開啟時，如上述般，藉由SBD抑制電洞從本體領域32流入漂移領域38。因此，在pn二極體進行逆回復動作時，存在於漂移領域38內的電洞少。所以，pn二極體的逆回復電流也小。如此，半導體裝置10是pn二極體的逆回復電流會被抑制。
另外，在SBD動作時，會有閘極電極18的電位變動的情況。通常SBD的特性是按照閘極電極18的電位而變動，但在半導體裝置10中因閘極電極18的電位的影響所造成SBD的特性的變動會被壓到最小限度。以 下，詳細說明。
當閘極電極18的電位高時，在本體領域32形成通道。SBD的動作時，若在本體領域32形成通道，則閘極絕緣膜16附近的阻障領域34的電位會成為接近上部電極22的電位的電位，在SBD的蕭特基接觸部(支柱領域35與上部電極22的接觸部)難產生電位差。只要閘極電極18的電位低，通道未被形成，則如此的現象不會產生。因此，為了SBD開啟所必要的順電壓是依閘極電極18的電位而變動。如此，在RC-IGBT中依閘極電極18的電位而二極體的特性變動的現象是被稱為閘極干涉。假若支柱領域35被形成於閘極溝槽14a的附近，則由於支柱領域35的下端部接近通道的下端部而配置，因此SBD是直接受到閘極干涉的影響。對於此，實施例1的半導體裝置10是支柱領域35會在晶格領域內形成於最遠離閘極溝槽14a的位置。因此，即使閘極絕緣膜16附近的阻障領域34的電位變動，支柱領域35的下端部的電位也不那麼變動。因此，SBD的特性難變動。如此，此半導體裝置10是SBD的特性不易因閘極干涉而變化。另外，在虛擬溝槽14b的周圍是通道未被形成，因此即使在虛擬溝槽14b的附近配置有支柱領域35，也不會產生閘極干涉的問題。
並且，閘極電極18的電位是對支柱領域35的電阻值也影響。亦即，若閘極電極18的電位變化，則從閘極電極18產生的電場會變化，支柱領域35中的載流 子的分布會變化。因此，支柱領域35的電阻是依閘極電極18的電位而變化。假若支柱領域35被形成於閘極溝槽14a的附近，則支柱領域35容易受到從閘極電極18產生的電場的影響。然而，在半導體裝置10中，支柱領域35是在晶格領域內形成於最離開閘極溝槽14a的位置。因此，在實施例的半導體裝置10中，支柱領域35是難受到從閘極電極18產生的電場的影響。因此，即使閘極電極18的電位變化，支柱領域35的電阻也幾乎不變化。另外，虛擬電極58的電位是被固定於上部電極22的電位，因此即使支柱領域35被配置於虛擬溝槽14b的附近，支柱領域35的電阻的變動的問題也不會產生。
如以上說明般，在此半導體裝置10中，因閘極電極18的電位變動的影響所造成SBD的特性變動會被壓到最小限度。
以下說明有關實施例1的半導體裝置10的變形例。在實施例1的半導體裝置10中，如圖2所示般，在看半導體基板12的上面12a時，支柱領域35是沿著虛擬溝槽14b來以一定的寬度連續地形成。然而，如圖3所示般，支柱領域35是亦可沿著虛擬溝槽14b來斷續地形成。又，如圖4所示般，支柱領域35的寬度是以可依位置而變化。
並且，在實施例1的半導體裝置10中，支柱領域35會在其深度範圍的全域接觸於虛擬絕緣膜56。然而，如圖5所示般，支柱領域35亦可形成於離開虛擬絕 緣膜56的位置。此情況，支柱領域35與虛擬絕緣膜56之間的間隔是儘可能窄為理想。例如，使支柱領域35與虛擬絕緣膜56之間的間隔形成比支柱領域35與閘極絕緣膜16之間的間隔更窄為理想。又，如圖6所示般，支柱領域35亦可在其深度範圍的一部分接觸於虛擬絕緣膜56。
並且，在實施例1的半導體裝置10中，虛擬電極58會在虛擬溝槽14b的長度方向的端部被電性連接至上部電極22。然而，如圖7、8所示般，亦可從虛擬電極58的上部除去層間絕緣膜20，使虛擬電極58在其上面連接至上部電極22。另外，圖7的例子是構成虛擬電極58的多晶矽會部分地形成於半導體基板12的上面12a上，在上面12a上，多晶矽與上部電極22會被連接。又，圖8的例子是構成虛擬電極58的多晶矽會只被形成於虛擬溝槽14b內，上部電極22會被連接至虛擬溝槽14b內的多晶矽。
並且，在實施例1的半導體裝置10中，支柱領域35對於上部電極22蕭特基接觸，但支柱領域35對於上部電極22亦可歐姆接觸。如此的構成中，藉由支柱領域35、阻障領域34、漂移領域38及陰極領域42所構成的電流路徑，不是SBD，而是作為被連接至上部電極22與下部電極26之間的電阻的機能。此情況也是在上部電極22的電位上昇時，電流會流至作為電阻機能的電流路徑，然後pn二極體會開啟，因此可使pn二極體開啟的 時機延遲。亦即，可抑制電洞流入漂移領域38。所以，此構成亦可抑制二極體的逆回復電流。
並且，在實施例1的半導體裝置10中，虛擬電極58是被電性連接至上部電極22。然而，虛擬電極58是亦可與上部電極22絕緣。亦即，虛擬電極58的電位是不被固定於上部電極22的電位，亦可為浮遊電位。
並且，在實施例1的半導體裝置10中，各閘極溝槽14a會條紋狀延伸。然而，如圖9、10所示般，亦可閘極溝槽14a格子狀延伸，虛擬溝槽14b形成於被閘極溝槽14a包圍的範圍內。即使如圖9、10般配置各領域，也可與實施例1同樣，IGBT及二極體動作。又，如圖11所示般，亦可組合配置條紋狀的虛擬溝槽14b與格子狀的閘極溝槽14a。
又，如圖12所示般，亦可形成有條紋狀的虛擬溝槽14b及格子狀的閘極溝槽14a。圖12是在被格子狀的閘極溝槽14a包圍的範圍內形成有射極領域30及支柱領域35(支柱領域35a)。在被格子狀的閘極溝槽14a包圍的範圍內是虛擬溝槽14b未被形成。支柱領域35a是形成於被格子狀的閘極溝槽14a包圍的範圍的中央。從支柱領域35a到閘極溝槽14a的距離是距離L1。虛擬溝槽14b是形成於被格子狀的閘極溝槽14a包圍的範圍的外側。在虛擬溝槽14b與閘極溝槽14a之間是形成有射極領域30及支柱領域35(支柱領域35b)。支柱領域35b是形成於離開虛擬溝槽14b的位置。支柱領域35b與虛擬溝 槽14b之間的距離是距離L2。支柱領域35b與閘極溝槽14a之間的距離是距離L3。距離L2是比距離L1短，比距離L3短。即使是如此的構成，也會因為支柱領域35b配置於虛擬溝槽14b的附近，所以可取得與上述的實施例1同樣的效果。
並且，在實施例1的半導體裝置10中，集極領域40與陰極領域42會接觸於漂移領域38。然而，如圖13所示般，亦可在漂移領域38的下側形成緩衝領域44。緩衝領域44是含磷作為雜質的n型領域。緩衝領域44是n型雜質濃度比漂移領域更高，比陰極領域42更低的n型領域。集極領域40及陰極領域42是形成於緩衝領域44的下側。集極領域40與陰極領域42會藉由緩衝領域44來從漂移領域38分離。緩衝領域44的n型雜質濃度是1×1015~1×1018/cm3程度。緩衝領域44的厚度是0.2~5.0μm程度。
[實施例2]
圖14所示的實施例2的半導體裝置200是具有p型的中間領域210的點與實施例1的半導體裝置10不同。實施例2的半導體裝置200的其他的構成是與實施例1的半導體裝置10相等。中間領域210是含硼作為雜質的p型領域。中間領域210是形成於阻障領域34與漂移領域38之間。中間領域210是形成於閘極溝槽14a與虛擬溝槽14b之間。中間領域210是在阻障領域34的下 側接觸於閘極絕緣膜16，在阻障領域34的下側接觸於虛擬絕緣膜56。阻障領域34會藉由中間領域210來從漂移領域38分離。中間領域210的p型雜質濃度是1×1015~1×1018/cm3程度。中間領域210的厚度是0.2~3.0μm程度。
中間領域210是具有p型雜質濃度高的高濃度領域210a、及p型雜質濃度低的低濃度領域210b。高濃度領域210a是形成在與中間領域210內的虛擬溝槽14b鄰接的位置。低濃度領域210b是形成在與中間領域210內的閘極溝槽14a鄰接的位置。因此，比閘極溝槽14a與虛擬溝槽14b之間的中間位置14c更靠虛擬溝槽14b側的中間領域210的p型雜質濃度的平均值要比中間位置14c更靠閘極溝槽14a側的中間領域210的p型雜質濃度的平均值更高。
另外，低濃度領域210b的p型雜質的平方面密度(在厚度方向積分中間領域210中的p型雜質濃度的值)是1×1012/cm2以上，高濃度領域210a的p型雜質的平方面密度是比低濃度領域210b的p型雜質的平方面密度更高的值(2×1012~1×1014/cm2程度)為理想。如此，若中間領域210的p型雜質的平方面密度為1×1012/cm2以上，則即使在半導體裝置200施加高電壓，也不會有中間領域210在厚度方向完全空乏化的情形。
說明有關半導體裝置200的IGBT的動作。在使IGBT開啟時，是在下部電極26施加比上部電極22更 高的電位。一旦在閘極電極18施加臨界值以上的電位，則在閘極絕緣膜16附近的本體領域32與中間領域210形成通道。於是，電子會從上部電極22經由射極領域30、本體領域32的通道、阻障領域34、中間領域210的通道、漂移領域38及集極領域40來朝下部電極26流動。並且，電洞會從下部電極26經由集極領域40、漂移領域38、中間領域210、阻障領域34及本體領域32來朝上部電極22流動。在實施例2的半導體裝置200也因為閘極溝槽14a與虛擬溝槽14b之間的間隔窄，所以可充分地取得載流子儲存效應。因此，此IGBT的ON電壓低。
之後，一旦使閘極電極18的電位降低至未滿臨界值，則通道會消失，電流會停止。亦即，IGBT會關閉。在實施例2的半導體裝置10中，IGBT關閉時的洩漏電流會被抑制。以下，詳細說明。在實施例1的半導體裝置10中，當IGBT關閉時，如圖1的箭號A1、A2所示般，有時洩漏電流會從漂移領域38經由阻障領域34及支柱領域35來朝上部電極22流動。相對於此，實施例2的半導體裝置200是在阻障領域34與漂移領域38之間形成有p型的中間領域210。由於漂移領域38與中間領域210的界面的pn接合會成為障壁，因此在實施例2的半導體裝置200中，洩漏電流會被抑制。但，即使如此設置中間領域210，還是會有洩漏電流越過中間領域210而流動的情況。如此的洩漏電流，通常是通過閘極絕緣膜16附近的中間領域210或虛擬絕緣膜56附近的中間領域210而 流動。在實施例2的半導體裝置200中，圖14的箭號A3所示的路徑是通過閘極絕緣膜16附近的中間領域210之洩漏電流的路徑，圖14的箭號A4所示的路徑是通過虛擬絕緣膜56附近的中間領域210而流動之洩漏電流的路徑。在箭號A4所示的路徑中，中間領域210(亦即高濃度領域210a)的p型雜質濃度會變高。因此，中間領域210與漂移領域38的界面的pn接合的障壁大。藉此，在箭號A4所示的路徑，洩漏電流難流動。並且，在箭號A3所示的路徑中，中間領域210(亦即低濃度領域210b)的p型雜質濃度會變低。這是因為在閘極絕緣膜16附近需要在IGBT開啟時形成通道，無法太提高中間領域210的p型雜質濃度。因此，在箭號A3所示的路徑中，中間領域210與漂移領域38的界面的pn接合的障壁小。然而，在箭號A3所示的路徑中，通過阻障領域34內的路徑長。由於阻障領域34是具有某程度的電阻，因此藉由通過阻障領域34內的路徑設置長，在箭號A3所示的路徑，洩漏電流難流動。
如以上所說明般，在實施例2的半導體裝置200中，藉由將支柱領域35配置於離開閘極溝槽14a的位置，拉長箭號A3所示的路徑，藉此抑制在箭號A3所示的路徑洩漏電流流動。又，藉由提高虛擬溝槽14b附近的中間領域210的p型雜質濃度，抑制在箭號A4所示的路徑洩漏電流流動。又，由於在虛擬溝槽14b附近未形成有通道，因此即使如此提高中間領域210的p型雜質濃 度，也不會特別產生問題。
並且，在實施例2的半導體裝置200中，當IGBT開啟時，在箭號A3、A4所示的路徑洩漏電流流動的情形也會被抑制。若在IGBT開啟時在箭號A3、A4所示的路徑電流流動，則恐有IGBT進行非預期的動作之虞，但在實施例2的半導體裝置200中可防止如此的動作。
其次，說明有關二極體的動作。由於中間領域210的厚度薄，中間領域210的p型雜質濃度沒那麼高，所以在SBD及pn二極體的動作時，電子及電洞是可越過中間領域210而流動。因此，在實施例2的半導體裝置200中，也與實施例1的半導體裝置10同樣，SBD及pn二極體動作。
在二極體的動作時流動於SBD的電流是如圖15的箭號A5、A6般容易通過閘極絕緣膜16附近及虛擬絕緣膜56的附近而流動。在此，如箭號A6所示般，若通過虛擬絕緣膜56的附近而流動的電流大，則在上部電極22與阻障領域34之間難產生電位差，pn二極體(亦即，本體領域32與阻障領域34的界面的pn接合)難必要以上開啟。對於此，在實施例2的半導體裝置200中，虛擬絕緣膜56附近的中間領域210(亦即高濃度領域210a)的p型雜質濃度會變高，藉此箭號A6所示的電流會被抑制。亦即，若虛擬絕緣膜56附近的中間領域210的p型雜質濃度高，則在此中間領域210與阻障領域34的界面 的pn接合中障壁會變大。因此，如箭號A6所示般流動的電流會被抑制。其結果，如箭號A5所示般流動的電流會變多，可在適當的時機使pn二極體開啟。
以上，說明有關實施例2的半導體裝置200。另外，對於實施例2的半導體裝置200，亦可適用與實施例1關聯說明的各種變形例的構成。
另外，在實施例2中，高濃度領域210a是形成於支柱領域35的正下面的範圍為理想，形成於比支柱領域35的正下面的範圍更廣的範圍更理想。例如，沿著虛擬溝槽14b來斷續地形成支柱領域35時，如圖16~17所示般，使在看半導體基板12的上面時的高濃度領域210a的範圍形成比支柱領域35的範圍更廣為理想。又，如圖18所示般，亦可將閘極溝槽14a與虛擬溝槽14b之間的大致全域設為高濃度領域210a，只將閘極溝槽14a的附近設為低濃度領域210b。
[實施例3]
圖19所示的實施例3的半導體裝置300是支柱領域35的構成與實施例1的半導體裝置10不同。實施例3的半導體裝置300的其他的構成是與實施例1的半導體裝置10相等。
在實施例3的半導體裝置300中，支柱領域35是具有：從阻障領域34往上方向延伸的第1部分35a、及從第1部分35a對於虛擬溝槽14b遠離的方向延 伸的第2部分35b。在第1部分35a的上端部是被層間絕緣膜20所覆蓋。第2部分35b的閘極溝槽14a側的端部是不被層間絕緣膜20所覆蓋，被蕭特基連接至上部電極22。
在實施例3的半導體裝置300中，第2部分35b的端部被連接至上部電極22，第1部分35a的上端部未被連接至上部電極22。因此，如圖19的箭號A7、A8所示般，洩漏電流的路徑會比實施例1的路徑(箭號A1、A2)更長。因此，可抑制洩漏電流。
另外，亦可思考拉長支柱領域35的深度方向的尺寸(亦即本體領域32的厚度)，藉此拉長洩漏電流的路徑。然後，若所欲形成如此的支柱領域35，則需要高能量離子注入，對半導體基板12產生損傷。像實施例3那樣藉由部分地在橫方向延長支柱領域35的表面部分，不用拉長支柱領域35的深度方向的尺寸，可提高洩漏電流的路徑的電阻。
以上，說明有關實施例3的半導體裝置300。另外，對於實施例3的半導體裝置300，亦可適用與實施例1關聯說明的各種變形例的構成。
另外，在使支柱領域35蕭特基接觸於上部電極22時，難以安定形成位障高。當此位障高低時，或使支柱領域35歐姆接觸於上部電極22時，像實施例3那樣藉由第2部分35b來抑制洩漏電流更有效。
並且，在實施例3中，虛擬電極58的上部是 被層間絕緣膜20所覆蓋。然而，亦可將虛擬電極58的上部直接連接至上部電極22。此情況，如圖20所示般，將構成虛擬電極58的多晶矽的一部分設在半導體基板12的上面12a上，於是可將虛擬電極58連接至上部電極22。又，藉由在上面12a上的多晶矽與支柱領域35的第1部分35a之間設置層間絕緣膜21，可防止第1部分35a被連接至上部電極22。
又，如圖21所示般，亦可在虛擬溝槽14b的旁邊部分地設置支柱領域35。此情況，在閘極溝槽14a的旁邊部分地設置射極領域30，在各溝槽的長度方向，將第2部分35b的位置從射極領域30的位置錯開為理想。若根據如此的構成，則可確保拉長射極領域30與第2部分35b之間的距離，可減少在IGBT產生閂鎖(Latch-up)的風險。
在以下說明有關本說明書所揭示的技術。另外，以下說明的技術事項分別為獨立有用者。
在本說明書所揭示的一例的半導體裝置中，支柱領域會接觸於虛擬絕緣膜。藉此，可更窄化閘極溝槽與虛擬溝槽的間隔。
在本說明書所揭示的一例的半導體裝置中，半導體基板是更具有：被配置在閘極溝槽與虛擬溝槽之間，阻障領域與漂移領域之間，連接至閘極絕緣膜，連接至虛擬絕緣膜之p型的中間領域。虛擬溝槽側的中間領域的p型雜質濃度的平均值要比閘極溝槽與虛擬溝槽之間的 中間位置更高，閘極溝槽側的中間領域的p型雜質濃度的平均值要比中間位置更高。若根據如此的構成，則可抑制漏電流通過虛擬溝槽的側面附近，從漂移領域往支柱領域流動。
支柱領域是具有：從阻障領域往表面的方向延伸的第1部分、及從第1部分對於虛擬溝槽遠離的方向延伸的第2部分，第2部分會被連接至表面電極，第1部分的表面側的端部未被連接至表面電極。若根據如此的構成，則可拉長流動於支柱領域的電流的路徑。藉此，可抑制經由支柱領域流動的漏電流。
以上，詳細說明本發明的具體例，但該等只不過是舉例說明，並非限定申請專利範圍者。在申請專利範圍中記載的技術是包含將以上舉例說明的具體例予以各種變形、變更者。
在本說明書或圖面說明的技術要素是單獨或藉由各種的組合來發揮技術的有用性者，並非限於申請時請求項記載的組合。並且，在本說明書或圖面舉例說明的技術是同時達成複數目的者，達成其中一個目的本身具有技術的有用性。
10‧‧‧半導體裝置
12‧‧‧半導體基板
12a‧‧‧上面
12b‧‧‧下面
14a‧‧‧閘極溝槽
14b‧‧‧虛擬溝槽
16‧‧‧閘極絕緣膜
18‧‧‧閘極電極
20‧‧‧層間絕緣膜
22‧‧‧上部電極
26‧‧‧下部電極
30‧‧‧射極領域
32‧‧‧本體領域
34‧‧‧阻障領域
35‧‧‧支柱領域
38‧‧‧漂移領域
40‧‧‧集極領域
42‧‧‧陰極領域
56‧‧‧虛擬絕緣膜
58‧‧‧虛擬電極

Claims (5)

  1. 一種半導體裝置，其特徵係具有：半導體基板，其係於表面形成有閘極溝槽及虛擬溝槽；表面電極，其係被配置於前述半導體基板的前述表面；及背面電極，其係被配置於前述半導體基板的背面，在前述閘極溝槽內配置有閘極絕緣膜、及藉由前述閘極絕緣膜來與前述半導體基板絕緣的閘極電極，在前述虛擬溝槽內配置有虛擬絕緣膜、及藉由前述虛擬絕緣膜來與前述半導體基板絕緣，且自前述閘極電極電性分離的虛擬電極，前述半導體基板係具有：n型的射極領域，其係配置於前述閘極溝槽與前述虛擬溝槽之間，接觸於前述閘極絕緣膜，露出於前述表面；p型的本體領域，其係配置於前述閘極溝槽與前述虛擬溝槽之間，在前述射極領域的背面側接觸於前述閘極絕緣膜；n型的阻障領域，其係配置於前述閘極溝槽與前述虛擬溝槽之間，在前述本體領域的背面側接觸於前述閘極絕緣膜及前述虛擬絕緣膜；n型的支柱領域，其係配置於前述閘極溝槽與前述虛擬溝槽之間，連接至前述表面電極，與前述阻障領域連繫； n型的漂移領域，其係配置於比前述阻障領域更靠背面側，藉由前述阻障領域來從前述本體領域分離，n型雜質濃度比前述阻障領域更低；p型的集極領域，其係露出於前述背面；及n型的陰極領域，其係露出於前述背面，n型雜質濃度比前述漂移領域更高。
  2. 如申請專利範圍第1項之半導體裝置，其中，前述支柱領域接觸於前述虛擬絕緣膜。
  3. 如申請專利範圍第1或2項之半導體裝置，其中，前述半導體基板更具有：被配置於前述閘極溝槽與前述虛擬溝槽之間且前述阻障領域與前述漂移領域之間，接觸於前述閘極絕緣膜及前述虛擬絕緣膜之p型的中間領域，比前述閘極溝槽與前述虛擬溝槽之間的中間位置更靠前述虛擬溝槽側的前述中間領域的p型雜質濃度的平均值要比比前述中間位置更靠前述閘極溝槽側的前述中間領域的p型雜質濃度的平均值更高。
  4. 如申請專利範圍第1~3項中的任一項所記載之半導體裝置，其中，前述支柱領域具有：在從前述阻障領域往前述表面的方向延伸的第1部分、及在從前述第1部分對於前述虛擬溝槽遠離的方向延伸的第2部分，前述第2部分被連接至前述表面電極，前述第1部分的表面側的端部未被連接至前述表面電極。
  5. 如申請專利範圍第1~4項中的任一項所記載之半導體裝置，其中，在與前述半導體基板的前述表面正交的剖 面中，前述閘極溝槽與前述虛擬溝槽係交替重複配置。
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