TW201138062A - Stacked die assembly having reduced stress electrical interconnects - Google Patents
Stacked die assembly having reduced stress electrical interconnects Download PDFInfo
- Publication number
- TW201138062A TW201138062A TW099137634A TW99137634A TW201138062A TW 201138062 A TW201138062 A TW 201138062A TW 099137634 A TW099137634 A TW 099137634A TW 99137634 A TW99137634 A TW 99137634A TW 201138062 A TW201138062 A TW 201138062A
- Authority
- TW
- Taiwan
- Prior art keywords
- die
- assembly
- support
- pad
- interconnect
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/2401—Structure
- H01L2224/24011—Deposited, e.g. MCM-D type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/2405—Shape
- H01L2224/24051—Conformal with the semiconductor or solid-state device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/76—Apparatus for connecting with build-up interconnects
- H01L2224/7615—Means for depositing
- H01L2224/76151—Means for direct writing
- H01L2224/76155—Jetting means, e.g. ink jet
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/821—Forming a build-up interconnect
- H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
- H01L2224/82102—Forming a build-up interconnect by additive methods, e.g. direct writing using jetting, e.g. ink jet
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06551—Conductive connections on the side of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Description
201138062 六、發明說明: 本申請案根據S.麥葛雷斯等人於2009年1 1月4日所提 出,名稱爲“具有應力減少之電互連之堆疊晶粒總成”之美 國暫時申請案第61 /2 80,584號,其藉由參考倂提於此。 【發明所屬之技術領域】 本發明係有關半導體晶粒對支撐中電路之電連接,特 別是有關電互連晶粒堆疊對支撐中電路之電連接。 【先前技術】 典型半導體晶粒具有形成有積體電路之前“主動”側、 後側及側壁。側壁於前緣銜接前側,於後緣銜接後側。半 導體晶粒通常設有位於前側之互連墊(晶粒墊),供晶粒 上之電路與佈署有晶粒之裝置中之其他電路電氣互連。所 設置的某些晶粒在前側上,沿一或更多晶粒邊具有晶粒墊 ,且此等晶粒可稱爲周邊墊晶粒。所設置的其他晶粒具有 成一或更多列配置在接近晶粒中央之前側之晶粒墊,且此 等晶粒可稱爲中央墊晶粒。晶粒可“重新安排路線”以在晶 粒之一或更多邊或接近該處提供互連墊之適當配置。 半導體晶粒可藉若干機構之任一者,與例如印刷電路 板、封裝基板、引線架或其他晶粒中的其他電路電氣連接 。此中z互連可例如藉由配線接合、倒裝晶片互連或膠帶 自動接合互連形成。封裝基板或引線架於安裝封裝而供使 用之裝置中,提供封裝對諸如印刷電路板上電路之下覆電 -5- 201138062 路(第二級互連)的電氣連接。 已有人提議許多方案來增加積體電路晶片封裝中之主 動半導體電路之密度,同時減小封裝尺寸(封裝涵蓋表面 、封裝厚度)。於製造具有較小涵蓋表面之高密度封裝之 方案中,功能相同或不同之二或更多半導體晶粒相互堆# 並安裝於封裝基板上。 堆疊半導體晶粒之電互連提供許多挑戰。例如,堆疊 中之二或更多晶粒可以其背離基板之前側安裝在基板上, 並藉由晶粒對基板或晶粒對晶粒配線接合連接。可形成晶 粒對晶粒配線接合互連,其中上晶粒大小定成或定位成上 晶粒不覆蓋在其連接之下晶粒之邊緣,且對配線跨距提供 不同水平空隙。這種狀況可能係例如上晶粒之涵蓋表面遠 較下晶粒狹窄:或例如,上晶粒配置成上晶粒之涵蓋表面 相對於下晶粒之邊偏移。替代地,堆疊中之晶粒可藉由將 其等連接於安裝堆疊之共用基板間接互連。在堆疊中之下 晶粒係配線接合之晶粒對基板,且上晶粒之涵蓋表面覆蓋 下晶粒之邊情況下,可介設隔件以在下與上晶粒間提供足 夠之垂直空隙,以調整下晶粒上方之配線環。隔件增加堆 疊之厚度,並因此增加封裝之堆疊之厚度。而且,於此一 配置中,下晶粒之配線接合之晶粒對基板連接必須在隔件 與上晶粒堆呰於其上方之前完成;亦即,晶粒必須原位堆 鹽於基板上,且晶粒必須串聯堆#及連接。 藉由參考倂提於本文之2008年5月20日由S.J.S.麥克艾 爾里等人所提名稱爲“電互連堆疊晶粒總成”之美國申請案 6 - 201138062 其中晶粒上之互連墊 些配置中,堆疊中之 互連墊,且覆蓋晶粒 此偏移露出下晶粒上 上之墊可用來與位於 材料係例如像是可固 月20日由Τ.卡斯開等 i互連”之美國申請案 疊晶粒與基板電互連 互連材料於原位以形 材料,並可於非固化 部或額外於分送後之 時完全固化。適當互 之聚合物,例如金屬 樹脂、金屬充塡熱固 暮電油墨。 依互連與接合墊間之 完整性而定。有朝向 連墊面積之一般趨勢 聚合物,像是充塡銀 料間之電氣導通依互 第1 2/1 24,077號說明堆疊晶粒配置, 藉導電互連材料之軌跡電連接。於某 相鄰晶粒設有沿晶粒邊配置於前側之 之邊緣相對於其下方之晶粒邊偏移。 互連墊之至少一部分區域,俾下晶粒 上方之晶粒上的墊電連接。導電互連 化導電環氧樹脂之導電聚合物。 藉由參考倂提於本文之2008年5 人所提名稱爲“藉由脈波分送形成之ΐ 第1 2/ 1 24,097號說明堆疊中晶粒或堆 之方法,其藉由以一系列脈波沉積電 成電連續互連。互連材料可爲可固化 或局部固化狀態下沉積;且材料可局 中間階段固化,並可在分送業已完成 連材料包含以粒子形式充塡導電材料 充塡聚合物,包含例如金屬充塡環氧 化聚合物、金屬充塡熱塑化聚合物或 晶粒對晶粒電連接之品質一部分 電氣導通,一部分依互連軌跡之機械 更細互連墊節距,並因此朝向更小互 。在互連材料係例如充塡導電粒子之 之環氧樹脂情況下,晶粒墊與互連材 連材料與墊表面間之附著而定。 堆疊晶粒總成須可在操作期間耐溫度變化。熱膨脹特 201138062 徵在封裝中各種材料間不同,且結構之熱循環可能造成互 連軌跡本身或晶粒墊或接合墊與互連軌跡間之接觸之疲勞 分解。 【發明內容】 本申請案揭示一種堆疊晶粒總成,其中互連故障藉由 多種方案之任一者減低。堆#晶粒總成包括堆疊於諸如基 板之支撐上方之晶粒,其中晶粒上之墊藉導電材料所形成 之軌跡電氣互連且電氣連接至支撐中之電路。適當導電材 料包含能以可流動形式應用,並接著固化或容許固化以形 成導電軌跡之材料。此種材料例如包括導電聚合物,其包 含可固化有機聚合物基質(例如導電(例如充塡)環氧樹 脂或導電油墨)中所含導電微粒子(例如導電金屬粒子) ;並例如包括於水載體中供應之導電微粒子。於特定實施 例中,互連材料係可固化導電聚合物或導電油墨之導電聚 合物。 電連接晶粒之支撐可爲電路板或封裝基板或引線架。 適當封裝基板例如包括球形格柵陣列(“BGA”)或焊墊格 柵陣列(“LGA”)基板或撓性膠帶基板。 熱膨脹特徵(特別是熱膨脹係數或“CTE”)在總成中 各種材料間不同,且結構之熱循環可能造成晶與互連間之 接觸之疲勞分解。構成各種不同組件之材料之不同CTEs可 能造成組件在一溫度範圍內脹縮不同程度。在總成之各個 組件相互牢牢固定情況下,這種差分膨脹/收縮可能造成 -8- 201138062 總成或總成之某些零件之翹曲。這種效應在堆疊中之晶粒 非常薄情況下特別有問題。依特定材料及特定溫度循環而 定,翹曲可能產生凸出之上晶粒表面或凹入之上晶粒表面 。這可能造成互連例如因互連軌跡之龜裂或破裂;或因軌 跡與晶粒墊或接合墊之完全或局部分離(層間剝離)而故 障。 電腦模擬、應力分析及測試業已在互連故障之位置暗 示或顯示某些圖案。例如,於至少某些堆疊晶粒總成中, 互連故障可能位於接近晶粒角隅之墊中。且例如於至少某 些堆疊晶粒總成中,互連故障位於堆疊中底部晶粒上晶粒 墊與基板上接合墊間的某些點。互連軌跡可例如局部會全 部自晶粒墊或自接合墊剝離;或者,例如,互連軌跡本身 可能在互連側壁上背側晶粒緣銜接基板之內角隅。 電腦模擬、應力分析及測試業已進一步暗示互連材料 與晶粒墊或接合墊間之電連接之強度可在墊上的某些位置 較其他位置更佳。特別是,依晶粒堆疊之特定配置而定, 若形成於墊中較接近晶粒緣之位置,或較接近底部晶粒之 互接側壁上之背側晶粒緣銜接下覆基板之晶粒附著側之內 角隅,或上晶粒之互接側壁上之背側晶粒緣銜接下覆晶粒 之主動側,即可產生更強的連接。 以下所述各種不同方案以互連故障爲課題。 於一方案中,堆疊中之底部晶粒具有較堆疊中之其他 晶粒更大的厚度。這可在晶圓級之底部晶粒製造中,例如 藉由使背硏磨後之底部晶粒較其他晶粒更厚來達成。底部 -9 - 201138062 晶粒可具有與堆禋中其他晶粒相同(或類似)之功能;或 者,底部晶粒可具有異於堆踁中其他晶粒之功能。較大厚 度對堆铿提供增大硬度,並可協助減少翹曲或彎曲。 於另一方案中,無作用晶粒位在堆题中最低功能晶粒 與支撐之間。在某些配置中,無作用晶粒可配置成大致與 堆疊中最低功能晶粒相同;在某些此種配置中,互連可不 接觸額外晶粒上之墊;或者,在某些此種配置中,墊可失 效(例如,它們可爲介電材料所覆蓋,俾額外晶粒不電連 接至覆蓋互連軌跡)。在某些配置中,無作用晶粒可爲額 外晶粒;在其他配置中,無作用晶粒係堆疊之“犧牲”底 部晶粒,藉由失效使之無作用。 於另一方案中,接近晶粒角隅之區域無電連接。在某 些配置中,“空出”區域可構成晶粒之互連邊部分,在此無 晶粒。該配置可以重新安排路線圖案設計入墊的佈署;或 者該配置可在晶粒切單期間,藉由將晶粒切割成較電路及 墊配置最低要求還寬達成。在某些配置中,“空出”區域可 於接近受影響角隅的一個或許多晶粒墊位置(“犧牲墊位 置”)構成對墊的失效互連。例如,犧牲墊位置中的晶粒 墊可失效(例如它們可爲介電材料所覆蓋),俾晶粒不電 連接至空出區域的覆蓋互連軌跡。在某些配置中,犧牲墊 位置中晶粒墊與對應接合墊之連接可藉由使基板上對應位 置之接合墊失效,或藉由將基板設計成無接合墊位於其上 來防止。 於另一方案中,在總成模製或封裝情況下,於模製或 -10- 201138062 封裝程序後完成互連材料之固化。在以可流動形式沉積互 連材料後,可進行局部固化。此後,進行模製或封裝,以 延遲互連材料之固化,直到總成業已藉由模製或封裝穩定 至某一程度後爲止。通常,在藉由加熱完成模製化合物或 封裝劑及互連材料兩者之固化,且每一者之固化過程可具 有不同溫度時間表情況下,可根據所用特定材料之固化要 件處理。 於互連材料之固化在模製或封裝程序後完成之又一方 案中’模製或封裝之總成可在最後固化期間預應力以提供 構造中之抗翹曲或彎曲。亦即,在特定總成之測試或模製 暗示熱應力可能產生凹入之上晶粒表面情況下,模腔配置 成當總成被壓入腔內,總成即撓曲以形成凸出之上晶粒表 面’並在最後固化期間保持於此狀態;或者在特定總成之 測試或模製暗示熱應力可能產生凸出之上晶粒表面情況下 ’模腔配置成當總成被壓入腔內,總成即撓曲以形成凹入 之上晶粒表面’並在最後固化期間保持於此狀態。 某些類型的互連故障可由軌跡中的橫向龜裂造成,其 通常自軌跡材料之表面發展,且其可能在模製或封裝期間 產生。因此’於另一方案中,特別是例如在總成待模製或 封裝情況下’互連軌跡可在封裝或模製程序前施加諸如聚 合物(對二甲苯基或矽橡膠)之材料膜。顯然地(無限制 )膜於互連材料與模製材料或封裝劑之間提供一種緩減或 潤滑’且藉此’例如在可能導致龜裂形成之應力測試期間 減少應力。 -11 - 201138062 於另一方案中,在模製暗示更強的電連接可在晶粒墊 或接合墊(“較佳位置”)獲得情況下,電連接被指向較佳 位置。特別是例如特定總成配置之應力分析可能暗示於晶 粒墊或接合墊上的某些位置,電連接(亦即導電軌跡與墊 間之連結)低於壓縮,於墊之其他位置上,電連接低於張 力。壓縮下之電氣連接可能更強。因此,互連材料應用來 特別是接觸較佳位置。在某些配置中,在提供介電施加, 待與互連軌跡接觸之區域上方有一開口情況下,藉由特別 是形成開口於較佳位置上方來完成。 於另一方案中,底部充塡形成於堆铿中的底部晶粒與 基板間。底部充塡沉積於接近底部晶粒之一或更多緣處。 底部充塡強化晶粒堆疊對基板之附著,並協助避免或減少 沿邊緣離層。底部充塡可間隔沿邊緣或連續沿邊緣施加於 特定點。在使用非導電底部充塡情況下,其可於晶粒緣之 任一者或沿其沉積,於某些配置中,非導電底部充塡沉積 於沿晶粒互連側壁之許多點,通常一般於接合墊間;且於 某些配置中,非導電底部充塡材料沉積於沿一或更多非互 連側壁之連續線。在使用導電底部充塡情況下,其可沉積 於不會造成短路的任何位置》於某些配置中,底部充塡沉 積於底部晶粒角隅或其附近,遠離晶粒或基板表面之任何 導電特性處。 於另一方案中’底部充塡材料沉積於由側壁與下覆表 面所形成之內角。側壁可例如爲底部晶粒之互連側壁,且 下覆表面可例如爲係接合墊內及鄰近晶粒側壁之基板之晶 -12- 201138062 粒附著側之區域。或者,互連側壁可例如爲上晶粒之互連 側壁:且下覆表面可例如爲下覆晶粒之接合墊內及鄰近上 晶粒側壁之下覆晶粒前側之電絕緣區域。或者,晶粒側壁 可例如爲基板上晶粒向位在下之倒裝晶片晶粒之側壁,且 電氣連接至晶粒涵蓋表面中之基板,且下覆表面可例如爲 接合墊內及鄰近晶粒側壁之基板之晶粒附著側之電絕緣區 域。或者’互連側壁可例如爲堆疊倒裝晶片晶粒上方之晶 粒之互連側壁;且下覆表面可例如爲下覆倒裝晶片晶粒後 側之電絕緣區域。或者,底部充塡可例如沉積於模製封裝 ’像是晶片比例封裝之側壁所形成之內角。底部充塡可形 成’其形成倒圓角之橫剖約呈正三角形;三角形之直角三 角形斜邊係可形成互連軌跡之斜面;且三角形之垂直側於 上晶粒互連緣或其附近形成具有直角三角形斜邊之角度。 倒圓角之斜面可微凹或凸,或可爲更複雜之略微弧曲表面 。底部充塡可爲CTE匹配以協助穩定該總成,減少離層效 應。而且’形狀如上述之底部充塡可提供從晶粒對晶粒或 從晶粒對基板之逐漸過渡,於晶粒之互連緣或於晶粒之側 壁之後緣銜接下覆表面之內角隅消除陡急角度(約爲直角 )過渡。在某些配置中,形成於底部晶粒之側壁及基板之 第一底部充塡材料倒圓角可支撐第一組電互連軌跡,此等 電互連軌跡連接底部晶粒上之墊與基板上之第一列中的接 合墊;且形成於上晶粒及底部晶粒之側壁之第一倒圓角上 之第一互連軌跡上方的額外底部充塡材料倒圓角可從上晶 粒上之晶粒墊至基板上從第一列起向外之第二列接合塾。 -13- 201138062 可使用其他方案’其中底部充塡材料形成於基板上晶 粒向位在下之倒裝晶片晶粒之側壁之內角,μ _胃胃g ^ 粒涵蓋表面中的基板,且下覆表面係接合塾內倒J及^胃f曰E| 粒側壁之基板之晶粒附著側之電絕緣區域,以胃Μ於_ P艮弟ij 底部充塡材料越過基板流動(“溢出”或“流出,,)。 於一個此種方案中,在沉積底部充塡材料流前形成— 堰堤,以防止或限制底部塡充劑材料側向,亦即、沿^; $ ¥ 行於基板上之接合墊列之方向流動。堰堤材料可·胃&巧· & 動形式施加之可固化材料,且其在此後固化或容胃午g]彳匕。 堰堤材料可具有在非固化狀態下一般較底部充塡材· g H 不可能流動(溢出或流過)的性質。堰堤材料可·仿U 胃有· 較底部充塡材料流更高的黏度。堰堤材料及底材·_ 流可在相同固化程序中固化,或者堰堤材料可在較导匕 程序中固化》 於另一個此種方案中,基板之附著側覆蓋軟焊掩模, 溝槽可形成於軟焊掩模中,其具有一溝槽壁,該溝槽 致平行於基板上之接合墊列,限制底部充塡材料流;@胃& 墊,並防止底部充塡材料溢出或流過接合墊。流動之潛& 材料之前進前部可大致於溝槽壁緣停止。 根據本發明之晶粒、封裝及總成可用於電腦、遠距s 信設備、消费及工業電子裝置。 【實施方式】 現在將參考顯示本發明之選擇性實施例之圖式,更詳 -14- 201138062 細說明本發明。圖式示意顯示本發明之特性,及其與其他 特性和構造之關係,且不按比例繪製。爲增進圖式中顯示 本發明實施例之清楚呈現,對應其他圖式中所示元件之元 件全部不重新編號,雖則其等在圖式中均容易辨識。亦爲 了清楚呈現,某些對本發明之瞭解不必要的特性不顯示於 圖式中。於說明中的某些點,可參考圖式中之位向諸如“ 上方”、“下方”'“上”' “下”、“頂部”、“底部”等相對位置 名詞;此等名詞並非意在限制使用中之裝置之位向》 現在轉至第1圖,其以立體圖顯示安裝於基板110上方 之半導體晶粒1 0。晶粒1 0具有二較大之大致平行.、大致矩 形側及四面側壁。一較大側壁稱爲前側,其他稱爲後側。 晶粒之電路位於前側之晶粒表面或接近該表面,並因此, 前側可稱爲晶粒之主動側。於第1圖所示視圖中,晶粒1 0 以背離基板11 〇之主動側顯示,俾晶粒1 〇之前側1 2可見。 於第1圖中亦可見的係晶粒1 〇之側壁1 4及1 6。晶粒之邊緣 接近側壁;例如,邊緣1 7接近晶粒1 0之前側1 2上之側壁1 4 。晶粒側壁與前側之相交處界定一前緣;例如前緣1 3界定 於晶粒側壁I4與前側12之相交處。互連墊配置於沿前緣之 邊緣中;於在此所示例子中’墊1 8成列1 9沿晶粒1 0之前緣 13配置於邊緣17或與其接近處。配置有墊之晶粒緣可稱爲 “互連緣”,且相鄰邊及晶粒側壁可分別稱爲“互連邊”及“ 互連側壁”。 於第1圖所示例子中,晶粒1 0藉晶粒附著膜1 5安裝至 基板11 0之晶粒附著側1 1 2。通常,若干基板成一或更多列 -15- 201138062 形成帶裝,且依序藉由鋸開或沖裁分開。於圖示例子中, 接合墊1 1 8成列1 1 9配置於基板1 1 0之晶粒附著側1 1 2,且晶 粒放置成墊18 —般與基板上之對應接合墊118對準。具有 對應接合墊118之墊18之電連接(於第1圖中未顯示)藉由 以可流動形式施加微量導電材料於個別晶粒墊及接合墊上 方,並接著固化(或容許材料固化)材料以完成互連製成 〇 供參考,平行於晶粒之較大側之平面(基板之晶粒附 著側之平面)之X及Y方向軸以及垂直於該平面之Z方向軸 以11標示於第1圖中且以21標示於第2A、2B及2C圖中。 像是例如於第1圖顯示之總成中之各種材料可具有不 同熱膨脹特徵(不同熱膨脹係數“CTE”)。特別是於晶粒 (矽)與晶粒附著膜間有一種CTE失配。構造之熱循環可 能在構造中造成壓力及應力,這可能造成互連與晶粒墊或 互連本身之接合墊間接觸之疲勞分解。 第2A、2B及2C圖以平面圖(第2A圖)並以剖視圖( 第2B、2C圖)中顯示安裝於基板210上之晶粒20。於在此 所示例子中,晶粒20藉晶粒附著膜25安裝至基板210之晶 粒附著側212。於本例子中,晶粒墊28、28’沿互連邊27、 27’成列29、29’配置於相對晶粒緣23、23’處。對應晶粒墊 218、218,沿互連邊27、27,成列219、219’配置於基板的附 著側2 1 2,且晶粒位於使晶粒墊1 1 8、1 1 8 ’大致與基板上之 對應接合墊218、218,對齊。若干基板成一或更多列形成 帶裝,且依序藉由鋸開或沖裁分開。於圖示例子中’接合 -16- 201138062 塾1 1 8成列1 1 9配置。具有對應接合墊2 ! 8、2 i 8,之晶粒墊 118、118’之電連接(於第丨圖中未顯示)藉由以可流動形 式施加導電材料的軌跡於個別晶粒墊及接合墊之上,並接 著固化(或容許材料固化)材料以完成互連來製成。各種 不同組件彼此相對收縮或膨脹之趨勢以箭頭2 1表示。 各個組件脹縮不同之趨勢可能造成零件之相對移動; 例如晶粒緣可相對於下覆基板移動。更通常地,在各個組 件牢固地彼此附著情況下,各個組件脹縮不同之趨勢可能 造成構造或構造之一部分捲曲或翹曲。這種形狀的變形可 能因導致互連本身中的龜裂或破裂,或因互連與一或更多 墊之局部或完全離層,而造成某些互連的故障。 藉由參考倂提於本文之2008年5月20日由S.J.S.麥克艾 爾里等人所提名稱爲“電互連堆疊晶粒總成”之美國申請案 第12/1 24,〇77號特別說明堆疊晶粒總成,其中堆疊中的連 續在晶粒墊座落之晶粒緣偏移,且晶粒藉導電軌跡互連。 導電軌跡由以可流動形式施加之材料形成,並依續固化或 容許固化。此種材料例子包含諸如充塡聚合物之導電聚合 物,例如充塡環氧樹脂或導電油墨。 第3A圖平面顯示偏置堆疊晶粒34a-34h之配置,每一 晶粒具有配置於鄰近前晶粒緣之一邊中的互連墊;且第3B 圖剖面顯示第3A圖中1B-1B所示之堆疊。參考堆叠中的最 上方晶粒44h,例如互連墊32在此例中成列312沿前晶粒緣 3 1 1定位。此例中的晶粒34h藉電絕緣等角塗層37覆蓋於所 有表面(後表面33、前表面35、側壁31)上,設有露出互 -17- 201138062 連墊3 2之開口》於此等例子中’堆疊中的連續施加晶粒可 直接彼此疊置,俾上晶粒後側上之塗層可接觸下覆晶粒前 側上之塗層。任選或額外地’晶粒附著膜可層盤至一或更 多晶粒之後側。 於第3 A及3 B圖所示例子中,每一晶粒具有沿一前晶粒 緣(“互連緣”)座落於一邊中的互連墊’且堆疊中的後續 晶粒配置成其個別互連緣面朝堆疊之同面。堆疊中的連續 晶粒在與墊座落之晶粒緣正交之方向中位移(偏移)’且 於此處所示例子中,該偏移離開於完全露出之各下覆晶粒 中的墊。該配置提供來作爲梯級晶粒堆题’且電互連越過 梯級形成。 堆疊安裝於具有在晶粒安裝表面39露出之一列316接 合位置36之支撐(例如封裝基板)上。接合位置連接至支 撐電路(未圖示)(或構成其一部分)。晶粒堆疊附著於 基板之晶粒安裝表面39,且配置成第一晶粒34a之前側壁 31 a沿一排316之接合位置36對準。如於此等例子中’第一 晶粒之施加後側直接接觸支撐表面3 9,且可用來附著堆疊 於支撐。任選地,晶粒附著膜可層脛至第—晶粒之後側以 附著堆II於支撐。 晶粒於堆疊中電連接(晶粒對晶粒),且堆疊藉配設 成與晶粒墊和接合墊接觸之互連材料之軌跡318電連接至 該支撐。互連材料可爲導電聚合物,像是含導電材料粒子 之聚合物基質。材料可爲可固化聚合物,例如像是導電環 氧樹脂(例如充塡銀之環氧樹脂):且可藉由以所規定圖 -18- 201138062 案形成未固化材料之軌跡,且此後固化聚合物,製成互連 ,以獲得與晶粒墊和接合位置之電氣接觸,及獲得其間軌 跡之機械完整性。 第3C圖顯示如於第3A及3B圖中所示堆疊部分(第3B 圖中虛線3C所示)。晶粒藉電絕緣等角塗層覆蓋於所有表 面上;亦即,例如晶粒34a之後表面33a、前表面35a及側 壁31a爲等角塗層37所覆蓋。該塗層設有露出互連墊32a之 開口。晶粒偏置;亦即,例如晶粒3 4 b之緣3 1 1 b相對於晶 粒34a之緣31 la後退(至圖式右側),使晶粒34a上之墊 3 2a露出。晶粒堆疊位於支撐之表面39上,使第一(最下 )晶粒34a之緣31 la對準接合墊36,且接合墊至少局部露 出。導電互連318接觸接合墊36、晶粒墊32a及晶粒墊32b (下覆晶粒中的連續晶粒墊),且其配設於塗層37上,其 使互連與下覆晶粒表面電絕緣。 如參考第3A、3B及3C圖所說明形成與晶粒墊和接合 墊導電互連之接觸可造成滿意的電晶粒對晶粒電互連或晶 粒對支撐電連接。於墊節距很細且晶粒墊及接合墊很小情 況下,此等構造可能易疲勞故障, 其中電連接在重複熱循環後,變得不理想。模擬該系統( 在連同故障互連之觀察之某些例子中)顯示於熱循環期間 或之後互連處於高壓,造成例如依第3C圖中箭頭A所示導 電材料自墊剝離(離層),並劣化或破壞導體與墊間之墊 連接。 又,特別是在互連非常薄情況下,模擬該系統(在連 -19- 201138062 同故障互連之觀察之某些例子中)顯示在堆疊最下方晶粒 之後緣(例如第3 C圖中之緣3 3 1 a )銜接下覆基板之“內角” 之互連中的龜裂或破裂。 如上述,在晶粒之前側爲電絕緣塗層覆蓋情況下,晶 粒上之墊可藉由選擇性移除墊上方的電絕緣塗層,用於m 連接。當互連材料沉積於堆疊中晶粒之上方時,材料僅接 觸露出之墊,並無與墊之電接觸(或另一晶粒表面爲互連 材料所覆蓋),此等墊保持爲電絕緣塗層所覆蓋。於第3A 、3 B及3C圖中,所有晶粒上的所有墊顯示成露出,供藉導 電軌跡電連接,且因此,在此等例子中,各晶粒中各墊電 連接至堆疊中另一晶粒上之墊及基板上之接合墊。依晶粒 上的墊佈局設計而定,既定晶粒上所有墊與其他晶粒上的 墊或與下覆支撐上的接合墊的電連接可能不理想。於此情 況下,可移除各晶粒上所選墊上方的電絕緣塗層,以露出 所選墊,且塗層可適當留在墊上,對其之電連接不符期望 。這可稱爲“刪減程序”,其用來使墊可選擇性用於電接觸 。或者,替代地,於“追加程序”中,電絕緣塗層可施加於 許多區域,於其上可形成電軌跡,且在此不擬有電接觸。 某些類型的互連故障可由軌跡本身中的橫向龜裂造成 ’其通常自軌跡材料之表面發展,且其可在模製或封裝期 間或之後,像是熱測試期間或使用中的熱循環期間發生。 因此’於其他方案中,特別是例如在總成待模製或封裝情 況下’互連軌跡可在封裝或模製之前,施加諸如聚合物之 材料膜(例如對二甲苯或矽橡膠)。諸如室溫硬化矽彈性 -20- 201138062 體之矽橡膠可能適當’此等材料可例如從D〇w Corning購 得。例如此種具有約1/2毫米(約1〇微米)厚度之材料可 能足以減緩龜裂形成。顯然(未限制本發明),膜於互連 材料與模製材料或封裝材料間提供一種緩和或摩擦減少, 藉此減少可能導致龜裂形成之應力。可選擇其他材料來提 供應力緩和或摩擦減少。 於第4A、4B圖中顯示使用供選擇性製造可用於連接之 墊之刪減程序製成之總成。第4 A圖舉例平面顯示8晶粒偏 置堆疊之互連緣附近一部分。每一晶粒具有一列49之墊( 於本例子中例如墊4 8 ; 3 2 )。於本例子中,此等墊可根據 括弧(1)、(2)、(3)…(30)、(31)、(32)所示與晶粒40上之墊 位置對準之墊位置,用1至η (於本例子中1 - 3 2 )來標示。 晶粒彼此堆疊並偏移,俾每一晶粒之互連緣相對於在其下 方之互連緣後退。晶粒配置於堆疊中,使對應墊位置於行 中對準。堆疊安裝於具有互連位置(接合墊或引線)46之 支撐(在此爲基板)400上。堆疊中之最下方晶粒以基板 定向成,堆疊緣(亦即,下晶粒互連緣)重疊基板上之引 線,且墊行與引線對準,因此’於此例子中’並無次於堆 疊之互連跨距尺寸。 本例子中的晶粒堆疊覆蓋等角絕緣塗層47 (像是例如 對二甲苯之材料)。形成貫穿等角塗層之開口(例如藉由 雷射濺鍍)以露出所選互連晶粒墊(例如墊48 )’惟所選 其他互連晶粒墊受到保護(電絕緣)° 第4Α、4Β圖顯示8晶粒偏置堆疊之互連部分,其與越 -21 · 201138062 過墊行(例如在行(1)、(2)、(3 ))之上形成之軌跡4 1 8電 互連。第4B圖係如第4A圖之B-B所示’於墊位置(2)行 處,貫穿第4A圖之構造之剖視圖。於此行中’在上面四個 晶粒中的墊(例如從頂部起第四個晶粒中的墊48 )及基板 上之接合墊46藉等角絕緣塗層中的開口露出;且下四個晶 粒中的墊(以及頂部晶粒上之墊內側之前側區域和基板之 外側區域)被覆蓋。露出之墊可藉形成於其上方之互連軌 跡用於電連接,而覆蓋墊(及其他覆蓋表面)絕緣以免與 任何覆蓋電軌跡接觸。軌跡4 1 8電氣連接行中之露出晶粒 墊(例如墊48 )至行中之其他露出晶粒墊及至基板400上 之對應互連位置46。仍被絕緣塗層覆蓋之墊及互連材料所 覆蓋之其他晶粒表面不電連接。 互連材料係可以可流動之形式施加的材料,且此後其 固化或容許固化以形成導電軌跡。爲形成軌跡,晶粒堆曼 可例如支撐於堆疊中最下方晶粒之後側,且互連材料可沿 軌迹施加於待連接之塾及其間之晶粒表面上方。互連材料 可使用例如像是注射器或喷嘴的施加工具施加。材料 '沿著 一般朝互連端子之沉積方向吐出,且工具沿工作方向移動 於晶粒堆疊面上方。在工具移動時,材料沉積。材料可以 連續流自工具擠出’或者’材料可一滴滴從工具吐出。材 料可成爲液滴射流從工具吐出,或成點狀沉積,這些點在 與堆疊表面接觸時或之後結合。液滴可非常小,且可成氣 霧從工具吐出。 互連材料可爲導電聚合物,像是充塡導電材料粒子之 -22- 201138062 聚合物。此材料可爲可固化聚合物’例如像是導電環氧樹 脂(例如充塡銀之環氧樹脂):且互連方法可包含成規定 圖案形成未固化材料之軌跡’且此後固化聚合物以獲得與 端子間之電接觸,以及獲得其間軌跡之機械整體性。或者 ,互連材料可爲導電油墨。 第5圖顯示一總成例子,其中堆疊中之底部晶粒5 1具 有較堆疊中其他晶粒52、53、54、55、56、57、58更大之 厚度。爲求清晰,圖式省略許多細節。例如,可使用晶粒 附著膜,並可於不擬電氣連接於覆蓋導電軌跡之表面上方 設置等角介電塗層(或其他電絕緣)。於該圖式中亦不顯 示互連軌跡。晶粒5 2、5 3、5 4、5 5、5 6、5 7、5 8可單切以 形成薄化(例如於背硏磨操作中)至所欲厚度之晶圓;且 晶粒5 1可業已從薄化至較其他大之厚度的晶圓單切。底部 晶粒可具有與堆疊中其他晶粒相同(或類似)的功能。或 者,底部晶粒可具有異於堆疊中其他晶粒的功能;例如, 較厚底部晶粒可爲處理器晶粒,且其他晶粒可爲記憶體晶 粒。根據所完成總成之期望功能,考慮其他晶粒功能。底 部晶粒之較大厚度對堆疊提供增大之硬度,並可協助減少 翹曲或彎曲。底部晶粒可能需要哪種厚度可特別是依封裝 之整體尺寸、其他晶粒之厚度及總成之各個組件中的CTE 失配程度。 第6A、6B及6C圖顯示堆疊晶粒總成的許多例子,其 中無作用晶粒位於堆疊中最下方功能晶粒與基板間。於第 6A圖中,例如無作用晶粒60係“虛設”晶粒;亦即,其無電 -23- 201138062 子功能。於本例子中’晶粒51、52、53、54、55、56、57 、5 8之8晶粒堆疊安裝於虛設晶粒上方。虛設晶粒之作用 係相對於基板5 00上之接合墊昇高最下方功能晶粒5 1之水 平(亦即互連緣)。 於第6B圖中,例如無作用晶粒62具有電子電路及周邊 晶粒墊,且其可配置成實質上與堆疊中最下方功能晶粒5 1 相同。於本例子中,無作用晶粒6 2上之晶粒墊如圖式中以 墊上之“X”所標示失效。此墊可例如爲介電材料所覆蓋, 俾額外晶粒不電連接至覆蓋互連墊。或者,例如,可切斷 墊對晶粒上之電路之電連接。 於第6A及6 B圖之例子中,無作用晶粒係額外晶粒;亦 即,無作用晶粒介設於晶粒堆疊與基板間。第6C圖之例子 類似於第6B圖之例子,除了在此無作用晶粒6 1係晶粒堆疊 本身的最下方晶粒,其以例如如參考第6B圖所述方式失效 。由於堆题中的最下方晶粒可在失效前完全發揮功能,因 此,晶粒61可稱爲“犧牲”晶粒。 第7A、7B及7C圖顯示堆疊晶粒總成的許多例子,其 中晶粒角隅附近區域無電連接。於例如第7A圖所示某些配 置中,“空出”區域72可構成無墊之晶粒之互連邊之一部分 。如上所述,該配置可以重新安排路線圖案設計墊佈署。 或者,該配置可於晶粒單切期間,藉由將晶粒切割成較電 路及墊配置最低需要更寬形成。 在例如顯示於第7B圖之某些配置中,“空出”區域74於 接近受影響角隅的一個或許多晶粒墊位置(“犧牲墊位置” -24- 201138062 )構成對墊的失效互連。於圖示例子中,犧牲墊位置(1)、 (2)、(3)及(30)、(31)、(32)爲介電材料所覆蓋(且無開口 形成於此等墊行上方)俾晶粒不電連接至空出區域中的覆 蓋互連軌跡。 在例如顯示於第7 C圖之某些配置中,“空出”區域7 6並 非藉由使晶粒上的墊失效,而是藉由使基板上對應位置之 接合墊失效,或藉由將基板設計成無接合墊位於其上來建 立。於圖示例子中,“空出”區域76中之接合墊保持藉基板 表面軟焊掩模或其他基板表面絕緣所覆蓋。 第8A、8B及8C圖顯示堆疊晶粒總成的許多例子,其 中底部塡充劑形成於底部晶粒與基板間的底部晶粒之一或 更多緣附近。底部塡充劑強化晶粒堆疊對基板之附著,並 協助防止或減少沿邊緣離層。 底部塡充劑例如顯示於第8 A圖中。在此,堆疊中晶粒 5 1、5 2、5 3、5 4、5 5、5 6、5 7、5 8之每一者藉晶粒附著膜 附著於下附晶粒(或基板);例如膜5丨8將晶粒5 8附著於 下附粒5 7,膜5 1 1將晶粒5 1附著於基板5 〇 0。晶粒附著膜 5 1 1在大小上作成,鄰近互連晶粒緣之晶粒與基板間的空 隙未被膜充塡。於在此所示方案中,一些底部充塡材料沉 積於BB粒:緣,並如第8A圖中82所示,流入該空隙,且可於 晶粒側壁形成“倒圓角,,8 3。 底部塡充劑可例如依第88圖所示,沿—緣隔著間隔, 或沿一緣連續施加於諸特定點。於第8B圖中,非導電底部 充塡材料沿晶粒互連側壁沉積於諸點,例如點83,其—般 -25- 201138062 在接合墊’例如接合墊85間。如底部充塡材料之特徵所示 ’ 一旦沉積之底部塡充劑可能流入底部晶粒與基板間的任 何空隙。 於第8 C圖中’底部充塡材料沿底部晶粒緣,在底部晶 粒之角隅附近’沉積於諸點’例如點8 6。如底部充塡材料 之特徵所示’一旦沉積之底部塡充劑可能流入底部晶粒與 基板間的任何空隙。 於其他配置中’底部塡充劑成連續線沿非互接側壁之 —或更多者沉積。在使用導電底部塡充劑情況下,其可沉 積於底部塡充劑不會造成短路之任何位置》底部塡充劑方 案可用於如在此圖示之晶粒偏置之晶粒堆疊;或堆疊中各 晶粒在至少一維中比下方晶粒小(角錐堆疊)之晶粒堆疊 :或堆铿中之連續晶粒錯開並可旋轉之堆疊中。此種配置 例如說明於以上參考之美國專利申請案第1 2/1 24,077號中 〇 可使用導電或非導電底部充塡材料。在使用導電底部 塡充劑情況下,其可沉積於底部塡充劑不會造成短路之任 何位置。底部充塡材料可使用標準設備來施加,且可在電 氣互連軌跡形成之前或之後施加。 第9 A、9B及9C圖顯示堆疊晶粒總成的許多例子,其 中沉積底部充塡材料’以在晶粒側壁與下覆面所形成的內 角形成倒圓角。第9A圖顯示一種配置,其中晶粒側壁係上 晶粒9 3之互連側壁9 4,且下覆面係下覆晶粒上之晶粒墊內 側及鄰近上晶粒側壁處’下側晶粒5 2之前側之電絕緣區9 6 -26- 201138062 。沉積之底部充塡材料形成一倒圓角9 〇,其提供自上晶粒 互連緣延伸至晶粒墊內側之下覆晶粒表面的漸傾表面,於 其上面可形成電互連軌跡9丨,其電連接上晶粒5 3及下覆晶 粒5 2 (以及適當地’連接額外晶粒,例如晶粒5丨)上之墊 至基板500中的電路。 可使用標準底部充塡材料,且其可使用供適用底部塡 充劑之標準設備。較佳底部充塡材料可爲高模量材料,其 具有與總成中其他材料匹配之良好C Τ Ε。舉例來說,一適 當標準底部充塡材料以Namics U8439-1名稱行銷。 第9B圖顯示一配置’其中晶粒51及52晶粒朝上安裝於 倒裝晶片晶粒9 1上方,該倒裝晶片晶粒9 1晶粒向下安裝於 基板500上’且其中底部塡充劑倒圓角9〇〇形成於晶粒51及 倒裝晶片晶粒9 1之側壁9 1 4、9 2 4與晶粒墊內側之下覆基板 5 00的表面91 6所形成之內角。於該例子中,—額外倒圓角 9 〇 2形成於晶粒5 2之互連側壁與晶粒墊內側之下覆晶粒5 i 的表面所形成之內角。倒圓角900、902提供自上晶粒52互 連緣延伸至晶粒墊內側之下覆晶粒表面,接著自晶粒5丨互 連緣延伸至晶粒墊內側之下覆晶粒表面的漸傾表面,於其 上面可形成電互連軌跡9 1 I,電連接上晶粒5 2及下覆晶粒 51上之墊至基板50〇中的電路。 第9C圖顯示又一例子,其中底部充塡材料倒圓角932 形成於晶粒5 3之互連側壁與下覆晶粒5 2之表面間;底部充 塡材料倒圓角9 3 4形成於底部晶粒5 1之互連側壁與下覆基 板500之表面間;且互連軌跡931沉積於倒圓角934上以連 -27- 201138062 接底部晶粒51至基板5 50上之第一排接合墊;此後,底部 充塡材料倒圓角936形成於倒圓角934及軌跡931上方;此 後,互連軌跡941形成於倒圓角93 2及倒圓角93 6上方以連 接上晶粒53至晶粒52,及基板500上之第一外排接合墊。 底部塡充劑可形成,其形成倒圓角之橫剖約呈正三角 形;三角形之直角三角形斜邊係可形成互連軌跡之斜面; 且三角形之垂直側於上晶粒互連緣或其附近形成具有直角 三角形斜邊之角度。倒圓角之斜面可微凹或凸,或可爲更 複雜之略微弧曲表面。底部塡充劑可爲CTE匹配以協助穏 定該總成,減少離層效應。而且,形狀如上述之底部塡充 劑可提供從晶粒對晶粒或從晶粒對基板之逐漸過渡,於晶 粒之互連緣或於晶粒之側壁之後緣銜接下覆表面之內角隅 消除陡急角度(約爲直角)過渡》在某些配置中,形成 於底部晶粒之側壁及基板之第一底部充塡材料倒圓角可支 撐第一組電互連軌跡,此等電氣互連軌跡連接底部晶粒上 之墊與基板上之第一列中的接合墊;且形成於上晶粒及底 部晶粒之側壁之第一倒圓角上之第一互連軌跡上方的額外 底部充填材料倒圓角可從上晶粒上之晶粒墊至基板上從第 —列起向外之第二列接合墊。 第10A及10B圖顯示協助限制基板上方之底部充塡材料 流動(“溢出”或“流出”)。第10A圖以局部類似於第9B圖 之部分剖視圖顯示;且第10B圖以部分平面圖顯示,其中 第10A圖之剖視圖以A-A指出。此等圖式顯示一配置,其 中晶粒5 1以晶粒在上安裝於晶粒在下安裝於基板1 〇〇〇上之 -28- 201138062 晶粒附著側之倒裝晶片晶粒9 1上方,且其中底部充塡材料 倒圓角1 9 0 0形成於晶粒5 1之側壁9 1 4 ' 9 2 4、倒裝晶片晶粒 91及從接合墊1〇2〇向內之下覆基板1000之表面1916間之內 角。倒圓角1 900提供自上晶粒(從圖式之框)延伸至從晶 粒墊5120向內之晶粒51之下覆表面,並接著自晶粒5〗互連 緣至從接合墊1 02 0向內之下覆基板表面延伸之逐漸傾斜表 面,於其上可形成電互連軌跡1 0 2 1,電連接上晶粒5 1上之 墊至基板1 020中之電路。 基板1 000之晶粒附著側爲軟焊掩模1010所覆蓋,且具 有貫穿軟焊掩模1010之溝槽壁1013之溝槽露出基板1000上 之接合墊1 020供連接。 此等圖式顯示用以限制底部充塡材料流出或溢出基板 表面之方案,其中基板1000之晶粒附著側爲軟焊掩模1〇1〇 所覆蓋。於此例子中,軟焊掩模中之溝槽具有溝槽壁1〇13 、1 〇 1 3 ’,且至少較接近晶粒之溝槽壁1 0 1 3 —般平行於基 板上之接合墊列(且一般平行於晶粒之互連側壁)。於底 部充塡材料之沉積期間,流動材料之前部大致停止於1 023 所指溝槽壁1 〇 1 3。亦即,溝槽壁1 0 1 3防止底部充塡材料溢 出或流出越過於溝槽內露出之接合墊1 020。 第1 0B圖額外顯示限制底部充塡材料流出或溢出基板 表面之額外方案。(不管基板是否有軟焊掩模,且可無或 加設溝槽方案來使用)。於此例子中,在沉積底部充塡材 料之前,堰堤1030、1030’設在底部充塡材料倒圓角之各 側的位置,以限制或防止底部充塡材料橫向,亦即,沿大 -29- 201138062 致平行於晶粒墊列之方向流動。 堰堤材料可爲以可流動形式應用之可固化材料,且此 後固化或容許固化,又,堰堤材料可具有使其在處於非固 化狀態時’ 一般比底部充塡材料較不可能流動(溢出或流 出)之性質。堰堤材料可具有例如較底部充塡材料更高的 黏度。堰堤材料及底部充塡材料可在相同固化程序中固化 ’或者’堰堤材料可在較早固化程序中固化》 可使用各種不同材料之任一者於堰堤,其具有適於特 定底部充塡材料之性質。於一特定例子中,底部充塡材料 可爲Namics公司以“Chipcoat”之名稱,像是“Chipcoat U8439-1 ”行銷者。且用於此一底部充塡材料之適當堰堤材 料可爲 Lord Thermoset 以 “CircuitSAFTM” 之名稱,像是 “CircuitSAF1^ ME-456”所行銷者。於沉積潛流材料前施加 之該堰堤材料防止該底部充塡材料之橫向流動;且二材料 可於一固化程序中固化,其可例如於1 6 5 t下對總成加熱 約1小時。其他適當材料在適當的實驗下選擇。 其他實施例在申請專利範圍中。 【圖式簡單說明】 第1圖係顯示安裝至支撐之晶粒之立體示意圖^ 第2 A圖係平面顯示如第1圖所示安裝至支撐之晶粒之 平面示意圖。 第2B及2C圖係顯示分別依B-B及C-C所指,安裝至第1 圖所示支撐之晶粒之剖視示意圖。 -30- 201138062 第3 A及3 B圖係以平面圖(第3 A圖)及剖視圖(第3 B 圖)顯示安裝及電連接至支撐之偏置晶粒堆疊之示意圖。 第3C圖係顯示第3B圖之剖視部分之示意圖。 第4 A圖係指8 -晶粒偏置堆疊例子之偏置緣之局部剖視 示意圖。 第4B圖係如第4A圖中B-B所指8-晶粒偏置堆疊之局部 剖視示意圖。 第5圖係剖視顯示根據上述另一方法構成之堆疊晶粒 總成例子之示意圖,該總成例子具有較厚底部晶粒。 第6A、6B及6C圖係剖視顯示根據上述另一方法構成 之堆疊晶粒總成例子之示意圖,該總成例子具有位於基板 之無作用晶粒。 第7A、7B及7C圖係剖視顯示根據上述另一方法構成 之堆疊晶粒總成例子之示意圖,該總成例子具有接近無電 互連之晶粒角隅之區域。 第8A、8B及8C圖係剖視顯示根據上述另一方案構成 之堆疊晶粒總成例子之示意圖,該總成例子具有形成於堆 疊中之底部晶粒與基板間之各個不同位置之底部充塡。 第9A、9B及9C圖係剖視顯示根據上述另一方案構成 之堆疊晶粒總成例子之示意圖,該總成例子具有形成於晶 粒側壁與下表面所界定內角隅之底部充塡塡角。 第10A及10B圖係顯示根據上述另一方案構成之堆疊晶 粒總成例子之示意圖,該總成例子具有限制底部充塡材料 流過基板表面之構造。第10B圖係部分平面圖,第10A圖係 -31 - 201138062 沿第1 OB圖之A-A所取剖視圖。 【主要元件符號說明】 1 0,2 0 :晶粒 1 2,3 1 1 :前側 118, 118’:接合墊 2 1 8,2 1 8 ’ :晶粒墊 1 3 , 2 3,2 3 ’ :前緣 14,16 :側壁 1 5 , 2 5 , 5 1 1 :晶粒附著膜 1 7, 27, 2 75 :邊 1 8,2 8,2 8 ’ :晶粒墊
19,21,29, 295, 1 1 9, 219,219’:歹!J 1 1 2,2 1 2 :晶粒附著側 3 1 :側壁 3 1 1 :前晶粒緣 311a, 311b :緣 3 12, 3 16:歹IJ 3 1 8 :軌跡 3 2, 3 2a :互連墊 33,33a:後表面 3 4 a - 3 4 h .偏置堆题晶 3 5, 3 5 a :前表面 3 6 :接合位置 -32- 201138062 37 :等角塗層 3 9 :晶粒安裝表面 4 0 :晶粒 46 :接合墊 47 :等角絕緣塗層 48 :墊 49 :列 51,52,53,54, 5 5, 56, 57, 5 8, 61, 62:晶粒 72,74,76:空出區域 83 :點(倒圓角) 85 :接合墊 86 :點 9 0 :倒圓角 91,941 :電互連軌跡 9 3 :上晶粒 94 :互連側壁 110, 210, 500 :基板 1 1 2,2 1 2 :晶粒附著側 1 1 8 , 2 1 8,2 1 8 ’ :接合墊 400 :支撐 4 1 8 , 9 3 1 :軌跡 5 1 1 , 5 1 8 :晶粒附著膜 914,924:側壁 916 :表面 -33- 201138062 9 3 1 :軌跡 932, 934, 936 :底部塡充劑倒圓角 1000, 1020:基板 1 0 1 0 :軟焊掩模 1 0 1 3 :溝槽壁 1021 :電互連軌跡 1030、 1030,:堰堤 -34-
Claims (1)
- 201138062 七、申請專利範圍: 1. 一種總成,包括複數個堆疊晶粒,其安裝於一支撐 上,並電互連至該支撐中之電路,其中最接近該支撐之一 堆疊晶粒具有大於另一堆疊晶粒之厚度。 2. 如申請專利範圍第1項之總成,其中,最接近該支 撐之該晶粒具有類似於另一堆疊晶粒之功能。 3 .如申請專利範圍第1項之總成,其中,最接近該支 撐之該晶粒具有異於另一堆疊晶粒之功能。 4. 一種總成,包括複數個堆疊晶粒,其安裝於一支撐 上,並電氣互連至該支撐中之電路,其中一無作用晶粒位 於該支撐與較接近該支撐之有作用之堆疊晶粒間。 5 .如申請專利範圍第4項之總成,其中,該無作用晶 粒配置成實質與該有作用之堆疊晶粒相同。 6.如申請專利範圍第5項之總成,其中,電互連不接 觸該無作用晶粒上之互連墊。 7 .如申請專利範圍第5項之總成,其中,該無作用晶 粒上之互連墊失效。 8 ·如申請專利範圍第4項之總成,其中,該無作用晶 粒包括額外晶粒。 9 ·如申請專利範圍第4項之總成,其中,該無作用晶 粒包括一“犧牲”晶粒,其因失效而無作用。 1 0 · —種總成,包括複數個堆疊晶粒,其安裝於一支 撐上並電氣互連至該支撐,其中接近該堆疊晶粒之角隅的 區域無電連接。 -35- 201138062 1 1 ·如申請專利範圍第1 0項之總成,其中,該區域包 括該晶粒之互連邊緣部分,無互連墊位於此處。 1 2 ·如申請專利範圍第1 〇項之總成,其中,該區域包 括一個或更多個犧牲墊位置。 1 3 ·如申請專利範圍第1 〇項之總成,其中,該區域包 括接近該角隅之墊,在此互連失效。 1 4 .如申請專利範圍第1 2項之總成,其中,犧牲墊位 置中之墊失效,俾該晶粒不電連接至該區域中之覆蓋互連 軌跡。 1 5 .如申請專利範圍第1 2項之總成,其中,藉由使該 支撐上對應位置之接合墊失效,防止犧牲墊位置中該墊與 對應接合墊之連接。 1 6 ·如申請專利範圍第1 2項之總成,其中,藉由將基 板設計成無接合墊位在該支撐上的對應位置,防止犧牲墊 位置中該墊與對應接合墊之連接。 17· —種總成之製造方法,該總成包括複數個堆疊晶 粒’其安裝於一支撐上並使用可固化互連材料電氣互連至 該支撐’該總成被模製或封裝,該方法包括於模製或封裝 程序後,完成該互連材料之固化。 18.如申請專利範圍第17項之方法,又包括於模製或 封裝程序前及以可流動形式沉積該互連材料後,局部固化 該互連材料。 19_如申請專利範圍第17項之方法,又包括於模製或 封裝程序後,在最後固化期間預施應力於模製或封裝之總 -36- 201138062 成,以提供抵消之翹曲或彎曲於構造中。 2 0 .如申請專利範圍第1 9項之方法’包括於模製或封 裝期間,撓曲該總成,以形成凸出之上晶粒表面,並在最 後固化期間保持該總成於此狀態。 2 1 .如申請專利範圍第1 9項之方法,包括於模製或封 裝期間,撓曲該總成,以形成凹入之上晶粒表面,並在最 後固化期間,保持該總成於此狀態。 2 2. —種總成,包括複數個堆疊晶粒,其安裝於一支 撐上,並電氣互連至該支撐,其中電連接指向晶粒墊或接 合墊上之位置,在該位置處預期有更強韌的電連接。 2 3 . —種總成之製造方法,該總成包括複數個堆疊晶 粒,其安裝於一支撐上並電氣互連至該支撐,其中互連材 料特別是施加於晶粒墊或接合墊上之接觸位置,在該位置 處預期有強制電連接。 24. —種總成之製造方法,該總成包括複數個堆疊晶 粒’其安裝於一支撐上並電氣互連至該支撐,且其中該總 成待封裝’該方法包括於模製或封裝程序前,以聚合物膜 塗佈互連軌跡。 25. 如申請專利範圍第24項之方法,其中該聚合物包 括有機聚合物。 2 6 .如申請專利範圍第2 5項之方法,其中該聚合物包 括對二甲苯基。 27.如申請專利範圍第25項之方法,其中該聚合物包 括矽氧烷彈性體。 -37- 201138062 28_ —種總成,包括複數個堆疊晶粒,其安裝於—支 擦上,並電氣互連至該支撐,其中底部塡充劑形成於該基 板與較接近該基板之堆#晶粒間。 29. 如申請專利範圍第28項之總成,其中該底部塡充 劑沉積於較接近該基板之該堆疊晶粒之一或更多邊緣附近 〇 30. 如申請專利範圍第29項之總成,其中該底部塡充 劑沉積於個別點。 3 1 .如申請專利範圍第2 9項之總成,其中該底部塡充 劑沿該邊緣隔間沉積。 3 2 _如申請專利範圍第2 9項之總成,其中該底部塡充 劑沿該邊緣連續沉積。 33. —種總成,包括複數個堆疊晶粒,其安裝於一支 撐上並電氣互連至該支撐,其中底部塡充劑沉積於由晶粒 側壁與下表面形成之內角。 34. 如申請專利範圍第33項之總成,其中,該晶粒側 壁包括較接近該支撐之堆疊晶粒之互連側壁。 35. 如申請專利範圍第34項之總成,其中,該下表面 包括該支撐的晶粒附著側之區域,在該支撐上之接合墊內 且鄰近該晶粒側壁。 3 6 .如申請專利範圍第3 3項之總成,其中,該晶粒側 壁包括較遠離該支撐之晶粒之互連側壁。 3 7 .如申請專利範圍第3 6項之總成,其中,該下表面 包括下方晶粒之前側之電絕緣區域,在該下方晶粒上之晶 -38- 201138062 粒墊內,並鄰近遠離該支撐之該晶粒之互連側壁。 3 8 .如申請專利範圍第3 3項之總成,其中,該晶粒側 壁包括倒裝晶粒之側壁,於該基板上,該倒裝晶粒之位向 成晶粒在下,並於該倒裝晶粒之涵蓋表面中,電連接至該 支撐,或諸如晶粒比例封裝或BGA封裝之封裝側,且該下 表面包括該支撐的晶粒附著側之電絕緣區域,在該支撐上 之接合墊內且鄰近該倒裝晶粒側壁或封裝側。 3 9 .如申請專利範圍第3 3項之總成,其中,該側壁包 括堆疊於倒裝晶粒上方之晶粒之互連側壁,且該下表面包 括該下方之倒裝晶粒之背側之電絕緣區域。 4 0.如申請專利範圍第33項之總成,其中,該底部塡 充劑形成一橫剖面大致成直角三角形之倒圓角,提供一傾 斜表面,於其上可形成互連軌跡。 4 1 .如申請專利範圍第40項之總成,其中,該倒圓角 之該傾斜表面略凹或凸,或爲更複雜之略微弧形表面。 42 ·如申請專利範圍第3 3項之總成,其中,形成於下 晶粒之側壁及基板之第一底部塡充劑倒圓角支撐第一組電 互連軌跡,該等電互連軌跡連接該晶粒上之墊與該基板上 第一列之接合墊。 43 .如申請專利範圍第42項之總成,其中,形成於上 晶粒的側壁及下晶粒之第一倒圓角上第一互連軌跡之上的 額外底部塡充劑倒圓角從該上晶粒上之該晶粒墊至該支撐 上第一列外,第二列之接合墊,支撐第二組互連軌跡。 44 ·如申請專利範圍第3 3項之總成,又包括一堰堤, -39- 201138062 以限制或防止該底部塡充劑材料沿大致平行於該基板上之 接合墊列之方向流動。 4 5 .如申請專利範圍第4 4項之總成,其中,該堰堤材 料包括以可流動形式施加之可固化材料,且其在此後固化 或容許固化。 4 6 ·如申請專利範圍第3 3項之總成,其中,該支撐之 晶粒附著側覆蓋軟焊掩模,又包括位於該軟焊掩模中之一 溝槽’其具有一溝槽壁,該溝槽壁大致平行於該基板上之 接合墊列,並位於該等接合墊與該晶粒側壁間。 -40-
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US28058409P | 2009-11-04 | 2009-11-04 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201138062A true TW201138062A (en) | 2011-11-01 |
TWI544604B TWI544604B (zh) | 2016-08-01 |
Family
ID=43970756
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW099137634A TWI544604B (zh) | 2009-11-04 | 2010-11-02 | 具有降低應力電互連的堆疊晶粒總成 |
Country Status (3)
Country | Link |
---|---|
US (1) | US8912661B2 (zh) |
TW (1) | TWI544604B (zh) |
WO (1) | WO2011056987A2 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI467711B (zh) * | 2013-09-10 | 2015-01-01 | Chipbond Technology Corp | 半導體結構 |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8829677B2 (en) | 2010-10-14 | 2014-09-09 | Invensas Corporation | Semiconductor die having fine pitch electrical interconnects |
US8587088B2 (en) | 2011-02-17 | 2013-11-19 | Apple Inc. | Side-mounted controller and methods for making the same |
KR20120135626A (ko) * | 2011-06-07 | 2012-12-17 | 삼성전자주식회사 | 반도체 칩 패키지의 제조 방법 |
US20130075892A1 (en) * | 2011-09-27 | 2013-03-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for Three Dimensional Integrated Circuit Fabrication |
US9196588B2 (en) * | 2011-11-04 | 2015-11-24 | Invensas Corporation | EMI shield |
KR101959395B1 (ko) * | 2012-07-06 | 2019-03-18 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
US8847412B2 (en) | 2012-11-09 | 2014-09-30 | Invensas Corporation | Microelectronic assembly with thermally and electrically conductive underfill |
CN103474421B (zh) * | 2013-08-30 | 2016-10-12 | 晟碟信息科技(上海)有限公司 | 高产量半导体装置 |
KR102107961B1 (ko) | 2013-11-14 | 2020-05-28 | 삼성전자 주식회사 | 반도체 장치 및 이의 제조 방법 |
KR102389816B1 (ko) * | 2015-08-25 | 2022-04-22 | 삼성전자주식회사 | 반도체 소자 및 반도체 소자의 패턴 형성 방법 |
US10790172B2 (en) * | 2018-08-17 | 2020-09-29 | Jabil Inc. | Apparatus, system, and method of providing a ramped interconnect for semiconductor fabrication |
US10797035B1 (en) * | 2019-04-02 | 2020-10-06 | Sandisk Technologies Llc | Bonded assembly containing side bonding structures and methods of manufacturing the same |
US11024604B2 (en) * | 2019-08-10 | 2021-06-01 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor devices and methods of manufacturing semiconductor devices |
US11373956B2 (en) * | 2020-01-14 | 2022-06-28 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and method of manufacturing the same |
US11456272B2 (en) | 2020-09-11 | 2022-09-27 | Western Digital Technologies, Inc. | Straight wirebonding of silicon dies |
TW202224285A (zh) * | 2020-11-02 | 2022-06-16 | 美商山姆科技公司 | 撓曲電路和與其相關之電氣通訊組件 |
Family Cites Families (203)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53147968A (en) | 1977-05-30 | 1978-12-23 | Hitachi Ltd | Thick film circuit board |
US4323914A (en) | 1979-02-01 | 1982-04-06 | International Business Machines Corporation | Heat transfer structure for integrated circuit package |
US4363076A (en) | 1980-12-29 | 1982-12-07 | Honeywell Information Systems Inc. | Integrated circuit package |
US4500905A (en) | 1981-09-30 | 1985-02-19 | Tokyo Shibaura Denki Kabushiki Kaisha | Stacked semiconductor device with sloping sides |
JPS6149432A (ja) | 1984-08-18 | 1986-03-11 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
US5138438A (en) | 1987-06-24 | 1992-08-11 | Akita Electronics Co. Ltd. | Lead connections means for stacked tab packaged IC chips |
JPH063819B2 (ja) | 1989-04-17 | 1994-01-12 | セイコーエプソン株式会社 | 半導体装置の実装構造および実装方法 |
US5200362A (en) | 1989-09-06 | 1993-04-06 | Motorola, Inc. | Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film |
US5334872A (en) | 1990-01-29 | 1994-08-02 | Mitsubishi Denki Kabushiki Kaisha | Encapsulated semiconductor device having a hanging heat spreading plate electrically insulated from the die pad |
US5311401A (en) | 1991-07-09 | 1994-05-10 | Hughes Aircraft Company | Stacked chip assembly and manufacturing method therefor |
US5218234A (en) * | 1991-12-23 | 1993-06-08 | Motorola, Inc. | Semiconductor device with controlled spread polymeric underfill |
US5331591A (en) | 1993-02-01 | 1994-07-19 | At&T Bell Laboratories | Electronic module including a programmable memory |
FR2704690B1 (fr) | 1993-04-27 | 1995-06-23 | Thomson Csf | Procédé d'encapsulation de pastilles semi-conductrices, dispositif obtenu par ce procédé et application à l'interconnexion de pastilles en trois dimensions. |
US7073254B2 (en) | 1993-11-16 | 2006-07-11 | Formfactor, Inc. | Method for mounting a plurality of spring contact elements |
US5502333A (en) | 1994-03-30 | 1996-03-26 | International Business Machines Corporation | Semiconductor stack structures and fabrication/sparing methods utilizing programmable spare circuit |
US5891761A (en) | 1994-06-23 | 1999-04-06 | Cubic Memory, Inc. | Method for forming vertical interconnect process for silicon segments with thermally conductive epoxy preform |
US6255726B1 (en) | 1994-06-23 | 2001-07-03 | Cubic Memory, Inc. | Vertical interconnect process for silicon segments with dielectric isolation |
US5698895A (en) | 1994-06-23 | 1997-12-16 | Cubic Memory, Inc. | Silicon segment programming method and apparatus |
US6228686B1 (en) | 1995-09-18 | 2001-05-08 | Tessera, Inc. | Method of fabricating a microelectronic assembly using sheets with gaps to define lead regions |
US5434745A (en) | 1994-07-26 | 1995-07-18 | White Microelectronics Div. Of Bowmar Instrument Corp. | Stacked silicon die carrier assembly |
JP3233535B2 (ja) | 1994-08-15 | 2001-11-26 | 株式会社東芝 | 半導体装置及びその製造方法 |
US5616953A (en) | 1994-09-01 | 1997-04-01 | Micron Technology, Inc. | Lead frame surface finish enhancement |
US5619476A (en) | 1994-10-21 | 1997-04-08 | The Board Of Trustees Of The Leland Stanford Jr. Univ. | Electrostatic ultrasonic transducer |
US5466634A (en) | 1994-12-20 | 1995-11-14 | International Business Machines Corporation | Electronic modules with interconnected surface metallization layers and fabrication methods therefore |
DE69621983T2 (de) | 1995-04-07 | 2002-11-21 | Shinko Electric Ind Co | Struktur und Verfahren zur Montage eines Halbleiterchips |
US5721151A (en) | 1995-06-07 | 1998-02-24 | Lsi Logic Corporation | Method of fabricating a gate array integrated circuit including interconnectable macro-arrays |
US5648684A (en) | 1995-07-26 | 1997-07-15 | International Business Machines Corporation | Endcap chip with conductive, monolithic L-connect for multichip stack |
US5691248A (en) | 1995-07-26 | 1997-11-25 | International Business Machines Corporation | Methods for precise definition of integrated circuit chip edges |
US5538758A (en) | 1995-10-27 | 1996-07-23 | Specialty Coating Systems, Inc. | Method and apparatus for the deposition of parylene AF4 onto semiconductor wafers |
JP3527350B2 (ja) | 1996-02-01 | 2004-05-17 | 株式会社ルネサステクノロジ | 半導体装置 |
US7166495B2 (en) | 1996-02-20 | 2007-01-23 | Micron Technology, Inc. | Method of fabricating a multi-die semiconductor package assembly |
US5880530A (en) | 1996-03-29 | 1999-03-09 | Intel Corporation | Multiregion solder interconnection structure |
US6784023B2 (en) | 1996-05-20 | 2004-08-31 | Micron Technology, Inc. | Method of fabrication of stacked semiconductor devices |
JP3685585B2 (ja) | 1996-08-20 | 2005-08-17 | 三星電子株式会社 | 半導体のパッケージ構造 |
US6034438A (en) | 1996-10-18 | 2000-03-07 | The Regents Of The University Of California | L-connect routing of die surface pads to the die edge for stacking in a 3D array |
US6962829B2 (en) | 1996-10-31 | 2005-11-08 | Amkor Technology, Inc. | Method of making near chip size integrated circuit package |
KR100447035B1 (ko) | 1996-11-21 | 2004-09-07 | 가부시키가이샤 히타치세이사쿠쇼 | 반도체 장치의 제조방법 |
US5910687A (en) | 1997-01-24 | 1999-06-08 | Chipscale, Inc. | Wafer fabrication of die-bottom contacts for electronic devices |
JP3779789B2 (ja) * | 1997-01-31 | 2006-05-31 | 株式会社ルネサステクノロジ | 半導体装置およびその製造方法 |
JP2980046B2 (ja) | 1997-02-03 | 1999-11-22 | 日本電気株式会社 | 半導体装置の実装構造および実装方法 |
US5879965A (en) | 1997-06-19 | 1999-03-09 | Micron Technology, Inc. | Plastic lead frames for semiconductor devices, packages including same, and methods of fabrication |
US6271598B1 (en) | 1997-07-29 | 2001-08-07 | Cubic Memory, Inc. | Conductive epoxy flip-chip on chip |
EP1029360A4 (en) | 1997-08-21 | 2006-04-12 | Vertical Circuits Inc | VERTICAL INTERCONNECTION METHOD FOR SILICON SEGMENTS WITH DIELECTRIC INSULATION |
US5888850A (en) | 1997-09-29 | 1999-03-30 | International Business Machines Corporation | Method for providing a protective coating and electronic package utilizing same |
US6441487B2 (en) | 1997-10-20 | 2002-08-27 | Flip Chip Technologies, L.L.C. | Chip scale package using large ductile solder balls |
US6138349A (en) | 1997-12-18 | 2000-10-31 | Vlt Corporation | Protective coating for an electronic device |
JP3891678B2 (ja) | 1998-03-11 | 2007-03-14 | 松下電器産業株式会社 | 半導体装置 |
US6315856B1 (en) | 1998-03-19 | 2001-11-13 | Kabushiki Kaisha Toshiba | Method of mounting electronic component |
DE19833713C1 (de) | 1998-07-27 | 2000-05-04 | Siemens Ag | Verfahren zur Herstellung eines Verbundkörpers aus wenigstens zwei integrierten Schaltungen |
JP3516592B2 (ja) | 1998-08-18 | 2004-04-05 | 沖電気工業株式会社 | 半導体装置およびその製造方法 |
US6153929A (en) | 1998-08-21 | 2000-11-28 | Micron Technology, Inc. | Low profile multi-IC package connector |
US6084297A (en) | 1998-09-03 | 2000-07-04 | Micron Technology, Inc. | Cavity ball grid array apparatus |
US6175158B1 (en) | 1998-09-08 | 2001-01-16 | Lucent Technologies Inc. | Interposer for recessed flip-chip package |
US6303977B1 (en) | 1998-12-03 | 2001-10-16 | Texas Instruments Incorporated | Fully hermetic semiconductor chip, including sealed edge sides |
US6297657B1 (en) | 1999-01-11 | 2001-10-02 | Wentworth Laboratories, Inc. | Temperature compensated vertical pin probing device |
JP2000269411A (ja) | 1999-03-17 | 2000-09-29 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
EP1041624A1 (en) | 1999-04-02 | 2000-10-04 | Interuniversitair Microelektronica Centrum Vzw | Method of transferring ultra-thin substrates and application of the method to the manufacture of a multilayer thin film device |
US6326689B1 (en) | 1999-07-26 | 2001-12-04 | Stmicroelectronics, Inc. | Backside contact for touchchip |
US6338980B1 (en) | 1999-08-13 | 2002-01-15 | Citizen Watch Co., Ltd. | Method for manufacturing chip-scale package and manufacturing IC chip |
KR100533673B1 (ko) | 1999-09-03 | 2005-12-05 | 세이코 엡슨 가부시키가이샤 | 반도체 장치 및 그 제조 방법, 회로 기판 및 전자 기기 |
US6376904B1 (en) | 1999-12-23 | 2002-04-23 | Rambus Inc. | Redistributed bond pads in stacked integrated circuit die package |
US6621155B1 (en) | 1999-12-23 | 2003-09-16 | Rambus Inc. | Integrated circuit device having stacked dies and impedance balanced transmission lines |
JP2001183415A (ja) | 1999-12-28 | 2001-07-06 | Molex Inc | ベアチップ用icソケット |
JP3879351B2 (ja) | 2000-01-27 | 2007-02-14 | セイコーエプソン株式会社 | 半導体チップの製造方法 |
DE10004941A1 (de) | 2000-02-06 | 2001-08-09 | Reimer Offen | Temperierter Probennehmer für Flüssigkeiten |
JP2001223323A (ja) | 2000-02-10 | 2001-08-17 | Mitsubishi Electric Corp | 半導体装置 |
CA2399842C (en) | 2000-03-02 | 2006-11-14 | Microchips, Inc. | Microfabricated devices for the storage and selective exposure of chemicals and devices |
US6335224B1 (en) | 2000-05-16 | 2002-01-01 | Sandia Corporation | Protection of microelectronic devices during packaging |
US6956283B1 (en) | 2000-05-16 | 2005-10-18 | Peterson Kenneth A | Encapsulants for protecting MEMS devices during post-packaging release etch |
US6384473B1 (en) | 2000-05-16 | 2002-05-07 | Sandia Corporation | Microelectronic device package with an integral window |
US6717245B1 (en) | 2000-06-02 | 2004-04-06 | Micron Technology, Inc. | Chip scale packages performed by wafer level processing |
US7355126B2 (en) * | 2000-06-16 | 2008-04-08 | Matsushita Electric Industrial Co., Ltd. | Electronic parts packaging method and electronic parts package |
US6525413B1 (en) | 2000-07-12 | 2003-02-25 | Micron Technology, Inc. | Die to die connection method and assemblies and packages including dice so connected |
JP4361670B2 (ja) * | 2000-08-02 | 2009-11-11 | 富士通マイクロエレクトロニクス株式会社 | 半導体素子積層体、半導体素子積層体の製造方法、及び半導体装置 |
US6593648B2 (en) | 2000-08-31 | 2003-07-15 | Seiko Epson Corporation | Semiconductor device and method of making the same, circuit board and electronic equipment |
JP3405456B2 (ja) | 2000-09-11 | 2003-05-12 | 沖電気工業株式会社 | 半導体装置,半導体装置の製造方法,スタック型半導体装置及びスタック型半導体装置の製造方法 |
SG97938A1 (en) | 2000-09-21 | 2003-08-20 | Micron Technology Inc | Method to prevent die attach adhesive contamination in stacked chips |
US6580165B1 (en) | 2000-11-16 | 2003-06-17 | Fairchild Semiconductor Corporation | Flip chip with solder pre-plated leadframe including locating holes |
DE10103186B4 (de) | 2001-01-24 | 2007-01-18 | Infineon Technologies Ag | Verfahren zur Herstellung eines elektronischen Bauteils mit einem Halbleiter-Chip |
US20020100600A1 (en) | 2001-01-26 | 2002-08-01 | Albert Douglas M. | Stackable microcircuit layer formed from a plastic encapsulated microcircuit and method of making the same |
JP2002305286A (ja) | 2001-02-01 | 2002-10-18 | Mitsubishi Electric Corp | 半導体モジュールおよび電子部品 |
US6910268B2 (en) | 2001-03-27 | 2005-06-28 | Formfactor, Inc. | Method for fabricating an IC interconnect system including an in-street integrated circuit wafer via |
US7115986B2 (en) | 2001-05-02 | 2006-10-03 | Micron Technology, Inc. | Flexible ball grid array chip scale packages |
US6973718B2 (en) | 2001-05-30 | 2005-12-13 | Microchips, Inc. | Methods for conformal coating and sealing microchip reservoir devices |
US6900528B2 (en) | 2001-06-21 | 2005-05-31 | Micron Technology, Inc. | Stacked mass storage flash memory package |
US20030006493A1 (en) | 2001-07-04 | 2003-01-09 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and manufacturing method thereof |
JP2003023138A (ja) | 2001-07-10 | 2003-01-24 | Toshiba Corp | メモリチップ及びこれを用いたcocデバイス、並びに、これらの製造方法 |
KR100394808B1 (ko) | 2001-07-19 | 2003-08-14 | 삼성전자주식회사 | 웨이퍼 레벨 적층 칩 패키지 및 그 제조 방법 |
US20030038353A1 (en) | 2001-08-23 | 2003-02-27 | Derderian James M. | Assemblies including stacked semiconductor devices separated by discrete conductive elements therebetween, packages including the assemblies, and methods |
US7518223B2 (en) | 2001-08-24 | 2009-04-14 | Micron Technology, Inc. | Semiconductor devices and semiconductor device assemblies including a nonconfluent spacer layer |
US20030038356A1 (en) | 2001-08-24 | 2003-02-27 | Derderian James M | Semiconductor devices including stacking spacers thereon, assemblies including the semiconductor devices, and methods |
US6569709B2 (en) | 2001-10-15 | 2003-05-27 | Micron Technology, Inc. | Assemblies including stacked semiconductor devices separated a distance defined by adhesive material interposed therebetween, packages including the assemblies, and methods |
US6747348B2 (en) | 2001-10-16 | 2004-06-08 | Micron Technology, Inc. | Apparatus and method for leadless packaging of semiconductor devices |
JP2003142518A (ja) | 2001-11-02 | 2003-05-16 | Nec Electronics Corp | 半導体製造装置、半導体製造方法、半導体装置及び電子装置 |
US6611052B2 (en) | 2001-11-16 | 2003-08-26 | Micron Technology, Inc. | Wafer level stackable semiconductor package |
US6627509B2 (en) | 2001-11-26 | 2003-09-30 | Delaware Capital Formation, Inc. | Surface flashover resistant capacitors and method for producing same |
JP2003163324A (ja) | 2001-11-27 | 2003-06-06 | Nec Corp | ユニット半導体装置及びその製造方法並びに3次元積層型半導体装置 |
US6750547B2 (en) | 2001-12-26 | 2004-06-15 | Micron Technology, Inc. | Multi-substrate microelectronic packages and methods for manufacture |
TW544882B (en) | 2001-12-31 | 2003-08-01 | Megic Corp | Chip package structure and process thereof |
US7190060B1 (en) | 2002-01-09 | 2007-03-13 | Bridge Semiconductor Corporation | Three-dimensional stacked semiconductor package device with bent and flat leads and method of making same |
US6607941B2 (en) | 2002-01-11 | 2003-08-19 | National Semiconductor Corporation | Process and structure improvements to shellcase style packaging technology |
US6802446B2 (en) | 2002-02-01 | 2004-10-12 | Delphi Technologies, Inc. | Conductive adhesive material with metallurgically-bonded conductive particles |
KR100486832B1 (ko) | 2002-02-06 | 2005-05-03 | 삼성전자주식회사 | 반도체 칩과 적층 칩 패키지 및 그 제조 방법 |
US6908784B1 (en) | 2002-03-06 | 2005-06-21 | Micron Technology, Inc. | Method for fabricating encapsulated semiconductor components |
USD475981S1 (en) | 2002-03-29 | 2003-06-17 | Mitsubishi Denki Kabushiki Kaisha | Integrated circuits substrate |
US7340181B1 (en) | 2002-05-13 | 2008-03-04 | National Semiconductor Corporation | Electrical die contact structure and fabrication method |
US6756252B2 (en) * | 2002-07-17 | 2004-06-29 | Texas Instrument Incorporated | Multilayer laser trim interconnect method |
US20040036170A1 (en) | 2002-08-20 | 2004-02-26 | Lee Teck Kheng | Double bumping of flexible substrate for first and second level interconnects |
JP4081666B2 (ja) | 2002-09-24 | 2008-04-30 | セイコーエプソン株式会社 | 半導体装置及びその製造方法、回路基板並びに電子機器 |
US7034387B2 (en) | 2003-04-04 | 2006-04-25 | Chippac, Inc. | Semiconductor multipackage module including processor and memory package assemblies |
US6656827B1 (en) | 2002-10-17 | 2003-12-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Electrical performance enhanced wafer level chip scale package with ground |
US6667543B1 (en) | 2002-10-29 | 2003-12-23 | Motorola, Inc. | Optical sensor package |
US7268005B2 (en) | 2002-10-30 | 2007-09-11 | Finisar Corporation | Apparatus and method for stacking laser bars for uniform facet coating |
TWI227550B (en) | 2002-10-30 | 2005-02-01 | Sanyo Electric Co | Semiconductor device manufacturing method |
JP2004153130A (ja) | 2002-10-31 | 2004-05-27 | Olympus Corp | 半導体装置及びその製造方法 |
JP2004158536A (ja) | 2002-11-05 | 2004-06-03 | Fujitsu Ltd | 半導体装置及び半導体装置の製造方法 |
JP4381675B2 (ja) | 2002-11-21 | 2009-12-09 | 富士通株式会社 | 半導体装置及びその製造方法、該半導体装置に係る測定用治具 |
US6881610B2 (en) | 2003-01-02 | 2005-04-19 | Intel Corporation | Method and apparatus for preparing a plurality of dice in wafers |
JP2004214548A (ja) | 2003-01-08 | 2004-07-29 | Mitsubishi Electric Corp | 部品内蔵基板型モジュール、それを搭載した基板、部品内蔵基板型モジュールの製造方法、および部品内蔵基板型モジュールを搭載した基板の製造方法 |
US7035113B2 (en) | 2003-01-30 | 2006-04-25 | Endicott Interconnect Technologies, Inc. | Multi-chip electronic package having laminate carrier and method of making same |
KR101186919B1 (ko) | 2003-02-06 | 2012-10-02 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 표시장치의 제조 방법 |
KR100499289B1 (ko) | 2003-02-07 | 2005-07-04 | 삼성전자주식회사 | 패턴 리드를 갖는 반도체 패키지 및 그 제조 방법 |
JP2004281538A (ja) | 2003-03-13 | 2004-10-07 | Seiko Epson Corp | 電子装置及びその製造方法、回路基板並びに電子機器 |
JP3772984B2 (ja) | 2003-03-13 | 2006-05-10 | セイコーエプソン株式会社 | 電子装置及びその製造方法、回路基板並びに電子機器 |
TWI231023B (en) | 2003-05-27 | 2005-04-11 | Ind Tech Res Inst | Electronic packaging with three-dimensional stack and assembling method thereof |
EP1636842B1 (en) | 2003-06-03 | 2011-08-17 | Casio Computer Co., Ltd. | Stackable semiconductor device and method of manufacturing the same |
JP2005005380A (ja) | 2003-06-10 | 2005-01-06 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
JP3842759B2 (ja) | 2003-06-12 | 2006-11-08 | 株式会社東芝 | 三次元実装半導体モジュール及び三次元実装半導体システム |
US6972480B2 (en) | 2003-06-16 | 2005-12-06 | Shellcase Ltd. | Methods and apparatus for packaging integrated circuit devices |
TWM243783U (en) * | 2003-06-30 | 2004-09-11 | Innolux Display Corp | Structure of chip on glass |
JP2007528120A (ja) | 2003-07-03 | 2007-10-04 | テッセラ テクノロジーズ ハンガリー コルラートルト フェレロェセーギュー タールシャシャーグ | 集積回路装置をパッケージングする方法及び装置 |
JP3718205B2 (ja) | 2003-07-04 | 2005-11-24 | 松下電器産業株式会社 | チップ積層型半導体装置およびその製造方法 |
KR20050009036A (ko) | 2003-07-15 | 2005-01-24 | 삼성전자주식회사 | 적층 패키지 및 그 제조 방법 |
SG120123A1 (en) | 2003-09-30 | 2006-03-28 | Micron Technology Inc | Castellated chip-scale packages and methods for fabricating the same |
US20050067694A1 (en) | 2003-09-30 | 2005-03-31 | Pon Florence R. | Spacerless die stacking |
US7064010B2 (en) | 2003-10-20 | 2006-06-20 | Micron Technology, Inc. | Methods of coating and singulating wafers |
US7064069B2 (en) | 2003-10-21 | 2006-06-20 | Micron Technology, Inc. | Substrate thinning including planarization |
JP4198072B2 (ja) | 2004-01-23 | 2008-12-17 | シャープ株式会社 | 半導体装置、光学装置用モジュール及び半導体装置の製造方法 |
DE102004008135A1 (de) | 2004-02-18 | 2005-09-22 | Infineon Technologies Ag | Halbleiterbauteil mit einem Stapel aus Halbleiterchips und Verfahren zur Herstellung desselben |
JP3811160B2 (ja) | 2004-03-09 | 2006-08-16 | 株式会社東芝 | 半導体装置 |
US7095105B2 (en) | 2004-03-23 | 2006-08-22 | Texas Instruments Incorporated | Vertically stacked semiconductor device |
KR100890073B1 (ko) | 2004-03-23 | 2009-03-24 | 텍사스 인스트루먼츠 인코포레이티드 | 수직으로 적층된 반도체 장치 및 그 제조 방법 |
US7245021B2 (en) | 2004-04-13 | 2007-07-17 | Vertical Circuits, Inc. | Micropede stacked die component assembly |
US7215018B2 (en) | 2004-04-13 | 2007-05-08 | Vertical Circuits, Inc. | Stacked die BGA or LGA component assembly |
US20050251031A1 (en) | 2004-05-06 | 2005-11-10 | Scimed Life Systems, Inc. | Apparatus and construction for intravascular device |
US7239020B2 (en) | 2004-05-06 | 2007-07-03 | Avago Technologies Wireless Ip (Singapore) Pte. Ltd. | Multi-mode integrated circuit structure |
TWI236110B (en) | 2004-06-25 | 2005-07-11 | Advanced Semiconductor Eng | Flip chip on leadframe package and method for manufacturing the same |
JP2006019493A (ja) | 2004-07-01 | 2006-01-19 | Disco Abrasive Syst Ltd | ウェーハの分割方法 |
DE102004039906A1 (de) | 2004-08-18 | 2005-08-18 | Infineon Technologies Ag | Verfahren zur Herstellung eines elektronischen Bauelements sowie ein elektronisches Bauelement mit mindestens zwei integrierten Bausteinen |
US7768795B2 (en) | 2004-09-08 | 2010-08-03 | Panasonic Corporation | Electronic circuit device, electronic device using the same, and method for manufacturing the same |
TWI288448B (en) | 2004-09-10 | 2007-10-11 | Toshiba Corp | Semiconductor device and method of manufacturing the same |
US7566634B2 (en) | 2004-09-24 | 2009-07-28 | Interuniversitair Microelektronica Centrum (Imec) | Method for chip singulation |
US8324725B2 (en) | 2004-09-27 | 2012-12-04 | Formfactor, Inc. | Stacked die module |
DE102004052921A1 (de) | 2004-10-29 | 2006-05-11 | Infineon Technologies Ag | Verfahren zur Herstellung von Halbleiterbauelementen mit externen Kontaktierungen |
JP2006140294A (ja) | 2004-11-11 | 2006-06-01 | Fujitsu Ltd | 半導体基板、半導体装置の製造方法及び半導体装置の試験方法 |
JP4613590B2 (ja) * | 2004-11-16 | 2011-01-19 | セイコーエプソン株式会社 | 実装基板及び電子機器 |
KR100626618B1 (ko) | 2004-12-10 | 2006-09-25 | 삼성전자주식회사 | 반도체 칩 적층 패키지 및 제조 방법 |
US20060138626A1 (en) | 2004-12-29 | 2006-06-29 | Tessera, Inc. | Microelectronic packages using a ceramic substrate having a window and a conductive surface region |
US7326592B2 (en) | 2005-04-04 | 2008-02-05 | Infineon Technologies Ag | Stacked die package |
US7371676B2 (en) | 2005-04-08 | 2008-05-13 | Micron Technology, Inc. | Method for fabricating semiconductor components with through wire interconnects |
US7208345B2 (en) | 2005-05-11 | 2007-04-24 | Infineon Technologies Ag | Method of manufacturing a semiconductor device comprising stacked chips and a corresponding semiconductor device |
US20060267173A1 (en) | 2005-05-26 | 2006-11-30 | Sandisk Corporation | Integrated circuit package having stacked integrated circuits and method therefor |
US7351657B2 (en) | 2005-06-10 | 2008-04-01 | Honeywell International Inc. | Method and apparatus for applying external coating to grid array packages for increased reliability and performance |
JP2006351793A (ja) | 2005-06-15 | 2006-12-28 | Fujitsu Ltd | 半導体装置 |
US7196262B2 (en) | 2005-06-20 | 2007-03-27 | Solyndra, Inc. | Bifacial elongated solar cell devices |
KR100629498B1 (ko) | 2005-07-15 | 2006-09-28 | 삼성전자주식회사 | 마이크로 패키지, 멀티―스택 마이크로 패키지 및 이들의제조방법 |
US7452743B2 (en) | 2005-09-01 | 2008-11-18 | Aptina Imaging Corporation | Microelectronic imaging units and methods of manufacturing microelectronic imaging units at the wafer level |
JP2007073803A (ja) | 2005-09-08 | 2007-03-22 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2007134486A (ja) | 2005-11-10 | 2007-05-31 | Toshiba Corp | 積層型半導体装置及びその製造方法 |
US7981726B2 (en) | 2005-12-12 | 2011-07-19 | Intel Corporation | Copper plating connection for multi-die stack in substrate package |
US7408243B2 (en) | 2005-12-14 | 2008-08-05 | Honeywell International Inc. | High temperature package flip-chip bonding to ceramic |
US20070158799A1 (en) | 2005-12-29 | 2007-07-12 | Chin-Tien Chiu | Interconnected IC packages with vertical SMT pads |
US20070158807A1 (en) | 2005-12-29 | 2007-07-12 | Daoqiang Lu | Edge interconnects for die stacking |
TWI284971B (en) | 2006-01-26 | 2007-08-01 | Siliconware Precision Industries Co Ltd | Multichip stack structure |
SG135074A1 (en) | 2006-02-28 | 2007-09-28 | Micron Technology Inc | Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices |
US8710675B2 (en) | 2006-02-21 | 2014-04-29 | Stats Chippac Ltd. | Integrated circuit package system with bonding lands |
US7429521B2 (en) * | 2006-03-30 | 2008-09-30 | Intel Corporation | Capillary underfill of stacked wafers |
US7732912B2 (en) | 2006-08-11 | 2010-06-08 | Tessera, Inc. | Semiconductor chip packages and assemblies with chip carrier units |
US7888185B2 (en) | 2006-08-17 | 2011-02-15 | Micron Technology, Inc. | Semiconductor device assemblies and systems including at least one conductive pathway extending around a side of at least one semiconductor device |
JP2008071953A (ja) * | 2006-09-14 | 2008-03-27 | Nec Electronics Corp | 半導体装置 |
US7829438B2 (en) | 2006-10-10 | 2010-11-09 | Tessera, Inc. | Edge connect wafer level stacking |
US7901989B2 (en) | 2006-10-10 | 2011-03-08 | Tessera, Inc. | Reconstituted wafer level stacking |
US8513789B2 (en) | 2006-10-10 | 2013-08-20 | Tessera, Inc. | Edge connect wafer level stacking with leads extending along edges |
KR100813624B1 (ko) | 2006-10-25 | 2008-03-17 | 삼성전자주식회사 | 반도체 패키지 및 그 제조방법 |
US8154881B2 (en) | 2006-11-13 | 2012-04-10 | Telecommunication Systems, Inc. | Radiation-shielded semiconductor assembly |
US7952195B2 (en) | 2006-12-28 | 2011-05-31 | Tessera, Inc. | Stacked packages with bridging traces |
US20080173792A1 (en) | 2007-01-23 | 2008-07-24 | Advanced Chip Engineering Technology Inc. | Image sensor module and the method of the same |
WO2008094749A1 (en) | 2007-01-29 | 2008-08-07 | Digital Angel Corporation | Micron-scale implatable transponder |
US20080203566A1 (en) | 2007-02-27 | 2008-08-28 | Chao-Yuan Su | Stress buffer layer for packaging process |
JP2008236688A (ja) | 2007-03-23 | 2008-10-02 | Hitachi Ltd | テレビ放送受信装置 |
US7638869B2 (en) | 2007-03-28 | 2009-12-29 | Qimonda Ag | Semiconductor device |
US8723332B2 (en) | 2007-06-11 | 2014-05-13 | Invensas Corporation | Electrically interconnected stacked die assemblies |
KR100914977B1 (ko) | 2007-06-18 | 2009-09-02 | 주식회사 하이닉스반도체 | 스택 패키지의 제조 방법 |
JP5049684B2 (ja) | 2007-07-20 | 2012-10-17 | 新光電気工業株式会社 | 積層型半導体装置及びその製造方法 |
JP5110995B2 (ja) | 2007-07-20 | 2012-12-26 | 新光電気工業株式会社 | 積層型半導体装置及びその製造方法 |
US8461672B2 (en) | 2007-07-27 | 2013-06-11 | Tessera, Inc. | Reconstituted wafer stack packaging with after-applied pad extensions |
WO2009020572A2 (en) | 2007-08-03 | 2009-02-12 | Tessera Technologies Hungary Kft. | Stack packages using reconstituted wafers |
US7906853B2 (en) | 2007-09-06 | 2011-03-15 | Micron Technology, Inc. | Package structure for multiple die stack |
KR101614960B1 (ko) | 2007-10-18 | 2016-04-22 | 인벤사스 코포레이션 | 반도체 다이 어셈블리 및 반도체 다이 준비 방법 |
KR20090059754A (ko) | 2007-12-07 | 2009-06-11 | 삼성전자주식회사 | 표시 기판 및 표시 기판의 제조 방법 |
WO2009114670A2 (en) | 2008-03-12 | 2009-09-17 | Vertical Circuits, Inc. | Support mounted electrically interconnected die assembly |
US8680662B2 (en) | 2008-06-16 | 2014-03-25 | Tessera, Inc. | Wafer level edge stacking |
WO2010141311A1 (en) | 2009-06-02 | 2010-12-09 | Hsio Technologies, Llc | Compliant printed circuit area array semiconductor device package |
-
2010
- 2010-11-02 TW TW099137634A patent/TWI544604B/zh not_active IP Right Cessation
- 2010-11-04 WO PCT/US2010/055472 patent/WO2011056987A2/en active Application Filing
- 2010-11-04 US US12/939,524 patent/US8912661B2/en active Active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI467711B (zh) * | 2013-09-10 | 2015-01-01 | Chipbond Technology Corp | 半導體結構 |
Also Published As
Publication number | Publication date |
---|---|
US20110272825A1 (en) | 2011-11-10 |
TWI544604B (zh) | 2016-08-01 |
WO2011056987A2 (en) | 2011-05-12 |
WO2011056987A3 (en) | 2011-11-24 |
US8912661B2 (en) | 2014-12-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI544604B (zh) | 具有降低應力電互連的堆疊晶粒總成 | |
KR102135704B1 (ko) | 다중칩 통합 팬아웃 패키지 | |
US8053275B2 (en) | Semiconductor device having double side electrode structure and method of producing the same | |
TWI417995B (zh) | 具有晶粒埋入式以及雙面覆蓋重增層之基板結構及其方法 | |
US11456226B2 (en) | Semiconductor package and method of fabricating the same | |
US8178964B2 (en) | Semiconductor device package with die receiving through-hole and dual build-up layers over both side-surfaces for WLP and method of the same | |
EP2537182B1 (en) | Microelectronic package with terminals on dielectric mass | |
US7061125B2 (en) | Semiconductor package with pattern leads and method for manufacturing the same | |
TWI515863B (zh) | 載體安裝式電氣互連晶粒組成件 | |
TWI668825B (zh) | 半導體封裝及其製造方法 | |
CN106129041B (zh) | 具有面阵单元连接体的可堆叠模塑微电子封装 | |
US20080284017A1 (en) | Methods of fabricating circuit board and semiconductor package, and circuit board and semiconductor package fabricated using the methods | |
JP2019512168A (ja) | シリコン基板に埋め込まれたファンアウト型の3dパッケージ構造 | |
US9230901B2 (en) | Semiconductor device having chip embedded in heat spreader and electrically connected to interposer and method of manufacturing the same | |
US11139281B2 (en) | Molded underfilling for package on package devices | |
TW201119007A (en) | Electrical interconnect for die stacked in zig-zag configuration | |
US10504826B1 (en) | Device almost last embedded device structure and method of manufacturing thereof | |
TW201208004A (en) | Semiconductor device package structure and forming method of the same | |
US20090008777A1 (en) | Inter-connecting structure for semiconductor device package and method of the same | |
CN113363244A (zh) | 半导体结构及其形成方法 | |
TW202243151A (zh) | 封裝結構及其形成方法 | |
US20230369164A1 (en) | High efficiency heat dissipation using discrete thermal interface material films | |
US7763983B2 (en) | Stackable microelectronic device carriers, stacked device carriers and methods of making the same | |
US10692737B2 (en) | Multilayer interconnect structure with buried conductive via connections and method of manufacturing thereof | |
CN112309874A (zh) | 封装件及其形成方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |