KR900004031A - 바이폴러 트랜지스터 및 그 제조방법 - Google Patents
바이폴러 트랜지스터 및 그 제조방법 Download PDFInfo
- Publication number
- KR900004031A KR900004031A KR1019890011433A KR890011433A KR900004031A KR 900004031 A KR900004031 A KR 900004031A KR 1019890011433 A KR1019890011433 A KR 1019890011433A KR 890011433 A KR890011433 A KR 890011433A KR 900004031 A KR900004031 A KR 900004031A
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- South Korea
- Prior art keywords
- region
- base
- intrinsic
- diffusion
- forming
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- 238000004519 manufacturing process Methods 0.000 title claims 2
- 238000009792 diffusion process Methods 0.000 claims 6
- 238000000605 extraction Methods 0.000 claims 4
- 239000004065 semiconductor Substances 0.000 claims 2
- 239000000758 substrate Substances 0.000 claims 2
- 239000012535 impurity Substances 0.000 claims 1
- 238000000034 method Methods 0.000 claims 1
- 230000001629 suppression Effects 0.000 claims 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66272—Silicon vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0804—Emitter regions of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0821—Collector regions of bipolar transistors
- H01L29/0826—Pedestal collectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1004—Base region of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/157—Special diffusion and profiles
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 바이폴러 트랜지스터의 한예의 단면도.
제2도는 그 요부 단면도.
제3도는 본 발명의 바이폴러 트랜지스터의 다른 한예의 단면도.
Claims (2)
- 제1전도형의 콜렉터 영역내에 형성된 제2전도형의 베이스 영역과, 그 베이스 영역내에 형성된 제1전도형의 에미터 영역으로 형성되는 바이폴러 트랜지스터에 있어서, 상기 베이스 영역은 베이스 취출 영역, 진성 베이스 영역 및 상기 베이스 취출 영역과 진성 베이스 영역간을 접속하고 그 진성 베이스 영역보다도 확산깊이가 얕은 베이스 접속 영역으로 형성되며, 상기 관성 베이스 영역내에 상기 에미터 영역이 형성되고, 적어도 그 진성 베이스 영역하에는 제1전도형의 확산 억제 영역이 형성되는 것을 특징으로하는 바이폴러 트랜지스터.
- 바이폴러 트랜지스터 제조방법에 있어서, 제1전도형의 반도체 기체상에 선택적으로 형성된 베이스 취출 전극과 셀파라인에서 불순물을 도입하여 소요의 확산 깊이로 되도록 제2전도형의 베이스 접속 영역을 형성하고, 그 베이스 접속 영역의 하부에 확산억제 영역을 형성하는 공정과, 상기 베이스 취출 전극에서의 확산에서 상기 베이스 접속 영역과 접속하는 베이스 취출 영역을 형성하는 공정과, 제1전도형의 반도체 기체의 표면에서 상기 베이스 접속 영역과 접하여, 진성 베이스 영역을 그 베이스 접속 영역의 확산 깊이 보다도 깊은 확산 깊이로서 형성하는 공정과, 상기 진성 베이스 영역내에 에미터 영역을 형성하는 공정을 가지는 것을 특징으로하는 바이폴러 트랜지스터 제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP201360 | 1988-08-12 | ||
JP63201360A JP2748420B2 (ja) | 1988-08-12 | 1988-08-12 | バイポーラトランジスタ及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR900004031A true KR900004031A (ko) | 1990-03-27 |
KR0156544B1 KR0156544B1 (ko) | 1998-10-15 |
Family
ID=16439760
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019890011433A KR0156544B1 (ko) | 1988-08-12 | 1989-08-11 | 바이폴러 트랜지스터 및 그 제조방법 |
Country Status (5)
Country | Link |
---|---|
US (1) | US5010026A (ko) |
EP (1) | EP0354765B1 (ko) |
JP (1) | JP2748420B2 (ko) |
KR (1) | KR0156544B1 (ko) |
DE (1) | DE68928482T2 (ko) |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5183768A (en) * | 1989-04-04 | 1993-02-02 | Matsushita Electric Industrial Co., Ltd. | Method of fabricating semiconductor device by forming doped regions that limit width of the base |
JPH03206621A (ja) * | 1990-01-09 | 1991-09-10 | Oki Electric Ind Co Ltd | 半導体集積回路装置の製造方法 |
JP3127455B2 (ja) * | 1990-08-31 | 2001-01-22 | ソニー株式会社 | 半導体装置の製法 |
GB2248142A (en) * | 1990-09-19 | 1992-03-25 | Koninkl Philips Electronics Nv | A method of manufacturing a semiconductor device |
US5238872A (en) * | 1990-12-11 | 1993-08-24 | Samsung Semiconductor, Inc. | Barrier metal contact architecture |
JP2672199B2 (ja) * | 1991-05-21 | 1997-11-05 | シャープ株式会社 | 半導体装置の製造方法 |
JP3061891B2 (ja) * | 1991-06-21 | 2000-07-10 | キヤノン株式会社 | 半導体装置の製造方法 |
US5091321A (en) * | 1991-07-22 | 1992-02-25 | Allegro Microsystems, Inc. | Method for making an NPN transistor with controlled base width compatible with making a Bi-MOS integrated circuit |
JPH0529329A (ja) * | 1991-07-24 | 1993-02-05 | Canon Inc | 半導体装置の製造方法 |
US5194926A (en) * | 1991-10-03 | 1993-03-16 | Motorola Inc. | Semiconductor device having an inverse-T bipolar transistor |
JP2855919B2 (ja) * | 1991-10-24 | 1999-02-10 | 日本電気株式会社 | 半導体装置およびその製造方法 |
CA2124843A1 (en) * | 1992-02-25 | 1993-09-02 | James A. Matthews | Bipolar junction transistor exhibiting suppressed kirk effect |
US5302534A (en) * | 1992-03-02 | 1994-04-12 | Motorola, Inc. | Forming a vertical PNP transistor |
DE69402221T2 (de) * | 1993-01-29 | 1997-08-14 | Nat Semiconductor Corp | Bipolartransistoren und deren Herstellungsverfahren |
US5380677A (en) * | 1993-06-23 | 1995-01-10 | Vlsi Technology, Inc. | Method for reducing resistance at interface of single crystal silicon and deposited silicon |
JPH07169771A (ja) * | 1993-12-15 | 1995-07-04 | Nec Corp | 半導体装置及びその製造方法 |
US5620907A (en) * | 1995-04-10 | 1997-04-15 | Lucent Technologies Inc. | Method for making a heterojunction bipolar transistor |
JP2907323B2 (ja) * | 1995-12-06 | 1999-06-21 | 日本電気株式会社 | 半導体装置およびその製造方法 |
FR2776828B1 (fr) * | 1998-03-31 | 2003-01-03 | Sgs Thomson Microelectronics | Region de base-emetteur d'un transistor bipolaire submicronique |
JP2000012553A (ja) * | 1998-06-26 | 2000-01-14 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
US6072223A (en) * | 1998-09-02 | 2000-06-06 | Micron Technology, Inc. | Circuit and method for a memory cell using reverse base current effect |
JP2001274257A (ja) * | 2000-03-27 | 2001-10-05 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
IT1316871B1 (it) * | 2000-03-31 | 2003-05-12 | St Microelectronics Srl | Dispositivo elettronico integrato monoliticamente e relativo processodi fabbricazione |
US6995068B1 (en) * | 2000-06-09 | 2006-02-07 | Newport Fab, Llc | Double-implant high performance varactor and method for manufacturing same |
DE10205712A1 (de) * | 2002-02-12 | 2003-08-28 | Infineon Technologies Ag | Polysilizium-Bipolartransistor und Verfahren zur Herstellung desselben |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4066473A (en) * | 1976-07-15 | 1978-01-03 | Fairchild Camera And Instrument Corporation | Method of fabricating high-gain transistors |
DE2728845A1 (de) * | 1977-06-27 | 1979-01-18 | Siemens Ag | Verfahren zum herstellen eines hochfrequenztransistors |
DE2946963A1 (de) * | 1979-11-21 | 1981-06-04 | Siemens AG, 1000 Berlin und 8000 München | Schnelle bipolare transistoren |
US4319932A (en) * | 1980-03-24 | 1982-03-16 | International Business Machines Corporation | Method of making high performance bipolar transistor with polysilicon base contacts |
US4495512A (en) * | 1982-06-07 | 1985-01-22 | International Business Machines Corporation | Self-aligned bipolar transistor with inverted polycide base contact |
US4693782A (en) * | 1985-09-06 | 1987-09-15 | Matsushita Electric Industrial Co., Ltd. | Fabrication method of semiconductor device |
US4887145A (en) * | 1985-12-04 | 1989-12-12 | Hitachi, Ltd. | Semiconductor device in which electrodes are formed in a self-aligned manner |
EP0255882A3 (de) * | 1986-08-07 | 1990-05-30 | Siemens Aktiengesellschaft | npn-Bipolartransistor mit extrem flachen Emitter/Basis-Strukturen und Verfahren zu seiner Herstellung |
JPS63261746A (ja) * | 1987-04-20 | 1988-10-28 | Oki Electric Ind Co Ltd | バイポ−ラ型半導体集積回路装置の製造方法 |
JP2661050B2 (ja) * | 1987-07-24 | 1997-10-08 | ソニー株式会社 | バイポーラトランジスタの製造方法 |
JP2625741B2 (ja) * | 1987-07-28 | 1997-07-02 | ソニー株式会社 | バイポーラトランジスタの製造方法 |
JPS6431461A (en) * | 1987-07-28 | 1989-02-01 | Sony Corp | Manufacture of bipolar transistor |
US4851362A (en) * | 1987-08-25 | 1989-07-25 | Oki Electric Industry Co., Ltd. | Method for manufacturing a semiconductor device |
JP2623635B2 (ja) * | 1988-02-16 | 1997-06-25 | ソニー株式会社 | バイポーラトランジスタ及びその製造方法 |
-
1988
- 1988-08-12 JP JP63201360A patent/JP2748420B2/ja not_active Expired - Lifetime
-
1989
- 1989-08-08 DE DE68928482T patent/DE68928482T2/de not_active Expired - Lifetime
- 1989-08-08 EP EP89308057A patent/EP0354765B1/en not_active Expired - Lifetime
- 1989-08-10 US US07/391,880 patent/US5010026A/en not_active Expired - Lifetime
- 1989-08-11 KR KR1019890011433A patent/KR0156544B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP0354765B1 (en) | 1997-12-10 |
KR0156544B1 (ko) | 1998-10-15 |
DE68928482D1 (de) | 1998-01-22 |
JPH0250435A (ja) | 1990-02-20 |
EP0354765A3 (en) | 1990-06-20 |
EP0354765A2 (en) | 1990-02-14 |
DE68928482T2 (de) | 1998-04-09 |
US5010026A (en) | 1991-04-23 |
JP2748420B2 (ja) | 1998-05-06 |
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