KR20010081954A - 반도체 장치 및 그 제조방법 - Google Patents
반도체 장치 및 그 제조방법 Download PDFInfo
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- KR20010081954A KR20010081954A KR1020000066669A KR20000066669A KR20010081954A KR 20010081954 A KR20010081954 A KR 20010081954A KR 1020000066669 A KR1020000066669 A KR 1020000066669A KR 20000066669 A KR20000066669 A KR 20000066669A KR 20010081954 A KR20010081954 A KR 20010081954A
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- 229910052721 tungsten Inorganic materials 0.000 description 5
- 239000010937 tungsten Substances 0.000 description 5
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 5
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- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
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- 229910052719 titanium Inorganic materials 0.000 description 1
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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- G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
- G03F9/7073—Alignment marks and their environment
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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- H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract
Description
Claims (28)
- 그 주면에 반도체 소자가 형성된 반도체 기판과, 상기 주면 또는 상기 주면상의 어느 한층에 형성된 제1 패턴과, 상기 제1 패턴의 상층에 형성된 제2 패턴을 가지는 반도체 장치로서,상기 제1 패턴에는 더미패턴이 포함되고, 상기 제2 패턴에는 광학적 패턴인식의 대상으로 되는 패턴이 포함되며,상기 광학적 패턴인식의 대상으로 되는 패턴은, 상기 더미패턴의 평면형상 내에 내포되도록 형성되어 있는 것을 특징으로 하는 반도체 장치.
- 제1항에 있어서,상기 제1 패턴에는 상기 더미패턴보다도 작은 면적을 가지는 다른 더미패턴이 포함되어 있는 것을 특징으로 하는 반도체 장치.
- 제2항에 있어서,상기 더미패턴 및 다른 더미패턴은 스크라이브영역에 형성되어 있는 것을 특징으로 하는 반도체 장치.
- 제2항에 있어서,상기 다른 더미패턴은 제품영역 및 스크라이브영역에 형성되어 있는 것을 특징으로 하는 반도체 장치.
- 제1항에 있어서,상기 더미패턴은 상기 광학적 패턴인식의 대상으로 되는 패턴주변의 패턴배치 금지영역 이상의 면적으로 형성되어 있는 것을 특징으로 하는 반도체 장치.
- 제5항에 있어서,상기 제1 패턴에는 상기 반도체 소자의 설계룰(design rule)과 동일 오더(order)의 가공치수를 가지고, 또한 상기 더미패턴보다도 작은 면적을 가지는 다른 더미패턴이 포함되며, 상기 패턴배치 금지영역에는 상기 다른 더미패턴이 배치되어 있지 않은 것을 특징으로 하는 반도체 장치.
- 제6항에 있어서,상기 더미패턴은 반도체 웨이퍼의 스크라이브 영역에 형성되고, 상기 다른 더미패턴은 상기 반도체 웨이퍼의 제품영역 및 스크라이브영역에 형성되어 있는 것을 특징으로 하는 반도체 장치.
- 그 주면에 반도체 소자가 형성된 반도체 기판과, 상기 주면 또는 상기 주면 상의 어느 한층에 형성된 제1 패턴과, 상기 제1 패턴의 상층에 형성된 제2패턴을 가지는 반도체 장치로서,상기 제1 패턴에는 제1 더미패턴이 포함되고, 상기 제2 패턴에는 상기 제1 더미패턴과 동일 설계치수의 패턴피치 및 패턴폭을 가지는 제2 더미패턴이 포함되며,상기 제2 더미패턴은, 그 평면위치에 있어서 상기 제1 더미패턴의 스페이스 상에 형성되어 있는 것을 특징으로 하는 반도체 장치.
- 제8항에 있어서,상기 제2 더미패턴의 어느 한 단변(端邊)은, 그 평면위치에 있어서 상기 제1 더미패턴에 겹쳐 형성되어 있는 것을 특징으로 하는 반도체 장치.
- 제8항에 있어서,상기 제1 더미패턴과 상기 제2 더미패턴과는, 그 평면위치에 있어서 피치의 반분의 거리만큼 어긋나 있는 것을 특징으로 하는 반도체 장치.
- 제8항에 있어서,상기 제1 패턴에는 상기 제1 더미패턴보다도 큰 면적을 가지는 다른 더미패턴이 더 포함되고, 상기 제2 패턴에는 광학적 패턴인식의 대상으로 되는 패턴이 더 포함되며,상기 광학적 패턴인식의 대상으로 되는 패턴은, 상기 다른 더미패턴의 평면형상 내에 내포되도록 형성되어 있는 것을 특징으로 하는 반도체 장치.
- 제11항에 있어서,상기 다른 더미패턴은 상기 광학적 패턴인식의 대상으로 되는 패턴주변의 패턴배치 금지영역 이상의 면적으로 형성되고,상기 패턴배치 금지영역에는 상기 제1 더미패턴이 배치되어 있지 않은 것을 특징으로 하는 반도체 장치.
- 제11항에 있어서,상기 다른 더미패턴은 반도체 웨이퍼의 스크라이브영역에 형성되고, 상기 제1 및 제2 더미패턴은 상기 반도체 웨이퍼의 제품영역 및 스크라이브영역에 형성되어 있는 것을 특징으로 하는 반도체 장치.
- 제1항에 있어서,상기 제1 패턴은 상기 주면에 형성된 활성영역패턴이고, 상기 제2 패턴은 상기 반도체 소자를 구성하는 게이트전극과 동층에 형성된 패턴인 것을 특징으로 하는 반도체 장치.
- (a)반도체 기판의 주면 상 또는 상기 주면 상의 어느 한 부재층 상에 더미패턴이 포함된 제1 패턴을 형성하는 공정과,(b)상기 제1 패턴이 형성된 상기 주면 상 또는 상기 제1 패턴으로 패터닝된부재상에 절연막을 퇴적하고, 상기 절연막에 연마를 행하여 표면을 평탄화하는 공정과,(c)상기 평탄화된 표면의 상층에 광학적 패턴인식의 대상으로 되는 패턴이 포함된 제2 패턴을 형성하는 공정과,를 가지고, 상기 광학적 패턴인식의 대상으로 되는 패턴은 상기 더미패턴의 평면형상 내에 내포되도록 형성하는 것을 특징으로 하는 반도체 장치의 제조방법.
- 제15항에 있어서,상기 광학적 패턴인식의 대상으로 되는 패턴을 광학적으로 검출하고, 상기 반도체 기체(基體)의 위치맞춤을 행하는 공정을 더 가지는 것을 특징으로 하는 반도체 장치의 제조방법.
- (a)반도체 기체(基體)의 주면 상 또는 상기 주면 상의 어느 한 부재층 상에 더미패턴이 포함된 제1 패턴을 형성하는 공정과,(b)상기 제1 패턴의 상층에 광학적 패턴인식의 대상으로 되는 패턴이 포함된 제2 패턴을 형성하는 공정과,(c)상기 광학적 패턴인식의 대상으로 되는 패턴을 광학적으로 검출하고, 상기 반도체 기체의 위치맞춤을 행하는 공정과,를 가지고, 상기 광학적 패턴인식의 대상으로 되는 패턴은, 상기 더미패턴의 평면형상 내에 내포되도록 형성하는 것을 특징으로 하는 반도체 장치의 제조방법.
- 제15항에 있어서,상기 더미패턴은, 상기 광학적 패턴인식의 대상으로 되는 패턴주변의 패턴배치 금지영역 이상의 면적으로 형성하는 것을 특징으로 하는 반도체 장치의 제조방법.
- 제15항에 있어서,상기 제1 패턴에는 제1 더미패턴이 더 포함되고, 상기 제2 패턴에는 상기 제1 더미패턴과 동일 설계치수의 패턴피치 및 패턴폭을 가지는 제2 더미패턴이 더포함되며,상기 제2 더미패턴은, 그 평면위치에 있어서 상기 제1 더미패턴의 스페이스 상에 형성하는 것을 특징으로 하는 반도체 장치의 제조방법.
- 제19항에 있어서,상기 제2 더미패턴의 어느 한 단변은, 그 평면위치에 있어서 상기 제1 더미패턴에 겹치도록 형성하는 제1의 구성,상기 제1 더미패턴과 상기 제2 더미패턴과는, 그 평면위치에 있어서 피치의 반분의 거리만큼 어긋나게 형성하는 제2의 구성,의 어느 한 구성을 가지는 것을 특징으로 하는 반도체 장치의 제조방법.
- 제15항에 있어서,상기 더미패턴을 반도체 웨이퍼의 스크라이브영역에 형성하고, 상기 제1 및 제2 더미패턴을 상기 반도체 웨이퍼의 제품영역 및 스크라이브영역에 형성하는 것을 특징으로 하는 반도체 장치의 제조방법.
- 제15항에 있어서,상기 제1 패턴이 전사되는 부재는 반도체 기판이고, 상기 제2 패턴이 전사되어 형성되는 부재는 게이트전극인 것을 특징으로 하는 반도체 장치의 제조방법.
- 제8항에 있어서,상기 제1 패턴은, 상기 주면에 형성된 활성영역패턴이고, 상기 제2 패턴은 상기 반도체 소자를 구성하는 게이트전극과 동층에 형성된 패턴인 것을 특징으로 하는 반도체 장치.
- 제17항에 있어서,상기 더미패턴은 상기 광학적 패턴인식의 대상으로 되는 패턴주변의 패턴배치 금지영역 이상의 면적으로 형성하는 것을 특징으로 하는 반도체 장치의 제조방법.
- 제17항에 있어서,상기 제1 패턴에는 제1 더미패턴이 더 포함되고, 상기 제2 패턴에는 상기 제1 더미패턴과 동일 설계치수의 패턴피치 및 패턴폭을 가지는 제2 더미패턴이 더 포함되며,상기 제2 더미패턴은, 그 평면위치에 있어서 상기 제1 더미패턴의 스페이스 상에 형성하는 것을 특징으로 하는 반도체 장치의 제조방법.
- 제17항에 있어서,상기 더미패턴을 반도체 웨이퍼의 스크라이브 영역에 형성하고, 상기 제1 및 제2 더미패턴을 상기 반도체 웨이퍼의 제품영역 및 스크라이브영역에 형성하는 것을 특징으로 하는 반도체 장치의 제조방법.
- 제17항에 있어서,상기 제1 패턴이 전사되는 부재는 반도체 기판이고, 상기 제2 패턴이 전사되어 형성되는 부재는 게이트전극인 것을 특징으로 하는 반도체 장치의 제조방법.
- 제25항에 있어서,상기 제2 더미패턴의 어느 한 단변은, 그 평면위치에 있어서 상기 제1 더미패턴에 겹치도록 형성하는 제1의 구성,상기 제1 더미패턴과 상기 제2 더미패턴과는, 그 평면위치에 있어서 피치의 반분의 거리만큼 어긋나게 형성하는 제2의 구성,의 어느 한 구성을 가지는 것을 특징으로 하는 반도체 장치의 제조방법.
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US7696608B2 (en) | 2010-04-13 |
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US20050110065A1 (en) | 2005-05-26 |
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US7154164B2 (en) | 2006-12-26 |
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US7112870B2 (en) | 2006-09-26 |
US20120220104A1 (en) | 2012-08-30 |
US8569107B2 (en) | 2013-10-29 |
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