KR100276546B1 - 반도체장치및그제조방법 - Google Patents

반도체장치및그제조방법 Download PDF

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Publication number
KR100276546B1
KR100276546B1 KR1019980012551A KR19980012551A KR100276546B1 KR 100276546 B1 KR100276546 B1 KR 100276546B1 KR 1019980012551 A KR1019980012551 A KR 1019980012551A KR 19980012551 A KR19980012551 A KR 19980012551A KR 100276546 B1 KR100276546 B1 KR 100276546B1
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KR
South Korea
Prior art keywords
region
trench
alignment mark
gate electrode
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019980012551A
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English (en)
Korean (ko)
Other versions
KR19990029155A (ko
Inventor
다까시 구로이
마이꼬 사까이
가쯔유끼 호리따
히로까즈 사야마
Original Assignee
다니구찌 이찌로오
미쓰비시덴키 가부시키가이샤
기타오카 다카시
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 다니구찌 이찌로오, 미쓰비시덴키 가부시키가이샤, 기타오카 다카시 filed Critical 다니구찌 이찌로오
Publication of KR19990029155A publication Critical patent/KR19990029155A/ko
Application granted granted Critical
Publication of KR100276546B1 publication Critical patent/KR100276546B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2041—Photolithographic processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0143—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations comprising concurrently refilling multiple trenches having different shapes or dimensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/501—Marks applied to devices, e.g. for alignment or identification for use before dicing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/975—Substrate or mask aligning feature

Landscapes

  • Semiconductor Memories (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Element Separation (AREA)
KR1019980012551A 1997-09-09 1998-04-09 반도체장치및그제조방법 Expired - Fee Related KR100276546B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP97-243993 1997-09-09
JP24399397A JP3519579B2 (ja) 1997-09-09 1997-09-09 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
KR19990029155A KR19990029155A (ko) 1999-04-26
KR100276546B1 true KR100276546B1 (ko) 2000-12-15

Family

ID=17112127

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019980012551A Expired - Fee Related KR100276546B1 (ko) 1997-09-09 1998-04-09 반도체장치및그제조방법

Country Status (4)

Country Link
US (2) US5889335A (https=)
JP (1) JP3519579B2 (https=)
KR (1) KR100276546B1 (https=)
TW (1) TW425661B (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030069776A (ko) * 2002-02-19 2003-08-27 미쓰비시덴키 가부시키가이샤 반도체장치의 제조방법

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US6395619B2 (en) * 1997-12-05 2002-05-28 Sharp Kabushiki Kaisha Process for fabricating a semiconductor device
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US6043133A (en) * 1998-07-24 2000-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of photo alignment for shallow trench isolation chemical-mechanical polishing
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JP2001203263A (ja) * 2000-01-20 2001-07-27 Hitachi Ltd 半導体集積回路装置の製造方法および半導体集積回路装置
US6603211B2 (en) * 2000-02-16 2003-08-05 Advanced Micro Devices, Inc. Method and system for providing a robust alignment mark at thin oxide layers
JP3415551B2 (ja) * 2000-03-27 2003-06-09 日本電気株式会社 半導体装置の製造方法
JP2001351837A (ja) * 2000-06-02 2001-12-21 Nec Corp 半導体装置の製造方法
JP2002043412A (ja) * 2000-07-24 2002-02-08 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP4832629B2 (ja) 2000-10-04 2011-12-07 ルネサスエレクトロニクス株式会社 半導体装置
KR20020056347A (ko) * 2000-12-29 2002-07-10 박종섭 반도체 소자의 제조 방법
JP3665275B2 (ja) * 2001-05-28 2005-06-29 沖電気工業株式会社 位置合わせマークの形成方法
JP2002368080A (ja) * 2001-06-05 2002-12-20 Hitachi Ltd 半導体集積回路装置およびその製造方法
JP4907014B2 (ja) * 2001-06-22 2012-03-28 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
JP3875047B2 (ja) * 2001-06-22 2007-01-31 シャープ株式会社 半導体基板の面方位依存性評価方法及びそれを用いた半導体装置
JP4761662B2 (ja) * 2001-07-17 2011-08-31 三洋電機株式会社 回路装置の製造方法
KR100398576B1 (ko) * 2001-08-07 2003-09-19 주식회사 하이닉스반도체 정렬 정확도 향상방법
US6638866B1 (en) * 2001-10-18 2003-10-28 Taiwan Semiconductor Manufacturing Company Chemical-mechanical polishing (CMP) process for shallow trench isolation
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DE10258420B4 (de) * 2002-12-13 2007-03-01 Infineon Technologies Ag Verfahren zur Herstellung einer Halbleiterspeichereinrichtung mit Charge-trapping-Speicherzellen und vergrabenen Bitleitungen
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KR101998666B1 (ko) 2013-06-25 2019-10-02 삼성전자주식회사 반도체 장치 및 그 제조 방법
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KR102066000B1 (ko) 2013-12-11 2020-01-14 삼성전자주식회사 반도체 소자의 제조하는 방법
KR20160015094A (ko) * 2014-07-30 2016-02-12 삼성전자주식회사 오버레이 마크, 오버레이 마크를 형성하는 방법 및 오버레이 마크를 이용하여 반도체 소자를 제조하는 방법
CN105914141B (zh) * 2016-06-24 2019-04-30 武汉新芯集成电路制造有限公司 一种形成栅极沟道的方法及对应的半导体结构
JP7163577B2 (ja) * 2017-12-28 2022-11-01 富士電機株式会社 半導体装置の製造方法
US10636744B2 (en) * 2018-08-09 2020-04-28 United Microelectronics Corp. Memory device including alignment mark trench
CN111916425B (zh) * 2019-05-10 2022-12-16 中芯国际集成电路制造(上海)有限公司 半导体形成方法及其结构
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CN113467188B (zh) * 2020-03-30 2022-05-13 长鑫存储技术有限公司 半导体结构及其制备方法
CN113013076B (zh) * 2021-02-25 2022-06-10 长鑫存储技术有限公司 套刻标记的形成方法及半导体结构
US12191258B2 (en) * 2021-12-03 2025-01-07 Nanya Technology Corporation Semiconductor device having integral alignment marks with decoupling features and method for fabricating the same
TWI903688B (zh) * 2024-08-13 2025-11-01 聯華電子股份有限公司 包含有對準標記的半導體結構以及其測量方法

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Also Published As

Publication number Publication date
JPH1187488A (ja) 1999-03-30
TW425661B (en) 2001-03-11
KR19990029155A (ko) 1999-04-26
US6218262B1 (en) 2001-04-17
US5889335A (en) 1999-03-30
JP3519579B2 (ja) 2004-04-19

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