JPWO2008001915A1 - 配線基板、配線基板を用いた半導体装置、及びそれらの製造方法 - Google Patents
配線基板、配線基板を用いた半導体装置、及びそれらの製造方法 Download PDFInfo
- Publication number
- JPWO2008001915A1 JPWO2008001915A1 JP2008522666A JP2008522666A JPWO2008001915A1 JP WO2008001915 A1 JPWO2008001915 A1 JP WO2008001915A1 JP 2008522666 A JP2008522666 A JP 2008522666A JP 2008522666 A JP2008522666 A JP 2008522666A JP WO2008001915 A1 JPWO2008001915 A1 JP WO2008001915A1
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- Prior art keywords
- metal film
- wiring
- wiring board
- layer
- insulating layer
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Abstract
Description
111、112、113、114;半導体装置
11;絶縁層
12;第1金属膜
13;第2金属膜
14;第1配線層
15;窪み
16;ビア
17;配線層
18;電極
19、20;ソルダーレジスト
21;支持基板
22;エッチングバリア層
23、27;半導体素子
24、28;接続電極
25;半田ボール
26;アンダーフィル
29;ワイヤー
30;モールド樹脂
31;接着剤
32、33;めっきレジスト
34;ビアホール
35;金属枠
36;彫り込み
Claims (36)
- 絶縁層と、この絶縁層に相互に絶縁されて形成された複数個の配線層と、前記絶縁層内に形成され前記配線層間を接続する複数個のビアとを有し、前記配線層のうち、前記絶縁層の一面に形成された表面配線層は、前記一面に露出している第1金属膜と、前記絶縁層内に埋め込まれ前記第1金属膜に積層された第2金属膜とを有し、前記第1金属膜の端部は前記第2金属膜の端部よりも前記第2金属膜の表面方向外側まで延出していることを特徴とする配線基板。
- 前記第1金属膜の表面は、前記絶縁層の前記一面よりも凹んだ位置にあることを特徴とする請求項1に記載の配線基板。
- 前記第1金属膜が形成された位置の前記絶縁膜の凹みの側面は、前記第1金属膜の端部の位置と一致していることを特徴とする請求項2に記載の配線基板。
- 前記第1金属膜が形成された位置の前記絶縁膜の凹みの側面は、前記第1金属膜の端部の位置よりも外側に位置することを特徴とする請求項2に記載の配線基板。
- 絶縁層と、この絶縁層に相互に絶縁されて形成された複数個の配線層と、前記絶縁層内に形成され前記配線層間を接続する複数個のビアとを有し、前記配線層のうち、前記絶縁層の一面に形成された表面配線層は、前記一面に露出している第1金属膜と、前記絶縁層内に埋め込まれ前記第1金属膜に積層された第2金属膜とを有し、前記第1金属膜の端部の位置は前記第2金属膜の端部の位置と一致しており、前記第1金属膜の表面は、前記絶縁層の前記一面よりも凹んだ位置にあり、前記第1金属膜が形成された位置の前記絶縁膜の凹みの側面は、前記第1金属膜の端部の位置よりも外側に位置することを特徴とする配線基板。
- 前記第1金属膜と前記第2金属膜とが同じ材料からなることを特徴とする請求項1乃至5のいずれか1項に記載の配線基板。
- 前記第1金属膜は、金、銀、ニッケル、銅、アルミニウム、パラジウム、白金、ロジウム、錫及び半田材料からなる群から選択された1種類の金属又は複数種類の金属の積層体からなることを特徴とする請求項1乃至5のいずれか1項に記載の配線基板。
- 前記第2金属膜は、金、銀、ニッケル、銅、アルミニウム、パラジウム、白金、ロジウム、錫及び半田材料からなる群から選択された1種類の金属又は複数種類の金属の積層体からなることを特徴とする請求項1乃至5のいずれか1項に記載の配線基板。
- 前記表面配線層のうち一部は、前記ビアが接続されていないことを特徴とする請求項1乃至5のいずれか1項に記載の配線基板。
- 前記絶縁層の片面又は両面に金属枠が設けられていることを特徴とする請求項1乃至5のいずれか1項に記載の配線基板。
- 前記絶縁層の前記一面と反対側の面の上に第2の電極が設けられ、前記表面配線層の一部を第1の電極とし、前記絶縁層の片面又は両面に前記第1の電極及び前記第2の電極の一部又は全体が露出するように開口部を設けたソルダーレジストが設けられていることを特徴とする請求項1乃至5のいずれか1項に記載の配線基板。
- 請求項1乃至5のいずれか1項に記載の配線基板の前記一面に、前記一面側から順にエッチングバリア層と支持基板とが設けられていることを特徴とする配線基板。
- 前記エッチングバリア層は、前記一面の全面に設けられていることを特徴とする請求項12に記載の配線基板。
- 前記エッチングバリア層の端部の位置は、前記第1金属膜の端部の位置よりも前記第1金属膜の表面方向外側まで延出しているか又は前記第1金属膜の端部の位置と一致していることを特徴とする請求項12に記載の配線基板。
- 前記支持基板は、導電性を有する材料か又は導電性を有する材料が絶縁材料の表面に積層された複合材料からなることを特徴とする請求項12に記載の配線基板。
- 前記エッチングバリア層は、前記支持基板の導電性を有する材料及び前記第1金属膜の材料と異なる材料からなることを特徴とする請求項12に記載の配線基板。
- 前記絶縁層の前記一面と反対側の面の上に第2の電極が設けられ、前記第2の電極の一部又は全体が露出するように開口部を設けたソルダーレジストが設けられていることを特徴とする請求項12に記載の配線基板。
- 請求項1乃至5のいずれか1項に記載の配線基板に、1又は複数個の半導体素子が接続されていることを特徴とする半導体装置。
- 前記半導体素子と前記配線基板とがフリップチップ接続及びワイヤーボンディング接続の少なくとも1つの接続方法によって接続されていることを特徴とする請求項18に記載の半導体装置。
- 支持基板上にエッチングバリア層を形成する工程と、前記エッチングバリア層上に第1金属膜を形成し、この第1金属膜上の内側に第2金属膜を積層して表面配線層を形成する工程と、前記支持基板、前記エッチングバリア層及び前記表面配線層を覆う様に絶縁層を形成する工程と、前記絶縁層にビアを形成する工程と、前記絶縁層の上に第2の配線層を形成する工程と、を有することを特徴とする配線基板の製造方法。
- 前記エッチングバリア層は、前記支持基板の全面に形成されることを特徴とする請求項20に記載の配線基板の製造方法。
- 前記絶縁層を形成する工程の前に、前記第2金属膜をエッチングする工程を有することを特徴とする請求項20又は21に記載の配線基板の製造方法。
- 支持基板上にエッチングバリア層を形成する工程と、前記エッチングバリア層上の内側に第1金属膜を形成し、この第1金属膜上に第2金属膜を積層して表面配線層を形成する工程と、前記支持基板、前記エッチングバリア層及び前記表面配線層を覆う様に絶縁層を形成する工程と、前記絶縁層にビアを形成する工程と、前記絶縁層の上に第2の配線層を形成する工程と、を有することを特徴とする配線基板の製造方法。
- 前記絶縁層の表面配線層が形成された面と反対側の面の上に第2電極を形成する工程と、前記第2電極の一部又は全体を露出するように開口部を設けてソルダーレジストを形成する工程と、を有することを特徴とする請求項20又は23に記載の配線基板の製造方法。
- 支持基板の両面に対し、請求項20又は23に記載の配線基板の製造方法によって配線基板を形成し、前記支持基板を分割して2個の配線基板を得ることを特徴とする配線基板の製造方法。
- 前記支持基板を除去する工程と、前記エッチングバリア層を除去する工程と、を有することを特徴とする請求項20又は23に記載の配線基板の製造方法。
- 前記支持基板を除去する工程において、前記支持基板を完全に除去することを特徴とする請求項26に記載の配線基板の製造方法。
- 前記支持基板を除去する工程において、前記支持基板の一部を残すことを特徴とする請求項26に記載の配線基板の製造方法。
- 前記エッチングバリア層を除去する工程の後に、前記表面配線層の一部を電極とし、この電極の一部又は全体を露出するように開口部を設けてソルダーレジストを形成する工程を有することを特徴とする請求項26に記載の配線基板の製造方法。
- 請求項20又は23に記載の配線基板の製造方法により形成される配線基板上に半導体素子を搭載する工程を有することを特徴とする半導体装置の製造方法。
- 前記半導体素子を搭載する工程の後に、前記支持基板を除去する工程と、前記エッチングバリア層を除去する工程と、を有することを特徴とする請求項30に記載の半導体装置の製造方法。
- 前記支持基板を除去する工程において、前記支持基板を完全に除去することを特徴とする請求項31に記載の半導体装置の製造方法。
- 前記支持基板を除去する工程において、前記支持基板の一部を残すことを特徴とする請求項31に記載の半導体装置の製造方法。
- 前記表面配線層の一部を電極とし、前記エッチングバリア層を除去する工程の後に、前記電極の一部又は全体を露出するように開口部を設けてソルダーレジストを形成する工程を有することを特徴とする請求項31に記載の半導体装置の製造方法。
- 請求項26に記載の配線基板の製造方法により形成される配線基板上に半導体素子を搭載する工程を有することを特徴とする半導体装置の製造方法。
- 前記半導体素子と前記配線基板とがフリップチップ接続及びワイヤーボンディング接続の少なくとも1つの接続方法によって接続することを特徴とする請求項30に記載の半導体装置の製造方法。
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US20090315190A1 (en) | 2009-12-24 |
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US7911038B2 (en) | 2011-03-22 |
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