JP6522521B2 - 半導体デバイスの電極及びその製造方法 - Google Patents
半導体デバイスの電極及びその製造方法 Download PDFInfo
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- JP6522521B2 JP6522521B2 JP2015558134A JP2015558134A JP6522521B2 JP 6522521 B2 JP6522521 B2 JP 6522521B2 JP 2015558134 A JP2015558134 A JP 2015558134A JP 2015558134 A JP2015558134 A JP 2015558134A JP 6522521 B2 JP6522521 B2 JP 6522521B2
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- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
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Description
本出願は、2013年2月15日に出願された米国仮出願番号第61/765,635号の優先権を主張する。基礎出願の開示内容は、本出願の開示内容の一部を構成し、引用によって本出願に援用される。
技術分野
本発明は、半導体電子デバイスに関し、詳しくは、フィールドプレートに接続される電極を有するデバイスに関する。
Claims (41)
- III−N材料構造と、
ソース及びドレインと、
前記III−N材料構造の表面上に形成され、厚さを有する一層の電極画定層であって、前記一層の電極画定層内に前記ドレインに近接する第1の側壁と、前記ソースに近接する第2の側壁とを有する凹部を有し、前記第1及び第2の側壁がそれぞれ複数の段を含み、前記III−N材料構造から遠い前記凹部の一部が第1の幅を有し、前記III−N材料構造に近い前記凹部の一部が第2の幅を有し、前記第1の幅が前記第2の幅より大きい一層の電極画定層と、
前記凹部内にあり、前記第1の側壁を少なくとも部分的に覆う拡張部分を含む電極とを備え、
前記第1の側壁は、前記III−N材料構造の表面に対して第1の有効角を形成し、前記第2の側壁は、前記III−N材料構造の表面に対して第2の有効角を形成し、前記第2の有効角は、前記第1の有効角より大きく、
前記電極は、前記トランジスタのゲート領域内にゲートを備え、
前記第1及び第2の側壁の複数の段は、それぞれ前記ゲートに直接隣接する第1の段幅を有する第1の段と、前記第1の段に直接隣接する第2の段幅を有する第2の段と、前記第2の段に直接隣接する第3の段幅を有する第3の段と、前記第3の段に直接隣接する第4の段幅を有する第4の段と、を含み、
前記第1の側壁の複数の段における前記第1の段幅の前記第2の段幅に対する比率は、前記第2の側壁の複数の段における前記第1の段幅の前記第2の段幅に対する比率と実質的に同じであり、 前記第1の側壁の第1の段幅、第2の段幅及び第3の段幅の合計は、前記第2の側壁の第1の段幅、第2の段幅及び第3の段幅の合計より大きく、前記第1の段幅と前記第4の段幅とは、前記第2の段幅よりも大きいIII−Nトランジスタ。 - 前記第2の有効角は、前記第1の有効角より実質的に大きい請求項1記載のトランジスタ。
- 前記第2の有効角は、前記第1の有効角より少なくとも10度大きい請求項1記載のトランジスタ。
- 前記III−N材料構造は、第1のIII−N材料層と、第2のIII−N材料層と、前記第1のIII−N材料層及び前記第2のIII−N材料層の間の組成の相違によって、前記第2のIII−N材料層に隣接する前記第1のIII−N材料層内に誘起された2DEGチャネルとを備える請求項1記載のトランジスタ。
- 前記第1のIII−N材料層は、GaNを含み、前記第2のIII−N材料層は、AlGaN、AlInN、AlInGaN又はBAlInGaNを含む請求項4記載のトランジスタ。
- 前記第1のIII−N材料層及び前記第2のIII−N材料層は、第III族面又は[0001]配向、又は第III族終端半極層であり、前記第2のIII−N材料層は、前記第1のIII−N材料層と前記電極画定層との間にある請求項4記載のトランジスタ。
- 前記第1のIII−N材料層及び前記第2のIII−N材料層は、N面又は[000−1]配向又は窒素終端半極層であり、前記第1のIII−N材料層は、前記第2のIII−N材料層と前記電極画定層との間にある請求項4記載のトランジスタ。
- 前記凹部は、前記電極画定層の全体の厚さに亘って延びている請求項4記載のトランジスタ。
- 前記凹部は、前記III−N材料構造内まで延びている請求項8記載のトランジスタ。
- 前記凹部は、前記2DEGチャネルを介して延びている請求項9記載のトランジスタ。
- 前記電極画定層は、SiNxを含む請求項1記載のトランジスタ。
- 前記電極画定層の厚さは、約0.1μm乃至5μmである請求項1記載のトランジスタ。
- 前記III−N材料構造と前記電極画定層との間に誘電性パッシベーション層を更に備え、前記誘電性パッシベーション層は、前記電極に隣接するIII−N材料の表面に直接的に接触する請求項1記載のトランジスタ。
- 前記誘電性パッシベーション層は、SiNxを含む請求項13記載のトランジスタ。
- 前記誘電性パッシベーション層は、前記電極が前記III−N材料構造に直接的に接触しないように、前記電極と前記III−N材料構造との間に設けられている請求項14記載のトランジスタ。
- 前記誘電性パッシベーション層と前記電極画定層との間に更なる絶縁層を更に備える請求項14記載のトランジスタ。
- 前記更なる絶縁層は、AlNを含む請求項16記載のトランジスタ。
- 前記電極の拡張部分は、前記側壁に直接的に接触する請求項1記載のトランジスタ。
- 前記第1の側壁の複数の段における前記第1の段幅の前記第3の段幅に対する比率は、前記第2の側壁の複数の段における前記第1の段幅の前記第3の段幅に対する比率と実質的に同じである請求項1記載のトランジスタ。
- 半導体デバイスを製造する方法であって、
半導体材料構造を準備する工程と、
前記半導体材料構造の表面上に厚さを有する一層の電極画定層を形成する工程と、
前記一層の電極画定層上に幅を有する開口を含むマスク層をパターン化する工程と、
前記一層の電極画定層をエッチングして凹部を形成する工程であって、前記凹部は、前記一層の電極画定層内に、第1の側壁と、前記第1の側壁の反対側の第2の側壁とを有し、前記第1及び第2の側壁は、それぞれ複数の段を有し、前記第1の側壁は、前記半導体材料構造の表面に対して第1の有効角を形成し、前記第2の側壁は、前記半導体材料構造の表面に対して第2の有効角を形成し、前記半導体材料構造から遠い凹部の一部が第1の幅を有し、前記半導体材料構造に近い凹部の一部が第2の幅を有し、前記第1の幅が前記第2の幅より大きい凹部を形成する工程とを有し、
前記エッチングは、第1の手順及び第2の手順の実行を含み、前記第1の手順は、前記電極画定層の一部を除去することを含み、前記第2の手順は、前記マスク層を完全には除去することなく、前記マスク層の一部を除去することを含み、前記第2の手順によって、前記マスク層の開口の幅が増加し、
前記エッチングの結果、前記第2の有効角が前記第1の有効角より大きくなり、
前記電極は、前記トランジスタのゲート領域内にゲートを備え、
前記第1及び第2の側壁の複数の段は、それぞれ前記ゲートに直接隣接する第1の段幅を有する第1の段と、前記第1の段に直接隣接する第2の段幅を有する第2の段と、前記第2の段に直接隣接する第3の段幅を有する第3の段と、前記第3の段に直接隣接する第4の段幅を有する第4の段と、を含み、
前記第1の側壁の複数の段における前記第1の段幅の前記第2の段幅に対する比率は、前記第2の側壁の複数の段における前記第1の段幅の前記第2の段幅に対する比率と実質的に同じであり、
前記第1の側壁の第1の段幅、第2の段幅及び第3の段幅の合計は、前記第2の側壁の第1の段幅、第2の段幅及び第3の段幅の合計より大きく、前記第1の段幅と前記第4の段幅とは、前記第2の段幅よりも大きくする方法。 - 前記エッチングの結果、前記第2の有効角が前記第1の有効角より実質的に大きくなる請求項20記載の方法。
- 前記エッチングの結果、前記第2の有効角が前記第1の有効角より少なくとも10度大きくなる請求項20記載の方法。
- 前記マスク層は、フォトレジストを含む請求項20記載の方法。
- 前記エッチング工程を実行する前に前記マスク層内で前記フォトレジストの再分布を引き起こす工程を更に有する請求項23記載の方法。
- 前記フォトレジストの再分布を引き起こす工程は、前記フォトレジストを熱アニール処理する工程を含む請求項24記載の方法。
- 前記フォトレジストの再分布を引き起こす工程によって、前記開口の一方の側に第1の傾斜側壁を有し、前記開口の他方の側に第2の傾斜側壁を有するマスク層が形成される請求項24記載の方法。
- 前記フォトレジストの再分布を引き起こす工程によって、前記第2の傾斜側壁の傾斜が前記第1の傾斜側壁の傾斜より大きくなる請求項26記載の方法。
- 前記マスク層を除去し、前記凹部内に電極を形成する工程を更に有する請求項20記載の方法。
- 前記エッチングは、前記第2の手順を実行した後に前記第1の手順を再び実行し、前記第1の手順を再び実行した後に前記第2の手順を再び実行することを含む請求項20記載の方法。
- 前記エッチングの結果、前記電極画定層の厚さの全体に延びる凹部が形成される請求項20記載の方法。
- 前記半導体材料構造は、III−N層を含む請求項20記載の方法。
- 半導体デバイスを製造する方法において、
半導体材料構造を準備する工程と、
前記半導体材料構造の表面上に厚さを有する一層の電極画定層を形成する工程と、
前記一層の電極画定層上に、第1の幅を有する複数の領域と、前記第1の幅より狭い第2の幅を有する複数の領域とが交互に現れるパターンを形成する開口を有するマスク層をパターン化する工程と、
前記開口の下の前記一層の電極画定層をエッチングし、凹部を形成する工程とを有し、前記凹部は、第1の側壁及び第2の側壁を有し、前記第1の側壁は、それぞれが前記一層の電極画定層内に前記第1の幅を有する領域の1つに隣接する複数の側壁部(部分)を有し、前記第2の側壁は、それぞれが前記第2の幅を有する領域の1つに隣接する複数の側壁部を有し、
前記エッチングの結果、前記第2の側壁の側壁部の平均傾斜が前記第1の側壁の側壁部の平均傾斜より大きくなり、
前記電極は、前記トランジスタのゲート領域内にゲートを備え、
前記第1及び第2の側壁の複数の段は、それぞれ前記ゲートに直接隣接する第1の段幅を有する第1の段と、前記第1の段に直接隣接する第2の段幅を有する第2の段と、前記第2の段に直接隣接する第3の段幅を有する第3の段と、前記第3の段に直接隣接する第4の段幅を有する第4の段と、を含み、
前記第1の側壁の複数の段における前記第1の段幅の前記第2の段幅に対する比率は、前記第2の側壁の複数の段における前記第1の段幅の前記第2の段幅に対する比率と実質的に同じであり、
前記第1の側壁の第1の段幅、第2の段幅及び第3の段幅の合計は、前記第2の側壁の第1の段幅、第2の段幅及び第3の段幅の合計より大きく、前記第1の段幅と前記第4の段幅とは、前記第2の段幅よりも大きくする方法。 - 前記エッチングは、前記一層の電極画定層の厚さの全体をエッチングし、前記全体のエッチングの間、前記マスク層をエッチングマスクとして使用する請求項32記載の方法。
- 前記エッチングは、更に、前記一層の電極画定層の直下にある層をエッチングする請求項33記載の方法。
- 前記半導体材料構造は、III−N層を含む請求項32記載の方法。
- チャネルを含む半導体材料構造と、
前記チャネルにそれぞれ電気的に接触するソース及びドレインと、
前記ソース及び前記ドレインの間にあり、ゲートと、前記ゲートからドレインに向かって延びる拡張部分とを含む電極とを備えるトランジスタであって、
前記トランジスタのゲート−ドレイン間隔は、20ミクロン未満であり、
前記ゲートが前記ソースに対して前記トランジスタの閾値電圧より低い電圧でバイアスされ、前記トランジスタのドレイン−ソース電圧が約600V以上であるときの前記トランジスタの単位ゲート幅あたりのオフ状態ドレイン電流は、約10−8Amps/mm以下であり、
2マイクロ秒以下の切換時間で前記トランジスタをオンに切り換える際の前記トランジスタの動的オン抵抗は、前記トランジスタのDCオン抵抗の1.1倍未満であるトランジスタ。 - 前記半導体材料構造は、III−N材料を含み、前記チャネルは、前記III−N材料内にある請求項36記載のトランジスタ。
- 前記トランジスタのDCオン抵抗は、12Ωmm未満である請求項36記載のトランジスタ。
- チャネルを含む半導体材料構造と、
前記チャネルにそれぞれ電気的に接触するソース及びドレインと、
前記ソース及び前記ドレインの間にあり、ゲートと、前記ゲートからドレインに向かって延びる拡張部分とを含む電極とを備えるトランジスタであって、
前記トランジスタのゲート−ドレイン間隔は、20ミクロン未満であり、
前記拡張部分は、複数の段を有し、前記拡張部分の長さ1ミクロンあたりの前記複数の段の数は0.4より大であり、
前記ゲートが前記ソースに対して前記トランジスタの閾値電圧より低い電圧でバイアスされ、前記トランジスタのドレイン−ソース電圧が約600V以上であるときの前記トランジスタの単位ゲート幅あたりのオフ状態ドレイン電流は、約10−8Amps/mm以下であるトランジスタ。 - 前記拡張部分の長さは、12ミクロン以下である請求項39記載のトランジスタ。
- 前記トランジスタのDCオン抵抗は、12Ωmm未満である請求項39記載のトランジスタ。
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