TWI555199B - 具有場板的半導體元件 - Google Patents

具有場板的半導體元件 Download PDF

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Publication number
TWI555199B
TWI555199B TW099128303A TW99128303A TWI555199B TW I555199 B TWI555199 B TW I555199B TW 099128303 A TW099128303 A TW 099128303A TW 99128303 A TW99128303 A TW 99128303A TW I555199 B TWI555199 B TW I555199B
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Taiwan
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layer
electrode
etch stop
iii
electrode defining
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TW099128303A
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TW201119033A (en
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儲榮明
可菲羅柏特
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全斯法姆公司
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Description

具有場板的半導體元件
本發明是關於半導體電子元件，特別是具有場板的元件。
迄今，現代功率半導體元件，其包括例如：功率金氧半導體場效電晶體(MOSFET)和絕緣閘極雙極性電晶體(IGBT)之元件，一般是以矽(Si)半導體材料來製作。近來，因碳化矽(SiC)功率元件的優越性質而開始被研究。III族氮化物(III-N)半導體元件目前是新興受矚目的候選者，其可用於承載大電流、支援高電壓及提供很低的電阻、高電壓元件操作和快速切換時間。如第1圖所示，典型的III-N高電子遷移率電晶體(HEMT)包含基板10、在基板上的通道層11(如氮化鎵(GaN)層)、和在通道層上的阻障層12(如AlxGa1-xN層)。二維電子氣體(2DEG)通道19設於通道層11中，其接近通道層11與阻障層12之間的界面處。源極14和汲極15分別構成連接2DEG通道的歐姆觸點(ohmic contact)。閘極16調節位於閘極區的2DEG部分，意即位於閘極16的正下方。
場板通常用於III-N元件來塑形在元件之高場區的電場，藉以降低峰值電場(peak electric field)及提高元件崩潰電壓(device breakdown voltage)，進而容許更高電壓操作。具場板之III-N高電子遷移率電晶體(HEMT)的實例繪示於第2圖。除了第1圖元件所包括的各層外，第2圖元件包括場板18，其連接閘極16，以及位於場板與阻障層12之間的絕緣層13(如氮化矽(SiN)層)。場板18可包括或由與閘極16相同的材料所組成。絕緣層13可當作表面鈍化層，以防止或抑制在絕緣層13與III-N材料相鄰的表面上的電壓波動。
已經證實傾斜場板在降低峰值電場及提高III-N元件的崩潰電壓上特別有效率。第3圖顯示類似第2圖之III-N元件，但其具有傾斜場板28。在此元件中，閘極16和傾斜場板28是由單一電極29所構成。絕緣層23(其可為SiN)含有凹部，其至少界定電極29的部分形狀。在此，絕緣層23將稱為「電極定義層23」。電極定義層23亦可當作表面鈍化層，以防止或抑制在電極定義層23與III-N材料相鄰的表面的電壓波動。此元件之閘極16和傾斜場板28可藉由以下步驟來形成：首先沉積電極定義層23，使其覆蓋阻障層12的整個表面、接著在包含閘極16的區域中蝕刻穿過電極定義層23而形成凹部、以及最後，至少在凹部內沉積電極29。
在許多使用III-N元件的應用中，例如高功率與高電壓應用，為了防止閘極漏電，因此在閘極16與下層的III-N層之間設置閘絕緣體。第4圖顯示具有傾斜場板和閘絕緣體的元件。第4圖的元件可藉由稍微修改第3圖元件之製程來實施。就第4圖的元件而言，在電極定義層23中的凹部僅部分蝕穿該電極定義層(而非完全貫穿該層)，其後沉積電極29。在此元件中，位於閘極16與下層的III-N層間的電極定義層23部分可做為閘絕緣體。
在一態樣中描述III族氮化物(III-N)元件，其包括III-N材料層、位於III-N材料層表面之絕緣層、位於遠離III-N材料層的絕緣層對側之蝕刻終止層、位於遠離絕緣層、遠離蝕刻終止層的蝕刻終止層對側之電極定義層、以及電極。在電極定義層中形成凹部，以及在凹部內形成電極。
對於在此所描述的元件來說，可應用一或多個下列敘述。電極可包括場板。場板可為傾斜場板。在電極定義層中的部分凹部可具有角度壁面(angled wall)，該角度壁面至少一部分與蝕刻終止層的主要表面呈非垂直角度，該角度壁面定義該傾斜場板。非垂直角度可介於約5度至約85度之間。絕緣層可為鈍化層。絕緣層可由氧化物或氮化物所組成。絕緣層的厚度約為2-50奈米。絕緣層的每單位面積電容為約0.8-40毫法拉/平方公尺。電極定義層可由氧化物或氮化物所組成。電極定義層的厚度至少約為100奈米。絕緣層與電極定義層的合併厚度可足以實質抑制分散。蝕刻終止層的厚度約為1至15奈米。蝕刻終止層可由氮化鋁所組成。電極定義層和蝕刻終止層可由不同材料所組成。蝕刻終止層和絕緣層可由不同材料所組成。凹部可形成在蝕刻終止層中。
在一些實施例中，III-N元件為二極體。該二極體可包括一或多個下列特徵。凹部可形成在絕緣層中。第一部分的III-N材料層可具有第一組成，第二部分的III-N材料層可具有第二組成，其中第一組成與第二組成間的差異可在III-N材料層中形成二維電子氣體(2DEG)通道。該二極體包括陰極，其中一部分的電極為陽極，該陽極對III-N材料層形成實質的蕭特基接觸(Schottky contact)，以及該陰極與2DEG通道電氣接觸(electrical contact)。凹部可延伸到III-N材料層中並且該電極位於III-N材料層的一部分凹部內。凹部延伸穿過2DEG通道。在元件之第一區的閾值(threshold)可大於約-15伏特(V)，其中第一區包含部分元件，其位於陽極區與陰極之間並與陽極區相鄰。在元件操作期間，絕緣層的厚度足以防止大於約10微安/毫米的外洩電流通過絕緣層。電極可為陽極電極，且元件更進一步包含陰極。
在一些實施例中，元件為高電子遷移率電晶體(HEMT)。HEMT可包括一或多個下列特徵。第一部分的III-N材料層可具有第一組成，以及第二部分的III-N材料層可具有第二組成，其中第一組成與第二組成間的差異可在III-N材料層中形成2DEG通道。元件可包括源極和汲極，其中部分電極為閘極，並且源極和汲極與2DEG通道電氣接觸。元件閾電壓(threshold voltage)可大於約-30V。選擇絕緣層的厚度，使得元件閾電壓可大於約-30V。在元件操作期間，絕緣層的厚度足以防止大於約100微安的外洩電流通過絕緣層。電極可為閘極電極，且元件更進一步包含源極和汲極。該元件可為場效電晶體(FET)，其中當以約800V或小於800V之源極-汲極偏壓，將元件從關(OFF)狀態切換成開(ON)狀態時，其所測量之動態接通電阻(dynamic on-resistance)是等於或小於直流(DC)接通電阻的1.4倍。
在此所述之任一元件可包括多個場板。具多個場板之元件可包括下列特徵。電極定義層和蝕刻終止層可為第一電極定義層和第一蝕刻終止層，且元件更進一步包含堆疊結構，該堆疊結構位於遠離第一蝕刻終止層的第一電極定義層的對側，其中堆疊結構包含第二蝕刻終止層和第二電極定義層。在堆疊結構中形成凹部，且一部分的電極位於堆疊結構上面。第二絕緣層可位於第一電極定義層與第二蝕刻終止層之間。元件可包括第二電極，其中第二凹部形成在第二電極定義層與第二蝕刻終止層中，且第二電極可形成在第二凹部內。第二電極可電氣連接至第一電極。元件可包括複數個堆疊結構，其中在每一個堆疊結構中形成凹部，且在每一個凹部中形成電極。元件可為加強模態(enhancement-mode)元件或空乏模態(depletion-mode)元件。
在另一態樣中描述形成III-N元件的方法。該方法包括：在III-N材料層的表面上施加絕緣層。在施加絕緣層後，在絕緣層上施加蝕刻終止層。在施加蝕刻終止層後，在蝕刻終止層上施加電極定義層。蝕刻電極定義層而形成凹部，其中藉由非垂直於蝕刻終止層表面的壁面至少部分界定該凹部。蝕刻步驟使用的蝕刻劑是具選擇性的，其蝕刻電極定義層的速率比蝕刻蝕刻終止層的速率快。在凹部內和電極定義層的露出部分上沈積導電材料。
該方法之一或多個實施例可包括一或多個下列特徵。該方法包括蝕刻該蝕刻終止層，使電極定義層中的凹部延伸到絕緣層中。蝕刻該蝕刻終止層可包括溼蝕刻。蝕刻電極定義層可包括乾蝕刻或氟型乾蝕刻。用於蝕刻該蝕刻終止層的蝕刻製程，其實質上不蝕刻電極定義層或絕緣層。該蝕刻製程可以約10：1或更高之選擇率來蝕刻該蝕刻終止層。蝕刻該電極定義層可產生具角度壁面的電極定義層，該角度壁面具有至少一部分與蝕刻終止層的主要表面呈非垂直角度。該非垂直角度約為5度至約85度。用於蝕刻該電極定義層的蝕刻製程，其實質上不蝕刻該蝕刻終止層。該蝕刻製程可以約10：1或更高之選擇率來蝕刻電極定義層。
閘絕緣體一般需製作得很薄，使閘極與2DEG間維持適當耦合，且為了確保元件閾電壓和其他元件參數的再現性，因此通常必須以高度的準確性來控制閘絕緣體的厚度。特別是當需要非常薄的閘絕緣體時，在此所述之技術足以精確地控制閘絕緣體厚度，因此藉由利用此製程可再現製造。
茲描述可再現製造的半導體元件，例如高電子遷移率電晶體(HEMT)和二極體。該等元件皆包括傾斜場板，且某些元件在閘極與下層半導體層之間還包括閘絕緣體。使用傾斜場板可得到具有良好性質的元件，其用於高電壓切換應用，例如高崩潰電壓及在高電壓操作下的最小化分散，而當電晶體結構內含閘絕緣體時，則可減少閘極漏電。此外，該元件的製造製程可利用傳統半導體元件製造製程來再現。該半導體元件可為III族氮化物或III-N半導體元件，故在此所述的元件包括III-N半導體層。在此亦描述形成該元件的方法。
第5圖繪示III族氮化物元件，意即III族氮化物高電子遷移率電晶體(HEMT)。在此，「III族氮化物」或「III-N材料」、層、元件等是指包含化合物半導體材料的材料或元件，該化合物半導體材料為依據化學計量化學式AlxInyGazN，其中x+y+z約為1。元件包括基板層10，其可包括或由矽、藍寶石、氮化鎵(GaN)、氮化鋁(AlN)、碳化矽(SiC)或任何其他適用於III-N元件的基板所組成。在一些實施例中，不包括基板。舉例來說，在一些實施例中，基板已於元件製造完成前被移除。形成於基板10頂部的III-N層11、12為III-N材料，其構成高電子遷移率電晶體(HEMT)元件的基礎。III-N層11、12有不同的組成，選擇該組成使得在層11中誘導2DEG通道，該層11茲稱為「通道層11」。在層12中的一些或所有III-N材料的能量間隙是大於通道層11，故層12茲稱為「阻障層12」。在一些實施例中，通道層11為氮化鎵(GaN)，且阻障層12為AlxGa1-xN，其中x為0至1。其應當理解可實施III-N材料結構的修飾，只要產生的結構可形成III-N高電子遷移率電晶體(HEMT)或其他III-N元件，例如異質接面場效電晶體(HFET)、金屬絕緣體半導體異質接面場效應電晶體(MISHFET)、金氧半導體場效電晶體(MOSFET)、金屬半導體場效電晶體(MESFET)、接面場效電晶體(JFET)、電流孔徑垂直電子電晶體(CAVET)、極化摻雜場效電晶體(POLFET)、高電子遷移率電晶體(HEMT)、場效電晶體(FET)、二極體或其它元件。舉例來說，亦可包含額外的III-N層，例如位於基板10與覆蓋基板的III-N層之間的III-N緩衝層、或位於通道層11與阻障層12間的氮化鋁層(AlN)。III-N層可定向在[0001](III-面或鎵-面C-平面)極性方向、[000](N面)極性方向、或任何其他極性、半極性或非極性方向。在某些實施例中，例如當III-N材料層被定向在[000]方向或在氮-終端半極性方向或在非極性方向時，該阻障層12係介於基板10與通道層11之間。就以上所描述，如第5圖所示，最上層III-N層(意即，離基板最遠的III-N層)為阻障層12，但在一些實施例中，最上層III-N層為通道層11或其它III-N層。
可設計該元件結構而獲得為空乏模態元件的III-N元件，因此當相對源極施加零電壓至閘極時，可在閘極區和通道層11的存取區中誘導2DEG通道19。或者，III-N元件可為加強模態元件，因此當相對源極施加零電壓至閘極時，可在存取區而非通道層11的閘極區中誘導2DEG通道19，並且必須施加正電壓至閘極，用以在通道層11的閘極區中誘導2DEG。在此，「閘極區」是指閘極16正下方的III-N材料區，意即在第5圖中的二條垂直虛線之間。用語「存取區」是指分別在閘極區的側邊和源極14與汲極15之間的元件區。因此，存取區可至少部分地位於傾斜極板28下方。
在一些實施例中，在閘極區中的III-N層結構不同於存取區的III-N層結構(未繪示)。舉例來說，存取區可包括閘極區所沒有的III-N層，反之亦然。在一些實施例中，最上層III-N層陷入閘極區(未繪示)。在最上層III-N層中的凹部部分延伸穿過該層，使得一部分的最上層III-N層於閘極區中被移除。或者，凹部可完全貫穿最上層III-N層並伸入最上層III-N層正下方的III-N層，如此全部的最上層III-N層和最上層III-N層底下的一部分該層可於閘極區中被移除。用於III-N元件的III-N層結構附加實例可參見西元2007年9月17日申請之美國專利申請案號11/856,687、西元2008年4月14日申請之美國專利申請案號12/102,340、西元2008年11月26日申請之美國專利申請案號12/324,574、西元2008年4月23日申請之美國專利申請案號12/108,449、西元2008年12月10日申請之美國專利申請案號12/332,284、西元2009年2月9日申請之美國專利申請案號12/368,248和西元2007年9月17日申請之美國專利申請案號11/856,695，其皆一併附上供作參考。
形成在閘極區對側的源極14和汲極15與通道層11中的2DEG通道19個別地接觸。閘絕緣層22與最高的III-N表面相鄰，且至少從源極14延伸到汲極15。如同第5圖所示的元件，當最上層III-N層在閘極區與存取區中為同一層時，則最上層III-N表面是指在基板10對側的最上層III-N層的表面。在一些實施例中，在閘極區中的最上層III-N層係不同於存取區的最上層III-N層，且在這些實施例中，最上層III-N表面包括最上層III-N層的所有表面，其位於在基板對面的元件側邊，其包括由在最上層III-N層之階梯、凹部或不連續所造成的任何垂直或傾斜表面。
閘絕緣層22可由任何絕緣膜所組成，為了確保有足夠的閘極電容，同時防止實質電流從閘極16經由2DEG通道19流向汲極15，該閘絕緣層可製作得很薄，例如小於約50奈米(nm)，例如小於或約為22nm、18nm或15nm，。舉例來說，閘絕緣層22的厚度可約為2-50nm，並由二氧化矽(SiO2)或氮化矽(SiN)所構成，且利用諸如化學氣相沉積(CVD)、金屬有機化學氣相沉積(MOCVD)、高溫化學氣相沉積(HTCVD)、濺鍍、蒸鍍之方法、或其它適合沉積的技術來沉積。在一些實施例中，閘絕緣層22由高介電係數(高K)的介電質所組成，例如二氧化鉿(HfO2)、過氧化鈦(Ti2O5)或二氧化鋯(ZrO2)。相較於使用同樣厚度的低介電係數介電質，高K介電質將產生更大的閘極電容。因此，當使用高K介電質時，閘絕緣層22不需製作得像低介電係數介電質一樣薄。舉例來說，當使用高K介電質時，假如閘絕緣層厚度約為2000nm或以下、約為1000nm或以下、或約為500nm或以下，即可達到足夠的閘極電容。
閘絕緣層22可製作得夠厚，以避免在元件操作期間，實質外洩電流(意即，外洩電流大於約100微安)流過閘絕緣層22。舉例來說，閘絕緣層22可能需製作成厚度大於約2nm，以實質抑制外洩電流。在一些實施例中，該元件為空乏模態元件(意即，元件閾電壓小於0V)，且選擇閘絕緣層22的厚度使得元件的閾電壓約為-30V或更大(意即，較小負值)，例如介於約-30V至0V之間。當在閘極區之2DEG為實質耗乏電荷時(意即，電荷密度約小於元件中最大2DEG電荷密度的1%)，該元件的閾電壓為最大電壓。在其他實施例中，選擇閘絕緣層22的厚度，使得該層的每單位面積電容約為0.8-40毫法拉/平方公尺。
由於閘絕緣層22直接與在元件存取區中的最上層III-N表面接觸，故其本身或結合在存取區中的覆蓋層後也能當作有效表面鈍化層，此將說明於後。在此所使用的，「鈍化層」是指生成或沉積在III-N元件中的最上層III-N層頂部的任何層或組合層，其可防止或抑制在元件操作期間，存取區中的最上層III-N表面的電壓波動。舉例來說，鈍化層可防止或抑制在最上層III-N表面的表面/界面狀態形成，或者其可防止或抑制在元件操作期間，表面/界面狀態捕集電荷的能力。
在III-N元件中，最上層III-N表面的電壓波動常因為在元件操作期間，表面狀態帶電所引起，其已知會造成不當影響，例如分散。分散是指當元件在射頻(RF)或切換條件下操作相較於當元件在直流(DC)條件下操作時所觀察到的電流-電壓(I-V)特徵差異。以有機金屬化學汽相沈積(MOCVD)來沉積之薄SiN層(如22nm)已證實可形成用於III-N元件之特效閘絕緣體，當結合適當的覆蓋層21、23後，其又可同時做為存取區之適當鈍化層，此將說明於後。
在一些實施例中，蝕刻終止層21形成於與閘絕緣層22直接相鄰的元件存取區中，在蝕刻終止層21的頂部形成電極定義層23。電極定義層23具有位於源極14與汲極15之間的凹部，意即在元件存取區之間的區域。在一些實施例中，蝕刻終止層21亦陷入此區域中。電極29共形沉積(conformally deposited)於凹部。電極29位於閘極區上方並往汲極15的方向延伸，使得一部分的電極29位於一部分的電極定義層23上面。位於閘極區上方的一部分電極29(意即，位於二垂直虛線間)為閘極16，在最靠近汲極15的一側上，與閘極16相鄰的部分電極29為傾斜場板28。在一些實施例中，往汲極15的方向延伸的部分電極29位於電極定義層23的至少一部分側壁24上面，但不覆蓋電極定義層23的非傾斜部分(未繪示)。即，往汲極15方向延伸的電極29的整個部分是容納在電極定義層23中的凹部內。在其他實施例中，電極29完全容納在電極定義層23中的凹部內且位於至少一部分的側壁24上面。
從第5圖清楚可知，傾斜場板的形狀部分地藉由凹部的形狀來定義，意即電極定義層23的側壁24的輪廓。對於在此所使用的「傾斜場板」，其至少一部分定義場板形狀的下表面的角度相對於在閘極區之最上層III-N表面約為5度至85度(如約10度至70度)。舉例來說，在第5圖中假如角度25約為5度至85度，那麼傾斜場板28則定義為傾斜場板。此外，側壁24不一定要有線性輪廓，其輪廓可為線性、拋物線或其他形狀，只要側壁24的至少一實質部分的角度相對閘極區之最上層III-N的表面約為5度至85度即可。在一些實施例中，相對於閘極區之最上層III-N表面，該定義場板形狀的下表面的實質部分角度約為30度至45度。
在最靠近源極14之閘極側的部分電極定義層23在與電極29相鄰的區域亦為傾斜，在此區域中的斜率是由角度26所定義。在此區域中的斜率可為固定不變或有所變化。在一些實施例中，角度25、26大致為相同，然在其他實施例中，二者不同。使藉由角度26來定義斜率之側壁比側壁24更傾斜，其對於降低閘極-源極電容是有利的。在一些實施例中，角度26約為45度至90度，例如約80度至90度。
為了形成具有側壁24之電極定義層23，其符合傾斜場板形成所需規格，同時容許十分精確地控制閘極16底下區域的閘絕緣層22的厚度，可採取以下製造程序。在一連串的III-N層上沉積或生成閘絕緣層22後，沉積蝕刻終止層21使其覆蓋整個結構，其後在各處沉積電極定義層23使其覆蓋該蝕刻終止層21。接著，採行具下列性質之蝕刻製程來移除位於閘極區上方的一部分電極定義層23材料。該蝕刻製程蝕刻電極定義層23之材料並產生側壁(如上述的側壁24)，但不實質蝕刻該蝕刻終止層21之材料。在一些實施例中，蝕刻製程以實質上比蝕刻該蝕刻終止層21之材料快的速率來蝕刻電極定義層23之材料，例如至少快約10倍、或快約10至10000倍。換言之，蝕刻製程以約10：1或更高之選擇率來蝕刻電極定義層23。在一實施例中，該蝕刻製程為乾蝕刻，例如反應離子蝕刻(RIE)或感應耦合電漿蝕刻(ICP)，其中蝕刻遮罩包括二層光阻，意即雙層光阻製程，在未遮蔽區域中，下光阻層底切(undercut)該上光阻層。此製程的完整敘述可參見Dora等人於IEEE Electron Device Letters，Vol 27，No 9，pp 713-715發表之文章「在具整合式傾斜場板之AlGaN/GaN高電子遷移率電晶體上達到高崩潰電壓(HIGH BREAKDOWN VOLTAGE ACHIEVED ON ALGAN/GAN HEMTS WITH INTEGRATED SLANT FIELD PLATES)」，其一併附上供作參考。在另一實施例中，該蝕刻製程為乾蝕刻，例如反應離子蝕刻(RIE)或感應耦合電漿蝕刻(ICP)，其中做為蝕刻遮罩的光阻具有傾斜側壁，且亦可被所採用之乾蝕刻技術蝕刻。
接著，採行具下列性質之第二蝕刻製程來移除位於閘極區上方的部分蝕刻終止層21材料。第二蝕刻製程蝕刻該蝕刻終止層21之材料，但不實質蝕刻該閘絕緣層22之材料。第二蝕刻製程可以實質上比蝕刻閘絕緣層22之材料快的速率來蝕刻該蝕刻終止層21之材料，例如至少快約10倍、或快約10至10000倍。在一些實施例中，第二蝕刻製程實質上亦無法蝕刻電極定義層23之材料。
蝕刻終止層21可由絕緣材料所構成，例如AlN、SiN、SiO2或其他絕緣材料，其有不同組成、或為不同於閘絕緣層22的材料。不同材料或組成可讓蝕刻步驟具選擇性。更明確地說，蝕刻終止層21可由以下所描述的材料所組成：在蝕刻製程中可蝕刻該蝕刻終止層21但又不實質蝕刻任何閘絕緣層22之材料。舉例來說，因為氫氧化鉀(KOH)基溼蝕刻其可用來蝕刻AlN，但實質上不蝕刻SiN，所以當閘絕緣層22由SiN所組成時，蝕刻終止層21可由AlN所組成。另外，若蝕刻終止層21很薄，例如小於約15nm(如約5nm)，則可防止蝕刻終止層21遭實質側向蝕刻。側向蝕刻會在電極定義層23底下與閘極16相鄰的區域產生底切。若在此區域出現底切，其可能造成在底切正下方的區域將無法足夠鈍化該最上層III-N的表面，因而造成不當影響，例如分散。在一些實施例中，蝕刻終止層21藉由濺鍍沉積之AlN所組成且其厚度約為5nm。
電極定義層23由絕緣材料所組成，例如AlN、SiN或SiO2，其有不同組成、或為不同於蝕刻終止層21的材料。不同材料或組成可讓蝕刻步驟具選擇性。更明確地說，電極定義層23可由以下所描述的材料所組成：在蝕刻製程中可蝕刻電極定義層23並形成如上所述側壁24之側壁，同時不實質蝕刻該蝕刻終止層21之材料。舉例來說，因為氟基乾蝕刻其可蝕刻SiN，但實質上不蝕刻AlN，所以當蝕刻終止層21由AlN所組成時，電極定義層23可由SiN所組成，並且如前所述，當使用適當光阻蝕刻遮罩時，可形成如上所述側壁24之側壁。此外，為了有效降低由傾斜場板所產生的峰值電場，電極定義層23的厚度可約為100nm或更厚，例如約100nm至200nm，例如約120nm。電極定義層23的最佳厚度是部分取決於在電路或模組中所採用的元件操作電壓。舉例來說，若採用較高的操作電壓，則最好有較厚的電極定義層23，例如約200nm至2000nm。在一些實施例中，電極定義層23藉由以電漿輔助化學氣相沉積(PECVD)所沉積之SiN來組成且其厚度約為120nm。
結合閘絕緣層22、蝕刻終止層21與電極定義層23可在元件存取區中構成適合之鈍化層。與最上層III-N表面相鄰的閘絕緣層22可防止或抑制在最上層III-N表面的表面/界面狀態形成，或者其可防止或抑制在元件操作期間，表面/界面狀態捕集電荷的能力。為適當防止或抑制藉由在最上層III-N表面之表面/界面狀態所引起的分散，閘絕緣層22的厚度需達約2nm或更厚。然而，使閘絕緣層22變厚會降低元件的互導(transconductance)，進而降低元件性能。
為避免在蝕刻終止層21對側之電極定義層23表面上的電壓波動造成實質分散，電極定義層23與閘絕緣層22的合併厚度需足夠厚，例如約100nm或更厚。電極定義層23與閘絕緣層22實質上可抑制分散所需的最小合併厚度是取決於元件操作電壓(意即，在操作期間，源極與汲極間的最大電壓差)。舉例來說，就高達約50V的操作而言，合併厚度可約為120nm或更厚；就高達約300V的操作而言，合併厚度可約為800nm或更厚；以及就高達約600V的操作而言，合併厚度可約為1800nm或更厚。由於期望閘絕緣層22的厚度很小，例如約20nm，因此電極定義層23的厚度幾乎或大致和此二層的最小合併厚度一樣。因為單獨的較厚層難以製造，故需形成附加層，以達到在高操作電壓下可實質抑制分散所需的最小合併層厚度。此元件繪示於第12a及13圖，且將進一步說明於後。
在傳統III-N元件中，在許多情況下，厚度大於約30nm之SiN單層(即未與蝕刻終止層或電極定義層結合的單一層)已證實適合當作鈍化層。在高元件操作電壓下，相較於較薄的SiN單層，較厚的SiN單層可改善鈍化或有效鈍化。至於第5圖的元件，就高達約50V的元件操作而言，當使用以有機金屬化學汽相沈積(MOCVD)所生成之2-20nm的SiN層做為閘絕緣層22、使用以濺鍍沉積之1-15hm的AlN層做為蝕刻終止層21、和使用以電漿輔助化學汽相沈積(PECVD)所沉積之100-200nm的SiN層做為電極定義層23時，其已證實可達到適當的鈍化效果。此亦顯示增加蝕刻終止層21的厚度將導致元件遭受更大分散，以致降低元件性能。舉例來說，元件製造唯一改變的參數為AlN蝕刻終止層21的厚度。這些元件因AlN蝕刻終止層21的厚度增加而呈現更大分散。
具有傾斜場板與閘絕緣體的III-N元件亦可省略第5圖的蝕刻終止層21來實施，並選擇作為可藉由蝕刻製程而被蝕刻的電極定義層23之材料，該蝕刻製程可選擇性的蝕刻電極定義層23的材料，而不實質蝕刻閘絕緣層22之材料。然而，第5圖的結構比此結構有利，因為其難以找到適合做為III-N元件之閘絕緣體，同時又可當作電極定義層23材料之蝕刻終止層，並且又同時能結合電極定義層23的材料做為適合鈍化層的閘絕緣層22的材料。
形成第5圖元件的方法繪示於第6-11圖。參照第6圖，將至少包括通道層11和阻障層12的一連串III-N層形成在基板10上，而於通道層11中構成2DEG 19。III-N層可利用諸如有機金屬化學汽相沈積(MOCVD)、分子束磊晶(MBE)、氫化物氣相磊晶(HVPE)之方法、或其他方法來磊晶成長。接著，參見第7圖，在一連串III-N層的頂部上形成閘絕緣層22。閘絕緣層22可利用諸如有機金屬化學汽相沈積(MOCVD)、電漿輔助化學汽相沈積(PECVD)、高溫化學汽相沈積(HTCVD)、濺鍍、蒸鍍之方法、或其他方法來生成或沉積。在一些實施例中，閘絕緣層22是以與III-N層相仿或相同的方法來形成，且可在同一步驟中形成。舉例來說，III-N層和閘絕緣層22皆可利用有機金屬化學汽相沈積(MOCVD)來沉積或生成。
接著，參照第8圖，分別在包含源極14與汲極15之區域中將閘絕緣層22移除，以及利用諸如蒸鍍、濺鍍、電漿輔助化學汽相沈積(PECVD)、高溫化學汽相沈積(HTCVD)之方法、或其他方法來形成與2DEG 19接觸的源極14與汲極15。在一些實施例中，源極14與汲極15是在形成閘絕緣層22之前形成。
參照第9圖，接著在閘絕緣層22上方形成蝕刻終止層21，在蝕刻終止層21上形成電極定義層23。接著，參見第10圖，將蝕刻遮罩17(如光阻)沉積在所示區域的電極定義層23上，並且利用蝕刻電極定義層23之材料，但不實質蝕刻該蝕刻終止層21之材料的技術來蝕刻未遮蔽區域的電極定義層23。此蝕刻可於蝕刻區域中形成傾斜側壁24。因此，該蝕刻可精確地停止在電極定義層23與蝕刻終止層21的界面。參照第11圖，移除蝕刻遮罩17，以及利用蝕刻該蝕刻終止層21之材料，但不實質蝕刻電極定義層23或閘絕緣層22之材料的技術來蝕刻在閘極區中的蝕刻終止層21。該蝕刻終止層具有主要表面，該主要表面為接合電極定義層且當蝕穿電極定義層時所露出的表面。故蝕刻可精確地停止在蝕刻終止層21與閘絕緣層22的界面上。最後，形成電極29，其包括閘極16和傾斜場板28，藉以完成第5圖所示元件。
在第5圖元件之一實施例中，III-N層和閘絕緣層22皆利用有機金屬化學汽相沈積(MOCVD)來生成，並以單一成長步驟來形成。閘絕緣層22包括或由SiN所組成且其厚度約為22nm。蝕刻終止層21包括或由AlN所組成，其利用蒸鍍或濺鍍來沉積且其厚度約為5nm。電極定義層23包括或由SiN所組成，其利用電漿輔助化學汽相沈積(PECVD)來沉積且其厚度約為120nm。如第10圖所示，蝕刻遮罩17為光阻，並經圖案化使得該側壁為實質傾斜。或者，該蝕刻遮罩可為雙層光阻，其中下光阻層相對上光阻層呈底切結構。在閘極區中的電極定義層23是利用氟基乾蝕刻來移除，例如反應離子蝕刻(RIE)或感應耦合電漿蝕刻(ICP)，其可蝕刻SiN，但不實質蝕刻AlN，故當使用具實質傾斜側壁之光阻或雙層光阻做為蝕刻遮罩時，可形成如上所述第5圖側壁24之側壁。在閘極區中的蝕刻終止層21是利用KOH基溼蝕刻移除，其可蝕刻AlN、但不實質蝕刻SiN。
茲已製造如第5圖中具有單一場板之元件，其動態接通電阻(以高達40V之源極-汲極偏壓將元件從OFF狀態切換成ON狀態時所測量)不超過DC接通電阻(RON)的1.2倍。當飽和電流為50mA/mm時，平均DC RON約為11.5歐姆-釐米(Ω-mm)，而以40V之源極-汲極偏壓切換元件時測量之平均動態RON約為11.9歐姆-釐米。在做為切換應用的半導體電晶體中，分散會導致元件的動態接通電阻提高。在無傾斜場板的元件中，例如第5圖元件，分散會造成動態接通電阻太高而不適合元件應用。第5圖元件的分散可保持夠小，意即實質抑制該分散，因此使動態接通電阻可為元件應用所接受。
第12a圖為元件的示意圖，其包括閘絕緣體和兩個傾斜場板。第12a圖的元件與第5圖的元件相同，但其更包括絕緣層32、第二蝕刻終止層31、第二電極定義層33和包括第二傾斜場板38的電極39。相較於第5圖元件，額外的第二傾斜場板38更可降低在元件操作期間的元件峰值電場，因此更進一步提高元件的崩潰電壓及減少分散、或在比第5圖元件可行電壓更高的電壓下產生足夠小的分散。
第二電極定義層33和第二蝕刻終止層31分別類似電極定義層23和蝕刻終止層21。即，第二電極定義層33可由絕緣材料所組成，例如AlN、SiN或SiO2，其有不同組成、或為不同於第二蝕刻終止層31的材料。此外，第二電極定義層33可包含以下所述材料：在蝕刻製程中可蝕刻電極定義層33並形成如上所述第5圖側壁24之側壁，且又不實質蝕刻第二蝕刻終止層31之材料。舉例來說，因為氟基乾蝕刻可蝕刻SiN，但實質上不蝕刻AlN，所以當第二蝕刻終止層31為AlN時，第二電極定義層33可為SiN，且當採用適當光阻蝕刻遮罩時，可形成如上述第5圖側壁24之側壁。在一些實施例中，第二電極定義層33的厚度約為10nm至1000nm，例如約500nm。在一些實施例中，第二電極定義層33藉由以電漿輔助化學氣相沉積(PECVD)所沉積之SiN來組成且其厚度約為500nm。
第二蝕刻終止層31可由絕緣材料所組成，例如AlN、SiN或SiO2，其有不同組成、或為不同於底下絕緣層32和不同於第二電極定義層33的材料。第二蝕刻終止層31可包含以下所述材料：在蝕刻製程中可蝕刻該蝕刻終止層31之材料，但又不實質蝕刻任何底下絕緣層32或第二電極定義層33之材料。舉例來說，因為KOH基溼蝕刻實質上不蝕刻SiN，但可用來蝕刻AlN，所以當底下絕緣層32和第二電極定義層33為SiN時，第二蝕刻終止層31可為AlN。另外，為了防止第二蝕刻終止層31遭實質側向蝕刻而在第二電極定義層33底下產生底切，該第二蝕刻終止層31可以很薄，例如小於約15nm(如約5nm)。在一些實施例中，第二蝕刻終止層31藉由以濺鍍沉積之AlN所組成且其厚度約為5nm。
在第12a圖的元件中形成電極39和相鄰層的方法與上述在第5圖的元件中形成電極29和相鄰層的方法相仿或相同。此外，電極39和電極29(為便於說明，其標繪於第5圖，但未標繪於第12a圖)可從外部或在元件周邊上電氣連接，如此第二傾斜場板38為閘極連接場板(未繪示)。在此，假如兩個或多個觸點或其他項目藉由足夠導電之材料連接，該材料可確保在各觸點或其他項目的電位在所有時候為相同(意即大致相同)，該兩個或多個觸點或其他項目則稱為「電氣連接」。另外，此元件可利用與上述電極39和相鄰層相仿或相同的製程和結構來增設附加傾斜場板，其亦可為閘極連接場板。
絕緣層32(其可為SiN)隔開電極39和電極29，並在蝕刻第二蝕刻終止層31時，保護電極29不被破壞。在一些實施例中，不包含絕緣層32，在此例子中電極39直接與在主動元件區中的電極29連接。
繪示在第12a圖的元件之一實施例中，III-N層和閘絕緣層22皆利用有機金屬化學汽相沈積(MOCVD)來生成，並以單一成長步驟形成。閘絕緣層22為SiN且其厚度約為22nm。蝕刻終止層21包括或由AlN組成，其利用蒸鍍或濺鍍來沉積且其厚度約為5nm。電極定義層23為SiN，其利用電漿輔助化學汽相沈積(PECVD)來沉積且其厚度約為120nm。如第10圖所示，蝕刻遮罩17是由光阻所組成，並經圖案化使側壁呈實質傾斜或具底切結構，藉以在底下電極定義層23中定義具傾斜側壁之溝槽。在閘極區中利用氟基乾蝕刻(例如反應離子蝕刻(RIE)或感應耦合電漿蝕刻(ICP)，其可蝕刻SiN，但不實質蝕刻AlN)來移除電極定義層23，故當採用適當光阻蝕刻遮罩時，可形成如上述第5圖側壁24之側壁。在閘極區中利用KOH基溼蝕刻(其可蝕刻AlN、但不實質蝕刻SiN)來移除蝕刻終止層21。絕緣層32為以電漿輔助化學汽相沈積(PECVD)所沉積之SiN且其厚度約為200nm。第二蝕刻終止層31為以蒸鍍或濺鍍所沉積之AlN且其厚度約為5nm。第二電極定義層33為以電漿輔助化學汽相沈積(PECVD)所沉積之SiN且其厚度約為500nm。第二電極定義層是利用氟基乾蝕刻來蝕刻，例如反應離子蝕刻(RIE)或感應耦合電漿蝕刻(ICP)，其蝕刻SiN，但不實質蝕刻AlN，且當採用適當光阻蝕刻遮罩時，可形成如上述第5圖側壁24之側壁。第二蝕刻終止層31是利用KOH基溼蝕刻來蝕刻，其蝕刻AlN，但不實質蝕刻SiN。
茲已製造如第12a圖中具有兩個傾斜場板之元件，其動態接通電阻(以高達200V之源極-汲極偏壓將元件從OFF狀態切換成ON狀態時所測量)不超過DC接通電阻(RON)的1.2倍。當飽和電流為50mA/mm時，平均DC RON約為11.5歐姆-釐米，而以200V之源極-汲極偏壓切換元件時所測量之平均動態RON亦約為11.5歐姆-釐米。在做為切換應用的半導體電晶體中，分散會導致元件的動態接通電阻提高。在不具有多個傾斜場板的元件中，例如第12a圖中的元件，分散會造成動態接通電阻太高而不適合元件應用。在第12a圖元件中的分散可保持夠小，意即可實質抑制分散，因此使動態接通電阻可為元件應用所接受。
茲已製造類似第12a圖、但具有三個傾斜場板之元件，其動態接通電阻(以高達600V之源極-汲極偏壓將元件從OFF狀態切換成ON狀態時所測量)不超過DC接通電阻(RON)的1.2倍。第12b圖為顯示這些元件之平均RON對應汲極電壓(Vd)的曲線圖。這些元件的平均DC RON約為170毫歐姆(mΩ)，而以600V之源極-汲極偏壓將元件從OFF狀態切換成ON狀態時測量之平均動態RON為約200毫歐姆。
茲已製造類似第12a圖，但具有四個傾斜場板之元件，其動態接通電阻(以高達800V之源極-汲極偏壓將元件從OFF狀態切換成ON狀態時所測量)不超過DC接通電阻(RON)的1.4倍。第12c圖為顯示這些元件之平均RON對應汲極電壓(Vd)的曲線圖。這些元件的平均DC RON約為1000毫歐姆，然而當以800V之源極-汲極偏壓將元件從OFF狀態切換成ON狀態時測量之平均動態RON為約1400毫歐姆。
第13圖顯示另一元件，其包括閘絕緣層22和兩個傾斜場板28及38。此元件類似第12圖中的元件，除了在主動元件區中兩個傾斜場板28及38是互相連接，並由單一金屬沉積而構成。舉例來說，包括元件閘極16與傾斜場板28、38的電極49可以單一步驟來沉積。因為可簡化製造製程及降低閘極電阻，所以此元件比第12a圖中的元件更具優勢。
在第13圖元件中的電極49和與電極49相鄰之層可依下述方法來形成。閘絕緣層22、第一蝕刻終止層21、第一電極定義層23、第二蝕刻終止層31和第二電極定義層33皆沉積在主動半導體元件層上。如前所述，接著在層33的頂部將蝕刻遮罩(如光阻)圖案化，及利用不蝕刻層31之材料並在層33內形成傾斜側壁的蝕刻製程於層33內形成開口。接著利用可蝕刻層31之材料，但不蝕刻層33或層23之材料的蝕刻製程來蝕刻該層31鄰接開口的部分。在蝕刻層33之前或之後，將沉積於層33頂部的圖案化蝕刻遮罩移除。接著，將第二蝕刻遮罩(如光阻)沉積在元件上，使得層33、31之露出表面和區域59外側露出的層23部分被蝕刻遮罩材料所覆蓋，但蝕刻遮罩材料不覆蓋在區域59內露出的層23部分。如前所述，接著利用不蝕刻層21之材料並在層23內形成傾斜側壁的蝕刻製程來蝕刻層23而形成開口。最後，移除第二蝕刻遮罩，及利用可蝕刻層21之材料，但不蝕刻層22或層23之材料的蝕刻製程來蝕刻層21鄰接層23內的開口的部分。
包括傾斜場板28之二極體繪示於第14及15圖中，其中第14圖為元件的截面圖，第15圖為元件的平面圖。第15圖中的平面圖顯示陽極觸點61與陰極觸點60各自的佈局。雖然陽極與陰極觸點在第15圖中呈圓形，但其通常可為任何適用電路佈局的形狀。該二極體包括III-N通道層11和阻障層12，其含有2DEG通道19且類似第5圖元件的III-N層。陽極觸點61由單一電極或複數個電極所組成，且直接接觸底下半導體材料。陰極觸點60接觸2DEG通道19，並緊鄰至少一部分的陽極觸點61。陰極觸點60為歐姆觸點、或實質展現歐姆行為，以及陽極觸點61為蕭特基觸點、或形成連接至底下III-N層的實質蕭特基觸點。陰極觸點60可為單一陰極觸點。在此，該用語「單一陰極觸點」是指當作陰極的單一金屬觸點、或做為多個陰極的複數個觸點，其電氣連接使得各觸點的電位大致相同。陽極觸點61與陰極觸點60可具任何任意形狀，然而該形狀必須經理想最佳化來減少特定順向電流(forward current)所需的元件面積。
介電層62由絕緣體或介電質所組成，且在元件存取區中與最上層III-N的表面相鄰。介電層62本身或結合在存取區中之覆蓋層後能當作有效表面鈍化層。層21為蝕刻終止層，以及層23為電極定義層，其要求分別與第5圖元件的蝕刻終止層和電極定義層類似或相同。
第14及15圖之二極體依下述來操作。當在陽極觸點61的電壓小於陰極觸點60的電壓，使得陽極觸點61與III-N層12間的蕭特基接面為逆向偏壓時，二極體處於OFF狀態，且陽極與陰極之間無實質電流流動。當在陽極觸點61的電壓大於陰極觸點60的電壓，使得陽極觸點61與III-N層12間的蕭特基接面為順向偏壓時，二極體處於ON狀態。電子主要從陰極觸點60流經2DEG通道19，然後流過順向偏壓之蕭特基接面而至陽極觸點61。即，至少99%的總順向偏壓電流從陽極經由蕭特基阻障層與2DEG通道流向陰極。具有少量外洩電流可流經其他路徑，例如沿著元件表面。
第16圖中的元件類似第14圖的元件，除了在陽極區64中，III-N材料凹陷貫穿III-N阻障層12並部分穿過III-N通道層11，使凹部延伸穿過包含2DEG的區域。在此情況下，陽極觸點61構成實質蕭特基觸點至其直接接觸的一些或所有III-N層。在一些實施例中，凹部只部分延伸穿過III-N層12，且不延伸貫穿包含2DEG通道的區域(未繪示)。在逆向偏壓操作期間，在陽極觸點部分66正下方的2DEG通道19部分(意即，介電層62正上方且與介電層62相鄰的陽極觸點部分)可為耗乏電子，藉以減少在元件中的逆向外洩電流。在陽極觸點部分66正下方的2DEG通道19部分為在元件存取區中的2DEG通道部分，意即介於陽極區64與陰極觸點60之間的區域，且侷限於與陽極區64相鄰的區域。在逆向偏壓操作期間，為了使陽極觸點部分66正下方的2DEG通道19部分變得耗乏電子，介電層62不能太厚。在一些實施例中，介電層62為氮化矽且其厚度小於約50nm，例如約2nm至50nm。介電層62可製作得足夠厚，以避免實質外洩電流(意即外洩電流大於約100微安/微米)從陽極經由在陽極觸點部分66正下方區域之介電層62流向陰極。舉例來說，介電層62可能需製作成厚度大於約2nm，以實質抑制外洩電流。在一些實施例中，選擇介電層62的厚度，使得在陽極觸點部分66正下方區域的元件的閾電壓約為-15V或更大(即較小負值或較大正值)，例如介於約-15V至-1V之間。，當在陽極觸點部分66正下方區域之2DEG為實質耗乏電荷時(即電荷密度小於元件中最大2DEG電荷密度的約1%)，該陽極觸點部分66正下方區域的閾電壓為最大電壓。在其他實施例中，選擇閘絕緣層22的厚度使該層的每單位面積電容約為0.8-40毫法拉/平方公尺。在一些實施例中，介電層62為SiN，並以金屬有機化學氣相沉積(MOCVD)來沉積之。
若介電層62為比氮化矽更高介電係數的介電質，則介電層可製作得更厚。舉例來說，藉由使用高介電係數的介電質做為介電層62，其可製作得比設計讓此區域得到同樣閾電壓的SiN層還厚，即可能使陽極觸點部分66正下方區域達到預定閾電壓。
其他已知有益於元件性能的特徵結構也可包含在第5、12a及13-16圖的結構中。其包含但不以此為限，將在閘極及/或存取區的III-N層進行表面處理、或在通道層11與基板10之間設置III-N緩衝層，例如具有比通道層11大的能量間隙的III-N層。該半導體層不必然為III-N層，而是由其他半導體材料所組成。場板不必然為傾斜場板，而是其他類型的場板。這些特徵結構可個別或互相結合使用。
10．．．基板
11．．．通道層/III-N層
12．．．阻障層/III-N層
13．．．絕緣層
14．．．源極
15．．．汲極
16．．．閘極
17．．．遮罩
18、28、38．．．場板
19．．．2DEG通道
21、31．．．蝕刻終止層
22．．．閘絕緣層
23、33．．．電極定義層
24．．．側壁
25、26．．．角度
29、39、49．．．電極
32．．．絕緣層
59．．．區域
60、61．．．觸點
62．．．介電層
64．．．陽極區
66．．．觸點部分
第1-4圖為先前技術之III-N高電子遷移率電晶體(HEMT)元件的截面示意圖。
第5圖為含有閘絕緣體與傾斜場板之III-N半導體電晶體的截面示意圖。
第6-11圖繪示形成第5圖的III-N半導體電晶體的方法。
第12a圖為含有閘絕緣體與傾斜場板之III-N半導體電晶體的截面示意圖。
第12b及12c圖為顯示III-N半導體電晶體之接通電阻對應汲極電壓的曲線圖。
第13圖為含有閘絕緣體與傾斜場板之III-N半導體電晶體的截面示意圖。
第14及15圖分別為含有傾斜場板之III-N半導體二極體的截面圖和平面圖。
第16圖為含有傾斜場板之III-N半導體二極體的截面示意圖。
各圖中相同的元件符號代表相同的元件。
10．．．基板
11．．．通道層
12．．．阻障層
14．．．源極
15．．．汲極
16．．．閘極
19．．．2DGE通道
21．．．蝕刻終止層
22．．．閘絕緣層
23．．．電極定義層
24．．．側壁
25、26．．．角度
28．．．場板
29．．．電極

Claims (58)

  1. 一種III族氮化物(III-N)元件，其包含：一III-N材料層；一絕緣層，其位於該III-N材料層之一表面上；一蝕刻終止層，其位於遠離該III-N材料層的該絕緣層之一對側；一電極定義層，其位於遠離該絕緣層、遠離該蝕刻終止層的該蝕刻終止層之一對側，其中該電極定義層和該蝕刻終止層是一第一電極定義層和一第一蝕刻終止層；一堆疊結構，其位於遠離該第一蝕刻終止層的該第一電極定義層之一對側，其中該堆疊結構包含一第二蝕刻終止層和一第二電極定義層；以及一電極，其中在該電極定義層中形成一凹部，且在該凹部中形成該電極。
  2. 如申請專利範圍第1項之元件，其中在該堆疊結構中形成該凹部，以及該電極之一部分是在遠離該第一電極定義層之該堆疊結構的一對側之上。
  3. 如申請專利範圍第1項之元件，進一步包含一第二絕緣層，位在該第一電極定義層和該第二蝕刻終止層之間。
  4. 如申請專利範圍第3項之元件，進一步包含一第二電 極，其中在該第二電極定義層中形成一第二凹部，且在該第二凹部中形成該第二電極。
  5. 如申請專利範圍第4項之元件，其中該第二電極與該第一電極電氣接觸。
  6. 如申請專利範圍第1項之元件，進一步包含複數個堆疊結構，其中在各堆疊結構中形成一凹部，且在各凹部中形成一電極。
  7. 如申請專利範圍第1至6項中任一項之元件，其中該電極包括一場板。
  8. 如申請專利範圍第7項之元件，其中該場板是一傾斜場板。
  9. 如申請專利範圍第1至6項中任一項之元件，其中該電極定義層中之該凹部的一部分具有多個角度壁面，該角度壁面至少一部分與該蝕刻終止層的一主要表面呈一非垂直角度，該多個角度壁面定義一傾斜場板。
  10. 如申請專利範圍第9項之元件，其中該非垂直角度是介於約5度至約85度之間。
  11. 如申請專利範圍第1至6項中任一項之元件，其中該絕緣層為一鈍化層。
  12. 如申請專利範圍第1至6項中任一項之元件，其中該絕緣層是由氧化物或氮化物所形成。
  13. 如申請專利範圍第12項之元件，其中該絕緣層的厚度約為2-50奈米。
  14. 如申請專利範圍第1至6項中任一項之元件，其中該絕緣層的每單位面積電容約為0.8-40毫法拉/平方公尺。
  15. 如申請專利範圍第1至6項中任一項之元件，其中該電極定義層是由氧化物或氮化物所形成。
  16. 如申請專利範圍第15項之元件，其中該電極定義層的厚度至少約為100奈米。
  17. 如申請專利範圍第1項之元件，其中該絕緣層與該電極定義層的一合併厚度是足以實質抑制分散。
  18. 如申請專利範圍第1至6項中任一項之元件，其中該蝕刻終止層的厚度是介於約1奈米至約15奈米之間。
  19. 如申請專利範圍第18項之元件，其中該蝕刻終止層是由氮化鋁所形成。
  20. 如申請專利範圍第1至6項中任一項之元件，其中該電極定義層和該蝕刻終止層是由不同材料所形成的。
  21. 如申請專利範圍第1至6項中任一項之元件，其中該蝕刻終止層和該絕緣層是由不同材料所形成的。
  22. 如申請專利範圍第1至6項中任一項之元件，其中該凹部是形成在該蝕刻終止層中。
  23. 如申請專利範圍第22項之元件，其中該凹部是形成在該絕緣層中。
  24. 如申請專利範圍第23項之元件，其中該III-N材料層的一第一部分具有一第一組成，該III-N材料層的一第二部分具有一第二組成，其中該第一組成與該第二組成間的一差異在該III-N材料層中形成二維電子氣體(2DEG)通道。
  25. 如申請專利範圍第24項之元件，進一步包含一陰極，其中該電極的一部分為一陽極，該陽極構成一實質 蕭特基(Schottky)觸點至該III-N材料層，以及該陰極與該2DEG通道電氣接觸。
  26. 如申請專利範圍第25項之元件，其中該凹部延伸至該III-N材料層中，且該電極位於該III-N材料層中該凹部的一部分內。
  27. 如申請專利範圍第26項之元件，其中該凹部延伸穿過該2DEG通道。
  28. 如申請專利範圍第27項之元件，其中該元件之一第一區的一閾電壓大於約-15伏特(V)，其中該第一區包含該元件的一部分，該元件的一部分是介於一陽極區與該陰極之間並與該陽極區相鄰。
  29. 如申請專利範圍第27項之元件，其中該絕緣層的厚度是足以防止在元件操作期間，大於約10微安/毫米的外洩電流通過該絕緣層。
  30. 如申請專利範圍第1至6項中任一項之元件，其中該III-N材料層的一第一部分具有一第一組成，該III-N材料層的一第二部分具有一第二組成，其中該第一組成與該第二組成間的一差異在該III-N材料層中形成一2DEG通道。
  31. 如申請專利範圍第30項之元件，進一步包含一源極和一汲極，其中該電極的一部分為一閘極，且該源極和該汲極與該2DEG通道電氣接觸。
  32. 如申請專利範圍第31項之元件，其中一元件閾電壓係大於約-30伏特。
  33. 如申請專利範圍第32項之元件，其中該絕緣層的一厚度係使得該元件閾電壓大於約-30伏特。
  34. 如申請專利範圍第32項之元件，其中該絕緣層的一厚度是足以在元件操作期間，避免大於約100微安的外洩電流通過該絕緣層。
  35. 如申請專利範圍第1至6項中任一項之元件，其中該元件為一場效電晶體(FET)，且當以800伏特或以下之一源極-汲極偏壓，將元件從關(OFF)狀態切換成開(ON)狀態時，所測量之一動態接通電阻為等於或小於一直流(DC)接通電阻的1.4倍。
  36. 如申請專利範圍第1至6項中任一項之元件，其中該電極為一閘電極，且該元件進一步包含一源極和一汲極。
  37. 如申請專利範圍第1至6項中任一項之元件，其中該電極為一陽極電極，且該元件進一步包含一陰極。
  38. 如申請專利範圍第1至6項中任一項之元件，其中該凹部包括一第一側壁和一第二側壁，該第一側壁位於遠離該第二側壁的該凹部之一對側，該第一和第二側壁各自從該電極定義層之一第一表面延伸至該電極定義層之一第二表面，該第一表面相鄰於該蝕刻終止層，且該第二表面相對於該第一表面，該蝕刻終止層之一表面與相鄰於該蝕刻終止層之該第一側壁的一部分之間形成一第一角度，該蝕刻終止層之該表面與相鄰於該蝕刻終止層之該第二側壁的一部分之間形成一第二角度，其中該第一角度大於該第二角度。
  39. 如申請專利範圍第38項之元件，其中該電極是一閘電極，該閘電極形成在該第一和第二側壁上。
  40. 如申請專利範圍第39項之元件，進一步包含在該凹部之相對側上形成一源極和一汲極，其中該源極接近於該第一側壁，而該汲極接近於該第二側壁。
  41. 如申請專利範圍第1至6項中任一項之元件，其中當以600伏特或以下之一源極-汲極偏壓，將元件從關狀 態切換成開狀態時，所測量之一動態接通電阻為不大於一直流接通電阻的1.2倍。
  42. 一種形成一元件的方法，其包含以下步驟：在一III-N材料層的一表面上施加一絕緣層；在施加該絕緣層後，在該絕緣層上施加一蝕刻終止層；在施加該蝕刻終止層後，在該蝕刻終止層上施加一電極定義層；蝕刻該電極定義層而形成一凹部，其中該蝕刻步驟使用具選擇性之一蝕刻劑，其蝕刻該電極定義層的一速率比蝕刻該蝕刻終止層的一速率快；以及在該凹部內和該電極定義層的一露出部分上沉積一導電材料。
  43. 如申請專利範圍第42項之方法，其中該電極定義層和該蝕刻終止層為一第一電極定義層和一第一蝕刻終止層，該方法進一步包含形成一堆疊結構，其位於遠離該第一蝕刻終止層的該第一電極定義層之一對側，其中該堆疊結構包含一第二蝕刻終止層和一第二電極定義層。
  44. 如申請專利範圍第43項之方法，其中該凹部形成於該堆疊結構中，且該電極的一部分位於遠離該第一電極定義層的該堆疊結構之一對側。
  45. 如申請專利範圍第43項之方法，進一步包含形成一第二絕緣層，其位於該第一電極定義層與該第二蝕刻終止層之間。
  46. 如申請專利範圍第45項之方法，進一步包含形成一第二電極，其中在該第二電極定義層中形成一第二凹部，且在該第二凹部內形成該第二電極。
  47. 如申請專利範圍第46項之方法，其中該第二電極與該第一電極電氣接觸。
  48. 如申請專利範圍第43項之方法，進一步包含形成複數個堆疊結構，其中在各堆疊結構中形成一凹部，且在各凹部中形成一電極。
  49. 如申請專利範圍第42至48項中任一項之方法，進一步包含蝕刻該蝕刻終止層，使得在該電極定義層中的該凹部延伸到該絕緣層。
  50. 如申請專利範圍第49項之方法，其中蝕刻該蝕刻終止層之步驟包含溼蝕刻。
  51. 如申請專利範圍第49項之方法，其中用於蝕刻該蝕 刻終止層的一蝕刻製程，其實質上不蝕刻該電極定義層或該絕緣層。
  52. 如申請專利範圍第51項之方法，其中該蝕刻製程以與該絕緣層相比約為10：1或更高之一選擇率來蝕刻該蝕刻終止層。
  53. 如申請專利範圍第42至48項中任一項之方法，其中蝕刻該電極定義層之步驟包含乾蝕刻。
  54. 如申請專利範圍第53項之方法，其中蝕刻該電極定義層之步驟包含應用一氟基乾蝕刻。
  55. 如申請專利範圍第42至48項中任一項之方法，其中蝕刻該電極定義層將產生具有多個角度壁面的該電極定義層，該角度壁面至少一部分與該蝕刻終止層的一主要表面呈一非垂直角度。
  56. 如申請專利範圍第55項之方法，其中該非垂直角度是介於約5度至約85度之間。
  57. 如申請專利範圍第42至48項中任一項之方法，其中用於蝕刻該電極定義層的一蝕刻製程，其實質上不蝕刻該蝕刻終止層。
  58. 如申請專利範圍第57項之方法，其中該蝕刻製程以與該蝕刻終止層相比約為10：1或更高之一選擇率來蝕刻該電極定義層。
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