CN102598275B - 具有场板的半导体器件 - Google Patents
具有场板的半导体器件 Download PDFInfo
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- CN102598275B CN102598275B CN201080048522.9A CN201080048522A CN102598275B CN 102598275 B CN102598275 B CN 102598275B CN 201080048522 A CN201080048522 A CN 201080048522A CN 102598275 B CN102598275 B CN 102598275B
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- layer
- electrode
- limit given
- etching stopping
- electric limit
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- 239000012212 insulator Substances 0.000 claims abstract description 132
- 239000000463 material Substances 0.000 claims abstract description 104
- 238000005530 etching Methods 0.000 claims description 186
- 238000000034 method Methods 0.000 claims description 75
- 229910017083 AlN Inorganic materials 0.000 claims description 33
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 claims description 33
- 230000008569 process Effects 0.000 claims description 27
- 239000000203 mixture Substances 0.000 claims description 20
- 239000006185 dispersion Substances 0.000 claims description 19
- 238000002161 passivation Methods 0.000 claims description 16
- 238000001312 dry etching Methods 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 10
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims description 7
- 229910052731 fluorine Inorganic materials 0.000 claims description 7
- 239000011737 fluorine Substances 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 18
- 239000000758 substrate Substances 0.000 description 15
- 230000004888 barrier function Effects 0.000 description 13
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 11
- 238000004544 sputter deposition Methods 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 238000009616 inductively coupled plasma Methods 0.000 description 7
- 238000001020 plasma etching Methods 0.000 description 7
- 230000005684 electric field Effects 0.000 description 6
- 230000008020 evaporation Effects 0.000 description 6
- 238000001704 evaporation Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000004062 sedimentation Methods 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 5
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
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- 229910052751 metal Inorganic materials 0.000 description 3
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- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
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- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- 241000854350 Enicospilus group Species 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- LKJPSUCKSLORMF-UHFFFAOYSA-N Monolinuron Chemical compound CON(C)C(=O)NC1=CC=C(Cl)C=C1 LKJPSUCKSLORMF-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
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- 230000005611 electricity Effects 0.000 description 1
- 238000002248 hydride vapour-phase epitaxy Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
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Abstract
描述了一种III-N器件,其具有III-N材料层,位于III-N材料层表面上的绝缘体层,位于绝缘体层的相对于III-N材料层的相反侧上的蚀刻停止层,以及位于蚀刻停止层相对于蚀刻停止层的相对于绝缘体层的相反侧上的电极限定层。凹陷形成在电极限定层中。电极形成在凹陷中。绝缘体能够具有精确控制的厚度,尤其是在电极和III-N材料层之间。
Description
技术领域
本发明涉及半导体电子器件,具体地涉及具有场板的器件。
背景技术
迄今为止,包括诸如功率MOSFET和绝缘栅双极晶体管(IGBT)的器件的现代功率半导体器件已经通常利用硅(Si)半导体材料来制作。最近,由于碳化硅(SiC)的优异性质而对碳化硅(SiC)功率器件进行了研究。III族氮化物(III-N)半导体器件现在作为承载大电流并且支持高电压并且提供非常低的导通电阻、高电压器件操作以及快速切换时间的候选者而受到了很大关注。图1中所示的通常的III-N高电子迁移率晶体管(HEMT)包括衬底10、位于衬底顶上的诸如GaN层的沟道层11、以及位于沟道层顶上的诸如AlxGa1-xN的阻挡层12。二维电子气(2DEG)沟道19被诱导在沟道层11中且在沟道层11和阻挡层12之间的界面附近。源电极14和漏电极15分别形成与2DEG沟道的欧姆接触。栅极16调制位于栅极区域中、即,位于栅极16正下方的2DEG的部分。
在III-N器件中通常使用场板来以这种方式对器件的高电场区域中的电场进行整形,使得减少了峰值电场并且增加了器件击穿电压,从而允许更高电压操作。在图2中示出了具有场板的III-N HEMT的示例。除了图1的器件中包括的层之外,图2中的器件包括连接到栅极16的场板18;以及在场板和阻挡层12之间的、诸如SiN层的绝缘体层13。场板18可以包括与栅极16相同的材料或者由与栅极16相同的材料形成。绝缘体层13可以用作表面钝化层,阻止或者抑制与绝缘体层13相邻的III-N材料的表面处的电压波动。
斜场板已经显示出了对于在III-N器件中减少峰值电场并且增加击穿电压是特别有效的。在图3中示出了类似于图2的III-N器件,但是其具有斜场板28。在该器件中,栅极16和斜场板28由单个电极29形成。可以是SiN的绝缘体层23包含至少部分地限定电极29的形状的凹陷。在此,绝缘体层23将被称为“电极限定层23”。电极限定层23还可以作为表面钝化层,阻止或者抑制与电极限定层23相邻的III-N材料的表面处的电压波动。该器件中的栅极16和斜场板28可以通过下述方式来形成:首先在阻挡层12的整个表面上沉积电极限定层23,然后在包含栅极16的区域中蚀刻穿过电极限定层23的凹陷,并且最终至少在该凹陷中沉积电极29。
在使用III-N器件的很多应用中,例如,在高功率和高电压应用中,可以有利的是,包括位于栅极16和下面的III-N层之间的栅极绝缘体以便于防止栅极泄漏。在图4中示出了具有斜场板和栅极绝缘体的器件。该器件可以通过略微修改用于图3中的器件的工艺来实现。对于图4中的器件,电极限定层23中的凹陷仅被部分地蚀刻穿过该层(而不是整体穿过该层),之后沉积电极29。在该器件中,位于栅极16和下面的III-N层之间的电极限定层23的部分用作栅极绝缘体。
发明内容
在一方面,描述了一种III-N器件,其包括III-N材料层;绝缘体层,其位于III-N材料层的表面上;蚀刻停止层,其位于绝缘体层的相对于III-N材料层的相反侧上;电极限定层,其位于蚀刻停止层的相对于蚀刻停止层的相对于绝缘体层的相反侧上;以及电极。凹陷形成在电极限定层中并且电极形成在凹陷中。
对于这里描述的所有器件,可应用下面所述中的一个或多个。电极可以包括场板。场板可以是斜场板。电极限定层中的凹陷的一部分可以具有成角度的壁,该成角度的壁的至少一部分相对于蚀刻停止层的主表面成非垂直角度,该成角度的壁限定斜场板。非垂直角度可以处于大约5度和85度之间。绝缘体层可以是钝化层。绝缘体层可以由氧化物或者氮化物形成。绝缘体层可以是大约2-50纳米厚。绝缘体层可以具有大约0.8-40毫法/平方米的每单位面积电容。电极限定层可以由氧化物或者氮化物形成。电极限定层可以为至少大约100纳米厚。绝缘体层和电极限定层的组合厚度能够足以基本上抑制分散(dispersion)。蚀刻停止层的厚度可以为大约1和15纳米之间。蚀刻停止层可以由氮化铝形成。电极限定层和蚀刻停止层可以由不同材料形成。蚀刻停止层和绝缘体层可以由不同材料形成。凹陷可以形成在蚀刻停止层中。
在一些实施中,III-N器件是二极管。该二极管可以包括下述特征中的一个或多个。凹陷可以形成在绝缘体层中。III-N材料层的第一部分可以具有第一组成并且III-N材料层的第二部分可以具有第二组成,其中第一组成和第二组成之间的差异形成了III-N材料层中的2DEG沟道。二极管可以包括阴极,其中电极的一部分是阳极,该阳极形成与III-N材料层的实质性肖特基接触,并且阴极与2DEG沟道电接触。凹陷可以延伸到III-N材料层中并且电极处于III-N材料层中的凹陷的一部分中。凹陷可以延伸穿过2DEG沟道。器件的第一区域的阈值可以大于大约-15V,其中第一区域包括位于阳极区域和阴极之间并且与阳极区域相邻的器件的部分。绝缘体层的厚度可以足以防止大于大约10微安/毫米的泄漏电流在器件操作期间通过绝缘体层。电极可以是阳极电极并且器件可以进一步包括阴极。
在一些实施中,器件是HEMT。HEMT可以包括下述特征中的一个或多个。III-N材料层的第一部分可以具有第一组成并且III-N材料层的第二部分可以具有第二组成,其中第一组成和第二组成之间的差异形成III-N材料层中的2DEG沟道。器件可以包括源极和漏极,其中电极的一部分是栅极,并且源极和漏极与2DEG沟道电接触。器件阈值电压可以大于大约-30V。绝缘体层的厚度可以被选择为器件阈值电压大于大约-30V。绝缘体层的厚度可以足以防止大于大约100微安的泄漏电流在器件操作期间通过绝缘体层。电极可以是栅极电极并且器件可以进一步包括源极和漏极。器件可以是FET,其中当以大约800V或更少的源极-漏极偏置将器件从截止状态切换到导通状态时测量的动态导通电阻等于或小于DC导通电阻的1.4倍。
这里描述的任何器件可以包括多个场板。具有多个场板的器件可以包括下述特征。电极限定层和蚀刻停止层可以是第一电极限定层和第一蚀刻停止层,器件可以进一步包括第一电极限定层的相对于第一蚀刻停止层的相反侧上的堆叠,其中该堆叠包括第二蚀刻停止层和第二电极限定层。凹陷可以形成在堆叠中,并且电极的一部分覆在该堆叠上。第二绝缘体层可以位于第一电极限定层和第二蚀刻停止层之间。器件可以包括第二电极,其中第二凹陷形成在第二电极限定层中和第二蚀刻停止层中,并且第二电极可以形成在第二凹陷中。第二电极可以电连接到第一电极。器件可以包括多个堆叠,其中凹陷形成在每个堆叠中,并且电极形成在每个凹陷中。器件可以是增强模式器件或者耗尽模式器件。
在另一方面,描述了一种形成III-N器件的方法。该方法包括将绝缘体层施加到III-N材料层的表面上。在施加绝缘体层之后,将蚀刻停止层施加在绝缘体层上。在施加蚀刻停止层之后,将电极限定层施加在蚀刻停止层上。蚀刻电极限定层以形成凹陷,其中通过不垂直于蚀刻停止层的表面的壁来至少部分地限定凹陷。蚀刻步骤使用具有选择性从而以比蚀刻蚀刻停止层更快的速率蚀刻电极限定层的蚀刻剂。导电材料沉积在凹陷中和电极限定层的暴露部分上。
该方法的一个或多个实施可以包括下述特征中的一个或多个。该方法可以包括蚀刻蚀刻停止层以将电极限定层中的凹陷延伸到绝缘体层。蚀刻蚀刻停止层可以包括湿法蚀刻。蚀刻蚀刻停止层可以包括干法蚀刻或基于氟的干法蚀刻。用于蚀刻蚀刻停止层的蚀刻工艺可以基本上不蚀刻电极限定层或者绝缘体层。蚀刻工艺可以以大约10∶1或更高的选择性蚀刻蚀刻停止层。蚀刻电极限定层可以导致电极限定层具有成角度的壁,该成角度的壁的至少一部分相对于蚀刻停止层的主表面成非垂直角度。非垂直角度可以处于大约5度和85度之间。用于蚀刻电极限定层的蚀刻工艺可以基本上不蚀刻蚀刻停止层。蚀刻工艺可以以大约10∶1或更高的选择性蚀刻电极限定层。
栅极绝缘体通常需要被制成很薄以保持栅极和2DEG沟道之间的足够耦合,并且通常,栅极绝缘体的厚度必须被控制到很高的精度以便于确保器件阈值电压和其它器件参数的可再现性。这里描述的技术可以导致栅极绝缘体厚度的足够精确的控制,尤其是在要求非常薄的栅极绝缘体的情况下,并且因此使用该工艺的可再现的制造是可能的。
附图说明
图1-4是现有技术的III-N HEMT器件的示意性横截面图。
图5是包含栅极绝缘体和斜场板的III-N半导体晶体管的示意性横截面图。
图6-11示出了形成图5的III-N半导体晶体管的方法。
图12a是包含栅极绝缘体和斜场板的III-N半导体晶体管的示意性横截面图。
图12b和图12c是示出用于III-N半导体晶体管的导通电阻与漏电压的曲线图。
图13是包含栅极绝缘体和斜场板的III-N半导体晶体管的示意性横截面图。
图14和图15分别是包含斜场板的III-N半导体二极管的示意性横截面图和平面图。
图16是包含斜场板的III-N半导体二极管的示意性横截面图。
在各附图中,相同的附图标记表示相同的元件。
具体实施方式
描述了可以进行可再现制造的、诸如HEMT和二极管的半导体器件。器件都包括斜场板,并且一些器件还包括位于栅极和下面的半导体层之间的栅极绝缘体。斜场板的使用可以导致具有对于高电压切换应用的优异性质的器件,诸如在高电压操作时的高击穿电压和最小分散,而当在晶体管结构中包括栅极绝缘体时,栅极绝缘体可以导致栅极泄漏减少。此外,用于这些器件的制造工艺可以使用传统的半导体器件制作工艺来再现。半导体器件可以是III族氮化物或者III-N半导体器件,并且因此这里描述的器件包括III-N半导体层。还描述了形成器件的方法。
图5示出了III族氮化物器件、即III族氮化物HEMT的示意性视图。如这里使用的,术语III族氮化物或者III-N材料、层、器件等等是指由根据化学计量式AlxInyGazN,其中x+y+z大约为1的化合物半导体材料构成的材料或器件。器件包括衬底层10,衬底层10可以包括硅、蓝宝石、GaN、AlN、SiC或者任何其它适合于在III-N器件中使用的衬底或者由上述形成。在一些实施中,不包括衬底。例如,在一些实施中,在完成器件制作之前移除衬底。形成在衬底10上面的III-N层11和12是形成HEMT器件的基础的III-N材料。III-N层11和12具有不同的组成,该组成被选择为使得在层11中诱导2DEG沟道19,该层11从而被称为“沟道层11”。层12中的III-N材料的一些或全部具有大于沟道层11的带隙的带隙,从而层12被称为“阻挡层12”。在一些实施中,沟道层11是GaN并且阻挡层12是AlxGa1-xN,其中x处于0和1之间。理解的是,可以对III-N材料结构进行修改,只要获得的结构是可以利用其来形成III-N HEMT或者其它III-N器件,诸如HFET、MISHFET、MOSFET、MESFET、JFET、CAVET、POLFET、HEMT、FET、二极管或者另外的器件的结构。例如,还可以包括额外的III-N层,诸如位于衬底10和上面的III-N层之间的III-N缓冲层,或者位于沟道层11和阻挡层12之间的AlN层。III-N层可以取向为[0001](III-面或者Ga-面C-面)极性方向、(N-面)极性方向或者任何其它极性、半极性或者非极性取向。在一些实施中,阻挡层12位于衬底10和沟道层11之间,诸如,当III-N材料取向为方向或者氮基半极性方向或者非极性方向时。因此,虽然最上面的III-N层、即距离衬底最远的III-N层在图5中被示出为是阻挡层12,但是在一些实施中,最上面的III-N层可以是沟道层11或者另外的III-N层。
器件结构可以被设计为使得获得的III-N器件是耗尽模式器件,从而当相对于源极将零电压施加到栅极时在沟道层11的接入区域和栅极区域中诱导2DEG沟道19。或者,III-N器件可以是增强模式器件,从而当相对于源极将零电压施加到栅极时,在沟道层11的接入区域而不是栅极区域中诱导2DEG沟道19,并且必须将正电压施加到栅极以在沟道层11的栅极区域中诱导2DEG。如这里使用的,术语“栅极区域”指栅极16正下方的III-N材料中的区域、即图5中的两个竖直虚线之间的区域。术语“接入区域(access region)”指分别位于栅极区域的任一侧上且位于源电极14和漏电极15之间的器件的区域。因此,接入区域可以至少部分地位于斜场板28下方。
在一些实施中,栅极区域中的III-N层结构不同于接入区域(未示出)中的III-N层结构。例如,接入区域可以包括没有被包括在栅极区域中的III-N层,或者反之亦然。在一些实施中,最上面的III-N层在栅极区域中凹陷(未示出)。最上面的III-N层中的凹陷可以部分地延伸穿过该层,从而最上面的III-N层的一部分被在栅极区域中移除。或者,凹陷可以完全延伸穿过最上面的III-N层并且延伸进入到位于最上面的III-N层正下面的III-N层中,从而最上面的III-N层的全部以及位于最上面的III-N层的层的一部分在栅极区域中被移除。用于III-N器件的III-N层结构的额外的示例可以参见下面的文献:2007年9月17日提交的美国专利申请No.11/856687;2008年4月14日提交的美国专利申请No.12/102340;2008年11月26日提交的美国专利申请No.12/324574;2008年4月23日提交的美国专利申请No.12/108449;2008年12月10日提交的美国专利申请No.12/332284;2009年2月9日提交的美国专利申请No.12/368248;以及2007年9月17日提交的美国专利申请No.11/856695,上述文献都通过引用并入这里。
形成在栅极区域的相对侧上的源电极14和漏电极15分别接触沟道层11中的2DEG沟道19。栅极绝缘体层22与最上面的III-N表面相邻并且至少从源电极14延伸到漏电极15。当最上面的III-N层在栅极区域和接入区域两者中是同一层时(即,图5中所示的器件的情况),最上面的III-N表面指最上面的III-N层的相对于衬底10相反侧的表面。在一些实施中,栅极区域中的最上面的III-N层不同于接入区域中的最上面的III-N层,并且在这些实施中,最上面的III-N表面包括位于器件的相对于衬底的相反侧上的所有表面,这些表面包括可以由最上面的III-N层中的台阶、凹陷或者不连续造成的任何垂直或者成角度的表面。
栅极绝缘体层22由可以被制成为薄的任何绝缘膜形成,以便于确保足够高的栅极电容,同时防止实质性电流从栅极16通过2DEG沟道19流动到漏电极15,其中形成栅极绝缘体层22的所述绝缘膜的厚度诸如小于大约50nm,诸如小于大约22nm、18nm或者15nm。例如,栅极绝缘体层22可以为大约2-50nm厚,可以由SiO2或者SiN形成,并且可以通过诸如化学气相沉积(CVD)、有机金属化学气相沉积(MOCVD)、高温化学气相沉积(HTCVD)、溅射、蒸镀或者其它适合的沉积技术来沉积。在一些实施中,栅极绝缘体层22由诸如HfO2、Ti2O5或者ZrO2的高介电常数(高K)电介质形成。与当使用相同厚度的较低的介电常数的电介质时的情况相比,高K电介质导致较高的栅极电容。因此,当使用高K电介质时,栅极绝缘体层22可以不需要被制成为如使用较低介电常数电介质时那样薄。例如,当使用高K电介质时,如果栅极绝缘体层的厚度为大约2000nm或者更小、大约1000nm或更小、或大约500nm或更小,可能能够实现足够大的栅极电容。
栅极绝缘体层22可以被制成为足够厚,使得可以防止实质性泄漏电流、即大于大约100微安的泄漏电流在器件操作期间流过栅极绝缘体层22。例如,可以需要使栅极绝缘体层22的厚度大于大约2nm以基本上抑制泄漏电流。在一些实施中,器件是耗尽模式器件(即,器件阈值电压小于0V),并且栅极绝缘体层22的厚度被选择为器件具有大约-30V或更大(即,负的程度更少的、诸如大约-30V和0V之间的阈值电压。器件的阈值电压是这样的最大电压:在该最大电压下栅极区域中的2DEG基本上耗尽电荷、即具有小于器件中的最大2DEG电荷密度的大约1%的电荷密度。在其它实施中,栅极绝缘体层22的厚度被选择为使得层的每单位面积的电容为大约0.8-40毫法/平方米。
由于栅极绝缘体层22直接接触器件接入区域中的最上面的III-N表面,因此,栅极绝缘体层22还能够自己或者与接入区域中的上面的层组合地用作有效表面钝化层,如下面将详细描述的。如这里使用的,“钝化层”指在III-N器件中的最上面的III-N层的顶部生长或者沉积的、可以防止或抑制器件操作期间在接入区域中最上面的III-N表面处的电压波动的任何层或层的组合。例如,钝化层可以防止或者抑制在最上面的III-N表面处的表面/界面态的形成,或者可以防止或者抑制表面/界面态在器件操作期间捕获电荷的能力。
在III-N器件中,常常由器件操作期间的表面态的充电引起的最上面的III-N表面处的电压波动已知导致诸如分散的不期望的效果。分散指当器件在RF或者切换条件下运行时相对于当器件在DC条件下运行时观察到的电流-电压(I-V)特性的差别。通过MOCVD沉积例如22nm的薄SiN层已经被示出为形成用于III-N器件的特别有效的栅极绝缘体,同时当与适当的上覆的层21和23组合时同时用作接入区域中足够的钝化层,将在下面对此进行描述。
在一些实施中,蚀刻停止层21形成在与栅极绝缘体层22直接相邻的器件接入区域中,在蚀刻停止层21上面形成有电极限定层23。电极限定层23具有位于源电极14和漏电极15之间、即位于器件接入区域之间的区域中的凹陷。在一些实施中,蚀刻停止层21也在该区域中凹陷。电极29共形地沉积在凹陷中。电极29覆在栅极区域上并且朝向漏电极15延伸,从而电极29的一部分位于电极限定层23的一部分上。覆在栅极区域的电极29上的部分、即位于两个竖直虚线之间的电极29的部分是栅极16,并且在离漏电极15最近一侧上与栅极16相邻的电极29的部分是斜场板28。在一些实施中,朝向漏电极15延伸的电极29的部分覆在电极限定层23的侧壁24的至少一部分上,但是没有覆在电极限定层23的非倾斜部分上(未示出)。即,朝向漏电极15延伸的电极29的整个部分包含在电极限定层23中的凹陷内。在其它实施中,电极29整体包含在电极限定层23中的凹陷内并且覆在侧壁24的至少一部分上。
从图5中显而易见的是,斜场板的形状部分地由凹陷的形状限定,即由电极限定层23的侧壁24的轮廓限定。如这里使用的,“斜场板”是下述场板,限定该场板的形状的下面的表面的至少一部分相对于栅极区域中的最上面的III-N表面处于大约5度和85度之间的角度,诸如大约10度和70度之间的角度。例如,如果角度25处于大约25度和85度之间,则图5中的斜场板28被限定为斜场板。另外,侧壁24不需要具有线性轮廓,其可以具有线性、抛物线或者其它形状的轮廓,只要侧壁24的至少大部分相对于栅极区域中最上面的III-N表面处于大约5度至85度的角度。在一些实施中,限定场板的形状的下面的表面的大部分相对于栅极区域中最上面的III-N表面的角度处于大约30和45度之间。
位于最靠近电极14的源极侧上的电极限定层23的部分也可以在与电极29相邻的区域中倾斜,其中通过角度26来限定该区域中的倾斜。该区域中的倾斜可以是恒定的或者可以变化。在一些实施中,角度25和26大约相同,而在其它实施中,它们是不同的。可以有利的是,通过角度26给定倾斜的侧壁比侧壁24更陡峭,这是因为这可以减少栅极-源极电容。在一些实施中,角度26处于大约45和90度之间,诸如处于大约80和90度之间。
为了形成具有侧壁24的电极限定层23,可以使用下述制作过程,其中侧壁24满足斜场板的形成所要求的规格并且同时允许栅极绝缘体层22,可以以足够的精度控制栅极绝缘体层22在栅极16下面的区域中的厚度。在一系列III-N层上沉积或生长栅极绝缘体层22之后,将蚀刻停止层21沉积在整个结构上,其后在蚀刻停止层21上各处沉积电极限定层23。接下来,使用具有下述性质的蚀刻工艺来移除位于栅极区域上面的电极限定层23的材料的一部分。蚀刻工艺蚀刻电极限定层23的材料并且产生诸如对于侧壁24所述侧壁的侧壁,但是该蚀刻工艺基本上没有蚀刻蚀刻停止层21的材料。在一些实施中,蚀刻工艺以比蚀刻蚀刻停止层21的材料的速率实质上更高的速率蚀刻电极限定层23的材料,诸如,以至少大约10倍高的速率,或者以大约10倍高和10000倍高之间的速率。换言之,蚀刻工艺以大约10∶1或更高的选择性来蚀刻电极限定层23。在一个实施中,蚀刻工艺是干法蚀刻,诸如反应离子蚀刻(RIE)或电感耦合等离子体蚀刻(ICP),其中蚀刻掩膜包括两层光致抗蚀剂,即,双层抗蚀工艺,在未掩膜区域中,下面的光致抗蚀剂层底切(undercut)上覆的光致抗蚀剂层。该工艺的完整描述可以参考文献:Dora等人在IEEE Electron Device Letters的Vol 27,No 9,pp 713-715中公开的“HIGH BREAKDOWN VOLTAGEACHIEVED ON ALGAN/GAN HEMTS WITH INTEGRATED SLANTFIELD PLATES”,其通过引用完全并入这里。在另一实施中,蚀刻工艺是干法蚀刻,诸如反应离子蚀刻(RIE)或电感耦合等离子体蚀刻(ICP),其中用作蚀刻掩膜的光致抗蚀剂具有倾斜侧壁并且也可以被使用的干法蚀刻技术蚀刻。
接下来,使用具有下述性质的第二蚀刻工艺来移除位于栅极区域上面的蚀刻停止层21的材料的部分。第二蚀刻工艺蚀刻蚀刻停止层21的材料,但是基本上没有蚀刻栅极绝缘体层22的材料。第二蚀刻工艺可以以比蚀刻蚀刻栅极绝缘体层22的材料的速率实质上更高的速率蚀刻蚀刻停止层21的材料,诸如,以至少大约10倍高的速率,或者以大约10倍高和10000倍高之间的速率。在一些实施中,第二蚀刻工艺也不可以实质性地蚀刻电极限定层23的材料。
蚀刻停止层21可以由与栅极绝缘体层22不同组成或者是不同材料的诸如AlN、SiN、SiO2或者另外的绝缘材料的绝缘材料形成。不同材料或者组成允许蚀刻步骤的选择性。具体地,蚀刻停止层21可以由这样的材料形成:对于该材料,蚀刻工艺可以蚀刻蚀刻停止层21的材料而基本上没有蚀刻栅极绝缘体层22的任何材料。例如,当栅极绝缘体层22由SiN形成时,蚀刻停止层21可以由AlN形成,这是因为可以使用基本上不蚀刻SiN的基于KOH的湿法蚀刻来蚀刻AlN。此外,如果蚀刻停止层21是薄的,诸如小于大约15nm,诸如大约5nm,则可以防止蚀刻停止层21的实质性横向蚀刻。横向蚀刻可以导致与栅极16相邻的区域中的电极限定层23下面的底切。如果在该区域中存在底切,则可能的是,最上面的III-N表面将不会在位于该底切正下面的区域中被充分地钝化,这可以导致诸如分散的不期望的效果。在一些实施中,蚀刻停止层21由通过溅射沉积而沉积的AlN形成并且为大约5nm厚。
电极限定层23由具有与蚀刻停止层21不同组成或者是不同材料的诸如AlN、SiN或者SiO2的绝缘材料形成。不同材料或者组成允许蚀刻步骤的选择性。具体地,电极限定层23可以由这样的材料形成:对于该材料,蚀刻工艺可以蚀刻电极限定层23的材料并且产生诸如对于侧壁24所述侧壁的侧壁而基本上没有蚀刻蚀刻停止层21的材料。例如,当蚀刻停止层21由AlN形成时,电极限定层23可以由SiN形成,这是因为当使用如前所述的适当的光致抗蚀剂蚀刻掩膜时,基于氟的干法蚀刻可以蚀刻SiN,基本上不蚀刻AlN,并且可以产生诸如对于侧壁24所述侧壁的侧壁。另外,为了优化由斜场板导致的峰值电场的减小,电极限定层23可以为大约100nm厚或者更厚,诸如,在大约100nm和200nm之间,诸如大约120nm。电极限定层23的优化厚度部分地取决于其中使用器件的电路或者模块内的该器件的操作电压。例如,如果将使用更大的操作电压,则可以有利的是,具有更厚的电极限定层23,诸如在大约200nm和2000nm之间。在一些实施中,电极限定层23由通过等离子体增强化学气相沉积(PECVD)沉积的SiN形成,并且为大约120nm厚。
栅极绝缘体层22、蚀刻停止层21和电极限定层23组合起来可以形成器件接入区域中的适合的钝化层。与最上面的III-N表面相邻的栅极绝缘体层22可以防止或者抑制在最上面的III-N表面处的表面/界面态的形成,或者其可以防止或者抑制表面/界面态在器件操作期间捕获电荷的能力。为了足够地防止或抑制由最上面的III-N表面处的表面/界面态引起的分散,栅极绝缘体层22可能需要为大约2nm厚或者更厚。然而,使栅极绝缘体层22更厚可以减少器件跨导,从而劣化器件性能。
为了防止在相对于蚀刻停止层21的相反侧上的电极限定层23的表面处的电压波动引起实质性的分散,电极限定层23和栅极绝缘体22的组合厚度可以充分大,诸如为大约100nm厚或者更厚。可以要求的基本上抑制分散的这两个层的最小的组合厚度取决于器件的操作电压(即,操作期间的源极和漏极之间的最大电压差)。例如,对于达到大约50V的操作,组合厚度可以为大约120nm或更厚,对于达到大约300V的操作,组合厚度可以为大约800nm或更厚,并且对于达到大约600V的操作,组合厚度可以为大约1800nm或更厚。由于可以期望的是,栅极绝缘体层22的厚度小,诸如大约20nm,因此电极限定层23的厚度可以和两层的最小组合厚度几乎一样大或者大约相同。因为厚的单独层会是难以制作的,因此,可能需要的是,形成额外的层以便于实现在较高操作电压下基本上抑制分散所要求的最小组合层厚度。在图12a和图13中示出了这样的器件,并且在下面进行进一步的描述。
在传统III-N器件中,厚度大于大约30nm的单SiN层,即没有与蚀刻停止层或者电极限定层组合使用的层,已经在很多情况下示出是适合的钝化层。与较薄的单SiN层相比,较厚的单SiN层可以在较高的器件操作电压下获得改进的钝化或者有效的钝化。对于图5的器件,已经示出了当2-50nm的MOCVD生长的SiN层用于栅极绝缘体层22、通过溅射沉积而沉积的1-15nm AlN层用于蚀刻停止层21并且通过PECVD沉积的100-200nm SiN层用于电极限定层23时,可以对于达到大约50V的器件操作实现适合的钝化。还示出的是,增加蚀刻停止层21的厚度可以使得器件经历更大的分散,从而劣化器件性能。例如,器件被制作为A1N蚀刻停止层21的厚度是唯一变化的参数。对于AlN蚀刻停止层21的厚度的增加,这些器件示出了增加的分散。
通过下述方式也可以实现具有斜场板和栅极绝缘体的III-N器件:省略图5中的蚀刻停止层21并且选择用于电极限定层23的材料,使得该材料可以被选择性地蚀刻电极限定层23的材料而基本上没有蚀刻栅极绝缘体层22的材料的蚀刻工艺蚀刻。然而,与该结构相比,图5的结构可以是有利的,这是因为,可能难以找到用于栅极绝缘体层22的这样的材料:该材料用作III-N器件的适合的栅极绝缘体而同时用作用于电极限定层23的材料的蚀刻停止层并且同时与电极限定层23的材料结合地用作适合的钝化层。
在图6-图11中图示了形成图5中的器件的方法。参考图6,至少包括沟道层11和阻挡层12的一系列III-N层形成在衬底10上,导致在沟道层11中形成2DEG 19。可以通过诸如MOCVD、MBE、HVPE或者另外的方法的方法来外延生长III-N层。接下来,如图7中所示,栅极绝缘体层22形成在该一系列III-N层顶部。可以通过诸如MOCVD、PECVD、高温CVD(HTCVD)、溅射、蒸镀或者另外的方法的方法来生长或者沉积栅极绝缘体层22。在一些实施中,通过与III-N层类似或者相同的方法来形成栅极绝缘体层22,并且可以在同一步骤中形成栅极绝缘体层22。例如,III-N层和栅极绝缘体层22全部可以通过MOCVD沉积或者生长。
接下来,参考图8,分别在包含源电极14和漏电极15的区域中移除栅极绝缘体层22,并且通过诸如蒸镀、溅射、PECVD、HTCVD或者另外的方法的方法来形成接触2DEG 19的源电极14和漏电极15。在一些实施中,在形成栅极绝缘体层22之前形成源电极14和漏电极15。
参考图9,然后在栅极绝缘体层22顶上形成蚀刻停止层21,在蚀刻停止层21顶部形成电极限定层23。接下来,如图10中所示,诸如光致抗蚀剂的蚀刻掩膜17被沉积在所示的区域中的电极限定层23顶上,并且使用蚀刻电极限定层23的材料而基本上不蚀刻蚀刻停止层21的材料的技术在未掩膜的区域中蚀刻电极限定层23。该蚀刻在蚀刻区域中导致倾斜的侧壁24。因此,蚀刻可以精确地停止在电极限定层23和蚀刻停止层21的界面处。参考图11,蚀刻掩膜17被移除,并且使用蚀刻蚀刻停止层21的材料而基本上不蚀刻电极限定层23或者栅极绝缘体层22的材料的技术来在栅极区域中蚀刻蚀刻停止层21。蚀刻停止层具有主表面,该主表面是与电极限定层形成界面并且当电极限定层被蚀刻穿过时被暴露的表面。因此,蚀刻可以精确地停止在蚀刻停止层21和栅极绝缘体层22的界面处。最终,形成了包括栅极16和斜场板28的电极29,从而导致了图5中所示的器件。
在图5中所示的器件的一个实施中,III-N层和栅极绝缘体层22都通过MOCVD来生长并且在单一的生长步骤中形成。栅极绝缘体层22包括SiN或者由SiN形成并且为大约22nm厚。蚀刻停止层21包括AlN或者由AlN形成,该AlN通过蒸镀或者溅射沉积,并且蚀刻停止层21为大约5nm厚。电极限定层23包括SiN或者由SiN形成,该SiN通过PECVD沉积,并且电极限定层23为大约120nm厚。图10中所示的蚀刻掩膜17是光致抗蚀剂并且以使侧壁实质上倾斜的方式进行图案化。替代地,蚀刻掩膜可以是双层光致抗蚀剂,其中下面的光致抗蚀剂层相对于上覆的光致抗蚀剂层被底切。使用诸如RIE或者ICP的基于氟的干法蚀刻在栅极区域中移除电极限定层23,该干法蚀刻蚀刻SiN并且基本上不蚀刻AlN并且当使用具有实质上倾斜的侧壁的光致抗蚀剂或者使用双层光致抗蚀剂作为蚀刻掩膜时产生诸如对于图5中侧壁24所述侧壁的侧壁。使用蚀刻AlN并且基本上不蚀刻SiN的基于KOH的湿法蚀刻来在栅极区域中移除蚀刻停止层21。
已经制作了诸如图5中所示的具有单个场板的器件,该器件的动态导通电阻(当以达到40V的源极-漏极偏置将器件从截止状态切换到导通状态时测量)不超过DC导通电阻(RON)的1.2倍。发现对于50mA/mm的饱和电流的平均DC RON为大约11.5ohm-mm,而发现当器件在施加有40V的源极-漏极偏置的同时进行切换时测量的平均动态RON为11.9ohm-mm。在切换应用中使用的半导体晶体管中,分散可以导致器件的动态导通电阻增加。在不具有诸如图5中的器件中的斜场板的器件中,分散可以导致对于器件正在其中使用的应用来说太大的动态导通电阻。图5的器件中的分散可以被保持为足够小,即,分散得到了充分的抑制,使得动态导通电阻对于器件应用来说是可接受的。
在图12a中示出包括栅极绝缘体和两个斜场板的器件的示意图。图12a的器件与图5中所示的器件相同,但是进一步包括了绝缘体层32、第二蚀刻停止层31、第二电极限定层33和包括第二斜场板38的电极39。与图5的器件相比,第二斜场板38的添加可以进一步减小器件操作期间的峰值电场,从而进一步增加器件击穿电压并且减少分散,或者导致在比利用图5的器件可能的电压更高的电压下的足够低的分散。
第二电极限定层33和第二蚀刻停止层31可以分别类似于电极限定层23和蚀刻停止层21。即,第二电极限定层33可以由与第二蚀刻停止层31不同组成或者是不同材料的诸如AlN、SiN或者SiO2的绝缘材料形成。另外,第二电极限定层33可以由这样的材料形成:对于该材料,蚀刻工艺可以蚀刻电极限定层33的材料并且产生诸如对于图5中的侧壁24所述侧壁的侧壁,同时基本上没有蚀刻第二蚀刻停止层31的材料。例如,当第二蚀刻停止层31是AlN时,第二电极限定层33可以为SiN,这是因为,基于氟的干法蚀刻蚀刻SiN,基本上不蚀刻AlN,并且当使用适合的光致抗蚀剂蚀刻掩膜时可以产生诸如对于图5中的侧壁24所述侧壁的侧壁。在一些实施中,第二电极限定层33的厚度处于大约10nm和1000nm之间,诸如大约500nm。在一些实施中,第二电极限定层33由通过等离子体增强化学气相沉积(PECVD)沉积的SiN形成并且大约500nm厚。
第二蚀刻停止层31可以由与下面的绝缘体层32不同且与第二电极限定层33不同组成或者是不同材料的诸如AlN、SiN或者SiO2的绝缘材料形成。第二蚀刻停止层31可以由这样的材料组成,对于该材料,蚀刻工艺可以蚀刻蚀刻停止层31的材料而基本上不蚀刻下面的绝缘体层32或者第二电极限定层33的材料。例如,当下面的绝缘体层32和第二电极限定层33是SiN时,第二蚀刻停止层31可以为AlN,这是因为可以使用基本上不蚀刻SiN的基于KOH的湿法蚀刻来蚀刻AlN。此外,第二蚀刻停止层31可以是薄的,诸如小于大约15nm,诸如大约5nm厚,以便于防止第二蚀刻停止层31的实质性横向蚀刻,该横向刻蚀可以导致第二电极限定层33下面的底切。在一些实施中,第二蚀刻停止层31由通过溅射沉积而沉积的AlN形成并且为大约5nm厚。
形成图12a的器件中的电极39和相邻层的方法与形成图5的器件中的电极29和相邻层的方法类似或者相同。另外,电极39和电极29(为了方便起见,在图5中标出而在图12a中没有标出)可以外部地或者在器件周围电连接,从而第二斜场板38是栅极连接的场板(未示出)。如这里使用的,如果两个或更多接触或者其它元件(item)通过这样的材料连接:该材料充分地导电以确保在该接触或者其它元件中的每一个处的电势始终相同,即大致相同,则该接触或者其它元件被称为被“电连接”。此外,额外的斜场板可以使用与对于电极39和相邻层所述的类似或相同的工艺而添加到该器件,该额外的斜场板也可以是栅极连接的场板。
可以是SiN的绝缘体层32将电极39与电极29分离并且可以当蚀刻第二蚀刻停止层31时保护电极29避免损坏。在一些实施中,不包括绝缘体层32,在该情况下,电极39可以直接连接到有源器件区域内的电极29。
在图12a中所示的器件的一个实施中,III-N层和栅极绝缘体层22都通过MOCVD来生长并且在单一的生长步骤中形成。栅极绝缘体层22是SiN并且为大约22nm厚。蚀刻停止层21包括AlN或者由AlN形成,该AlN通过蒸镀或者溅射沉积,并且蚀刻停止层21为大约5nm厚。电极限定层23是通过PECVD沉积的SiN,并且为大约120nm厚。图10中所示的蚀刻掩膜17由光致抗蚀剂形成并且被以这样的方式图案化:使得侧壁实质上倾斜,或者使得侧壁具有底切使得可以在下面的电极限定层23中限定具有斜侧壁的沟槽。使用诸如RIE或者ICP的基于氟的干法蚀刻在栅极区域中移除电极限定层23,该干法刻蚀蚀刻SiN而基本上不蚀刻AlN并且当使用适当的光致抗蚀剂蚀刻掩膜时产生诸如对于图5中的侧壁24所述侧壁的侧壁。使用蚀刻AlN而基本上不蚀刻SiN的基于KOH的湿法蚀刻在栅极区域中移除蚀刻停止层21。绝缘体层32是由PECVD沉积的SiN,并且为大约200nm厚。第二蚀刻停止层31是通过蒸镀或者溅射沉积的AlN,并且为大约5nm厚。第二电极限定层33是通过PECVD沉积的SiN,并且为大约500nm厚。使用诸如RIE或者ICP的基于氟的干法蚀刻来蚀刻第二电极限定层33,该干法蚀刻蚀刻SiN而基本上不蚀刻AlN并且当使用适合的光致抗蚀剂蚀刻掩膜时产生诸如对于图5中的侧壁24所述侧壁的侧壁。使用蚀刻AlN而基本上不蚀刻SiN的基于KOH的湿法蚀刻来蚀刻第二蚀刻停止层31。
已经制作了诸如图12a中所示的具有两个斜场板的器件,该器件的动态导通电阻(当以达到200V的源极-漏极偏置将器件从截止状态切换到导通状态时测量)不超过DC导通电阻(RON)的1.2倍。发现对于50mA/mm的饱和电流的平均DC RON为大约11.5ohm-mm,而发现当器件在施加有200V的源极-漏极偏置的同时进行切换时测量的平均动态RON也为大约11.5ohm-mm。在切换应用中使用的半导体晶体管中,分散可以导致器件的动态导通电阻增加。在不具有诸如图12a中的器件中的多个斜场板的器件中,分散可以导致对于器件正在其中使用的应用来说太大的动态导通电阻。图12a的器件中的分散可以保持为足够小,即,分散得到充分的抑制,从而动态导通电阻对于器件应用来说是可接受的。
已经制作了与图12a中所示的器件类似但是具有三个斜场板的器件,该器件的动态导通电阻(当以达到600V的源极-漏极偏置将器件从截止状态切换到导通状态时测量)不超过DC导通电阻(RON)的1.2倍。在图12b中示出了示出对于这些器件的平均RON与漏电压Vd的曲线图。对于这些器件的平均DC RON是大约170毫欧,而发现当以600V的源极-漏极偏置将器件从截止状态切换到导通状态时测量的平均动态RON为大约200毫欧。
已经制作了与图12a中所示的器件类似但是具有四个斜场板的器件,该器件的动态导通电阻(当以达到800V的源极-漏极偏置将器件从截止状态切换到导通状态时测量)不超过DC导通电阻(RON)的1.4倍。在图12c中示出了示出对于这些器件的平均RON与漏电压Vd的曲线图。对于这些器件的平均DC RON是大约1000毫欧,而发现当以800V的源极-漏极偏置将器件从截止状态切换到导通状态时测量的平均动态RON为大约1400毫欧。
在图13中示出了包括栅极绝缘体22和两个斜场板28和38的另一器件。该器件与图12中所示的器件类似,但是不同之处在于两个斜场板28和38在有源器件区域中彼此连接并且可以利用单个金属沉积来形成。例如,包括器件栅极16以及斜场板28和38的电极49可以在单个步骤中沉积。由于可以简化制造工艺并且可以减少栅极电阻,因此这与图12a中的器件相比可以是有利的。
可以如下地形成图13的器件中的电极49和与电极49相邻的层。栅极绝缘体层22、第一蚀刻停止层21、第一电极限定层23、第二蚀刻停止层31和第二电极限定层33都沉积在有源半导体器件层上。然后在层33顶部对诸如光致抗蚀剂的蚀刻掩膜进行图案化,并且使用如前所述的不蚀刻层31的材料并且导致层33中的倾斜侧壁的蚀刻工艺来在层33中蚀刻孔。然后使用蚀刻层31的材料而不蚀刻层33或23的材料的工艺来蚀刻与孔相邻的层31的部分。在蚀刻层33之前或之后移除在层33顶部沉积或图案化的蚀刻掩膜。接下来,在器件上沉积诸如光致抗蚀剂的第二蚀刻掩膜,从而层33和31的暴露表面以及位于区域59外部的层23的暴露部分由蚀刻掩膜材料覆盖,但是区域59的层23的暴露部分没有被蚀刻掩膜材料覆盖。接下来使用如前所述的不蚀刻层21的材料并且导致层23中的倾斜侧壁的蚀刻工艺在层23中蚀刻孔。最终,移除第二蚀刻掩膜,并且使用蚀刻层21的材料而不蚀刻层22或23的材料的工艺蚀刻与层23中的孔相邻的层21的部分。
在图14和图15中示出包括斜场板28的二极管,其中图14是器件的横截面图并且图15是器件的平面图。图15中所示的平面图分别示出阳极和阴极接触61和60的布局。虽然图15中的阳极和阴极接触被示出为圆形形状,但是它们通常可以为任何适合于使用它们的电路的布局的形状。二极管包括III-N沟道和阻挡层11和12,其包含2DEG沟道19并且类似于图5的器件中的III-N层。阳极接触61由单个电极或多个电极形成并且直接接触下面的半导体材料。阴极接触60接触2DEG沟道19并且紧挨着阳极接触61的至少一部分。阴极接触60是欧姆接触,或者展示出实质性的欧姆行为,并且阳极接触61是与下面的III-N层的肖特基接触或者与下面的III-N层形成实质性的肖特基接触。阴极接触60可以为单个阴极接触。如这里使用的,术语“单个阴极接触”指用作阴极的单个金属接触,或者被电连接而使得每个接触处的电势大致相同的用作阴极的多个接触。阳极和阴极接触61和60可以是任意形状,但是该形状理想地被优化为最小化给定正向电流所要求的器件面积。
电介质层62由绝缘体或者电介质形成并且与器件接入区域中最上面的III-N表面相邻。电介质层62能够自己或者与接入区域中的上面的层组合地用作有效表面钝化层。层21是蚀刻停止层,并且层23是电极限定层,并且分别具有与图5的器件中的蚀刻停止层和电极限定层类似或者相同的要求。
图14和图15中的二极管如下地操作。当阳极接触61处的电压小于阴极接触60处的电压,使得阳极接触61和III-N层12之间的肖特基结反向偏置时,二极管处于截止状态并且没有实质性电流在阳极和阴极之间流动。当阳极接触61处的电压大于阴极接触60处的电压时,阳极接触61和III-N层12之间的肖特基结被正向偏置,并且二极管处于导通状态。电子从阴极接触60主要通过2DEG沟道19并且然后通过正向偏置的肖特基结流入阳极接触61中。即,全部正向偏置电流的至少99%从阳极通过肖特基势垒并且通过2DEG沟道流到阴极。少量的泄漏电流可以流过其它路径,诸如沿着器件的表面流动。
图16中的器件与图14中的器件类似,不同之处在于在阳极区域64中,III-N材料完全凹陷穿过III-N阻挡层12并且部分地穿过III-N沟道层11,从而凹陷延伸穿过包含2DEG的区域。在该情况下,阳极接触61形成与阳极接触61直接接触的III-N层中的一些或全部的实质性的肖特基接触。在一些实施中,凹陷仅部分地延伸穿过III-N层12并且没有延伸穿过包含2DEG沟道的区域(未示出)。在反向偏置操作期间,2DEG沟道19的位于阳极接触的部分66正下方的部分可以被耗尽电子,从而减少了器件中的反向泄漏电流,阳极接触的部分66即位于电介质层62正上方并且与电介质层62相邻的阳极的部分。位于阳极接触的部分66正下方的2DEG沟道19的部分是器件接入区域中的2DEG沟道的部分,并且被限制到与阳极区域64相邻的区域,器件接入区域即位于阳极区域64和阴极接触60之间的区域。为了位于阳极接触的部分66正下方的2DEG沟道19的部分在反向偏置操作期间变为被耗尽电子,电介质层62不能太厚。在一些实施中,电介质层62是氮化硅并且厚度小于大约50nm,诸如大约2nm和50nm之间。电介质层62可以被制成足够厚以防止实质性的泄漏电流、即大于大约10微安/毫米的泄漏电流从阳极通过位于阳极接触的部分66正下方的区域中的电介质层62流到阴极。例如,可能必要的是,使电介质层62大于大约2nm以基本上抑制泄漏电流。在一些实施中,电介质层62的厚度被选择为在位于阳极接触的部分66正下方的区域中,器件具有大约-15V或更大的阈值电压(即,负的程度更少或者正的程度更多),诸如大约-15V和-1V之间。位于阳极接触的部分66正下方的区域的阈值电压是使得该区域中的2DEG基本上被耗尽电荷、即具有小于器件中的最大2DEG电荷密度的大约1%的电荷密度的最大电压。在其它实施中,栅极绝缘体层22的厚度被选择为层的每单位面积的电容为大约0.8-40毫法/m2。在一些实施中,电介质层62是SiN并且通过金属有机化学气相沉积(MOCVD)沉积。
如果电介质层62是相对于氮化硅的高K电介质,则电介质层可以更厚。例如,可能能够通过使用高K电介质用于电介质层62来在位于阳极接触的部分66正下方的区域中实现期望的阈值电压,该电介质层62比被设计为获得该区域的相同阈值电压的SiN层更厚。
其它已知的有益于器件性能的特征也可以包括在图5、图12a和图13-图16中的结构中。这些包括但不限于对于栅极和/或接入区域中的III-N层的表面处理,或者在沟道层11和衬底10之间包括诸如具有大于沟道层11的带隙的带隙的III-N层的III-N缓冲层。半导体层不需要是III-N层,而是可以代替地由其它半导体材料形成。场板不需要是斜场板,而是可以代替地是其它类型的场板。这些特征可以单独地或者彼此组合地使用。
Claims (62)
1.一种III-N器件,包括:
III-N材料层;
绝缘体层,所述绝缘体层在所述III-N材料层的表面上;
第一蚀刻停止层,所述第一蚀刻停止层在所述绝缘体层的相对于所述III-N材料层的相反侧上;
第一电极限定层,所述第一电极限定层在所述第一蚀刻停止层的相对于所述绝缘体层的相反侧上;
电极,其中凹陷形成在所述第一电极限定层中并且所述电极形成在所述凹陷中;以及
堆叠,所述堆叠在所述第一电极限定层的相对于所述第一蚀刻停止层的相反侧上,其中所述堆叠包括第二蚀刻停止层和第二电极限定层。
2.根据权利要求1所述的器件,其中所述电极包括场板。
3.根据权利要求2所述的器件,其中所述场板是斜场板。
4.根据权利要求3所述的器件,其中所述第一电极限定层中的所述凹陷的一部分具有成角度的壁,所述成角度的壁的至少一部分与所述第一蚀刻停止层的主表面成非垂直角度,所述成角度的壁限定所述斜场板。
5.根据权利要求4所述的器件,其中所述非垂直角度在5度和85度之间。
6.根据前述权利要求中的任何一项所述的器件,其中所述绝缘体层是钝化层。
7.根据权利要求1-5中的任何一项所述的器件,其中所述绝缘体层由氧化物或者氮化物形成。
8.根据权利要求7所述的器件,其中所述绝缘体层为2-50纳米厚。
9.根据权利要求1-5中的任何一项所述的器件,其中所述绝缘体层具有0.8-40毫法/平方米的每单位面积电容。
10.根据权利要求1-5中的任何一项所述的器件,其中所述第一电极限定层由氧化物或者氮化物形成。
11.根据权利要求10所述的器件,其中所述第一电极限定层为至少100纳米厚。
12.根据权利要求1-5中的任何一项所述的器件,其中所述绝缘体层和所述第一电极限定层的组合厚度足以基本上抑制分散。
13.根据权利要求1-5中的任何一项所述的器件,其中所述第一蚀刻停止层在1和15纳米厚之间。
14.根据权利要求13所述的器件,其中所述第一蚀刻停止层由氮化铝形成。
15.根据权利要求1-5中的任何一项所述的器件,其中所述第一电极限定层和第一蚀刻停止层由不同材料形成。
16.根据权利要求1-5中的任何一项所述的器件,其中所述第一蚀刻停止层和绝缘体层由不同材料形成。
17.根据权利要求1-5中的任何一项所述的器件,其中所述凹陷形成在所述第一蚀刻停止层中。
18.根据权利要求17所述的器件,其中所述凹陷还形成在所述绝缘体层中。
19.根据权利要求18所述的器件,其中所述III-N材料层的第一部分具有第一组成并且所述III-N材料层的第二部分具有第二组成,其中所述第一组成和所述第二组成之间的差异在所述III-N材料层中形成2DEG沟道。
20.根据权利要求19所述的器件,进一步包括阴极,其中所述电极的一部分是阳极,所述阳极形成与所述III-N材料层的实质性肖特基接触,并且所述阴极与所述2DEG沟道电接触。
21.根据权利要求20所述的器件,其中所述凹陷延伸到所述III-N材料层中并且所述电极在所述III-N材料层中的所述凹陷的一部分中。
22.根据权利要求21所述的器件,其中所述凹陷延伸穿过所述2DEG沟道。
23.根据权利要求22所述的器件,其中所述器件的第一区域的阈值大于-15V,其中所述第一区域包括所述器件的在所述阳极区域和所述阴极之间并且与所述阳极区域相邻的部分。
24.根据权利要求22所述的器件,其中所述绝缘体层的厚度足以防止大于10微安/毫米的泄漏电流在器件操作期间通过所述绝缘体层。
25.根据权利要求1-5中的任何一项所述的器件,其中所述III-N材料层的第一部分具有第一组成并且所述III-N材料层的第二部分具有第二组成,其中所述第一组成和所述第二组成之间的差异在所述III-N材料层中形成2DEG沟道。
26.根据权利要求25所述的器件,进一步包括源极和漏极,其中所述电极的一部分是栅极,并且所述源极和所述漏极与所述2DEG沟道电接触。
27.根据权利要求26所述的器件,其中器件阈值电压大于-30V。
28.根据权利要求27所述的器件,其中所述绝缘体层的厚度使得所述器件阈值电压大于-30V。
29.根据权利要求27所述的器件,其中所述绝缘体层的厚度足以防止大于100微安的泄漏电流在器件操作期间通过所述绝缘体层。
30.根据权利要求1-5中的任何一项所述的器件,其中所述凹陷还形成在所述堆叠中,并且所述电极的一部分在所述堆叠的相对于所述第一电极限定层的相反侧上。
31.根据权利要求1-5中的任何一项所述的器件,进一步包括第二绝缘体层,所述第二绝缘体层在所述第一电极限定层和所述第二蚀刻停止层之间。
32.根据权利要求31所述的器件,进一步包括第二电极,其中第二凹陷形成在所述第二电极限定层中和所述第二蚀刻停止层中,并且所述第二电极形成在所述第二凹陷中。
33.根据权利要求32所述的器件,其中所述第二电极电连接到所述第一电极。
34.根据权利要求32所述的器件,进一步包括多个堆叠,其中凹陷形成在每个堆叠中,并且电极形成在每个凹陷中。
35.根据权利要求1-5中的任何一项所述的器件,其中所述器件是FET,并且当以800V或更小的源极-漏极偏置将所述器件从截止状态切换到导通状态时测量的动态导通电阻等于或者小于DC导通电阻的1.4倍。
36.根据权利要求1-5中的任何一项所述的器件,其中所述电极是栅电极并且所述器件进一步包括源极和漏极。
37.根据权利要求1-5中的任何一项所述的器件,其中所述电极是阳极电极,并且所述器件进一步包括阴极。
38.根据权利要求1-5中的任何一项所述的器件,其中所述器件是增强模式器件。
39.根据权利要求1-5中的任何一项所述的器件,其中所述器件是耗尽模式器件。
40.根据权利要求4或5所述的器件,其中所述器件是FET,所述FET进一步包括漏极,所述电极覆在所述成角度的壁的至少一部分上,并且所述电极没有覆在所述第一电极限定层的在所述成角度的壁的所述部分与所述漏极之间的部分上。
41.一种形成器件的方法,包括:
将绝缘体层施加在III-N材料层的表面上;
在施加所述绝缘体层之后,将第一蚀刻停止层施加在所述绝缘体层上;
在施加所述第一蚀刻停止层之后,将第一电极限定层施加在所述第一蚀刻停止层上;
蚀刻所述第一电极限定层以形成凹陷,其中通过与所述第一蚀刻停止层的表面不垂直的壁至少部分地限定所述凹陷,其中蚀刻步骤使用下述蚀刻剂,所述蚀刻剂具有选择性从而以比蚀刻所述第一蚀刻停止层更快的速率蚀刻所述第一电极限定层;
将导电材料沉积在所述凹陷中和所述第一电极限定层的暴露部分上;以及
将堆叠形成在所述第一电极限定层的相对于所述第一蚀刻停止层的相反侧上,其中所述堆叠包括第二蚀刻停止层和第二电极限定层。
42.根据权利要求41所述的方法,进一步包括蚀刻所述第一蚀刻停止层以将所述第一电极限定层中的所述凹陷延伸到所述绝缘体层。
43.根据权利要求42所述的方法,其中蚀刻所述第一蚀刻停止层包括湿法蚀刻。
44.根据权利要求42或者43所述的方法,其中用于蚀刻所述第一蚀刻停止层的蚀刻工艺基本上不蚀刻所述第一电极限定层或者所述绝缘体层。
45.根据权利要求44所述的方法,其中与蚀刻所述绝缘体层相比,所述蚀刻工艺以10:1或更高的选择性蚀刻所述第一蚀刻停止层。
46.根据权利要求41-43中的任何一项所述的方法,其中蚀刻所述第一电极限定层包括干法蚀刻。
47.根据权利要求46所述的方法,其中蚀刻所述第一电极限定层包括施加基于氟的干法蚀刻。
48.根据权利要求41-43中的任何一项所述的方法,其中蚀刻所述第一电极限定层导致所述第一电极限定层具有成角度的壁,所述成角度的壁的至少一部分与所述第一蚀刻停止层的主表面成非垂直角度。
49.根据权利要求48所述的方法,其中所述非垂直角度在5度和85度之间。
50.根据权利要求41-43中的任何一项所述的方法,其中用于蚀刻所述第一电极限定层的蚀刻工艺基本上不蚀刻所述第一蚀刻停止层。
51.根据权利要求50所述的方法,其中与蚀刻所述第一蚀刻停止层相比,所述蚀刻工艺以10:1或更高的选择性蚀刻所述第一电极限定层。
52.根据权利要求41-43中的任何一项所述的方法,其中,先于形成所述凹陷而形成所述堆叠,所述凹陷还形成在所述堆叠中,并且所述电极的一部分在所述堆叠的相对于所述第一电极限定层的相反侧上。
53.根据权利要求41-43中的任何一项所述的方法,进一步包括:将第二绝缘体层形成在所述第一电极限定层和所述第二蚀刻停止层之间。
54.根据权利要求53所述的方法,进一步包括:将第二凹陷形成在所述第二电极限定层中和所述第二蚀刻停止层中,并且将第二电极形成在所述第二凹陷中。
55.根据权利要求54所述的方法,其中所述第二电极电连接到所述第一电极。
56.根据权利要求54所述的方法,进一步包括形成多个堆叠,其中凹陷形成在每个堆叠中,并且电极形成在每个凹陷中。
57.一种形成III-N器件的方法,包括:
将绝缘体层形成在III-N材料层的表面上;
将第一蚀刻停止层形成在所述绝缘体层的相对于所述III-N材料层的相反侧上;
将第一电极限定层形成在所述第一蚀刻停止层的相对于所述绝缘体层的相反侧上,所述第一电极限定层包括形成在所述第一电极限定层中的凹陷;
将导电材料沉积在所述凹陷中;以及
将堆叠形成在所述第一电极限定层的相对于所述第一蚀刻停止层的相反侧上,其中所述堆叠包括第二蚀刻停止层和第二电极限定层。
58.根据权利要求57所述的方法,其中,先于形成所述凹陷而形成所述堆叠,所述凹陷还形成在所述堆叠中,并且所述电极的一部分在所述堆叠的相对于所述第一电极限定层的相反侧上。
59.根据权利要求57所述的方法,其中,先于形成所述堆叠而在所述凹陷中沉积所述导电材料,所述方法进一步包括:将第二绝缘体层形成在所述第一电极限定层和所述第二蚀刻停止层之间。
60.根据权利要求59所述的方法,进一步包括:将第二凹陷形成在所述第二电极限定层中和所述第二蚀刻停止层中,并且将第二电极形成在所述第二凹陷中。
61.根据权利要求60所述的方法,其中所述第二电极电连接到所述第一电极。
62.根据权利要求60所述的方法,进一步包括形成多个堆叠,其中凹陷形成在每个堆叠中,并且电极形成在每个凹陷中。
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US8692294B2 (en) | 2014-04-08 |
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US9831315B2 (en) | 2017-11-28 |
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US9373699B2 (en) | 2016-06-21 |
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