US9257513B1 - Semiconductor component and method - Google Patents
Semiconductor component and method Download PDFInfo
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- US9257513B1 US9257513B1 US14/452,162 US201414452162A US9257513B1 US 9257513 B1 US9257513 B1 US 9257513B1 US 201414452162 A US201414452162 A US 201414452162A US 9257513 B1 US9257513 B1 US 9257513B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 127
- 238000000034 method Methods 0.000 title claims abstract description 54
- 239000000463 material Substances 0.000 claims abstract description 67
- 238000004519 manufacturing process Methods 0.000 claims abstract description 41
- 239000003989 dielectric material Substances 0.000 claims abstract description 22
- 238000002161 passivation Methods 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims description 13
- 230000006911 nucleation Effects 0.000 claims description 11
- 238000010899 nucleation Methods 0.000 claims description 11
- 230000000873 masking effect Effects 0.000 description 37
- 229910002601 GaN Inorganic materials 0.000 description 15
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 239000004020 conductor Substances 0.000 description 8
- 150000001875 compounds Chemical class 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 5
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 238000004943 liquid phase epitaxy Methods 0.000 description 4
- 238000001465 metallisation Methods 0.000 description 4
- 238000001451 molecular beam epitaxy Methods 0.000 description 4
- 239000003870 refractory metal Substances 0.000 description 4
- 238000000663 remote plasma-enhanced chemical vapour deposition Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000002248 hydride vapour-phase epitaxy Methods 0.000 description 3
- -1 AlNx Inorganic materials 0.000 description 2
- AJGDITRVXRPLBY-UHFFFAOYSA-N aluminum indium Chemical compound [Al].[In] AJGDITRVXRPLBY-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000977 initiatory effect Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000000927 vapour-phase epitaxy Methods 0.000 description 2
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- 229910016909 AlxOy Inorganic materials 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- NWAIGJYBQQYSPW-UHFFFAOYSA-N azanylidyneindigane Chemical compound [In]#N NWAIGJYBQQYSPW-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
- H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/746—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts for AIII-BV integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/408—Electrodes ; Multistep manufacturing processes therefor with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
- H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
Definitions
- the present invention relates, in general, to electronics and, more particularly, to semiconductor structures thereof, and methods of forming semiconductor devices.
- III-N materials gallium nitride (GaN)/aluminum gallium nitride (AlGaN) materials include high reverse leakage currents and low reverse breakdown voltages.
- semiconductor manufacturers have used a dielectric layer at the anode of the device to reduce the reverse leakage current.
- FIG. 1 is a cross-sectional view of a semiconductor component during manufacture in accordance with an embodiment of the present invention
- FIG. 2 is a cross-sectional view of the semiconductor component of FIG. 1 at a later stage of manufacture
- FIG. 3 is a cross-sectional view of the semiconductor component of FIG. 2 at a later stage of manufacture
- FIG. 4 is a cross-sectional view of the semiconductor component of FIG. 3 at a later stage of manufacture
- FIG. 5 is a cross-sectional view of the semiconductor component of FIG. 4 at a later stage of manufacture
- FIG. 6 is a cross-sectional view of the semiconductor component of FIG. 5 at a later stage of manufacture
- FIG. 7 is a cross-sectional view of the semiconductor component of FIG. 6 at a later stage of manufacture
- FIG. 8 is a cross-sectional view of the semiconductor component of FIG. 7 at a later stage of manufacture
- FIG. 9 is an expanded of a portion of the semiconductor component of FIG. 8 ;
- FIG. 10 is a cross-sectional view of a semiconductor component during manufacture in accordance with another embodiment of the present invention.
- FIG. 11 is a cross-sectional view of the semiconductor component of FIG. 10 at a later stage of manufacture
- FIG. 12 is a cross-sectional view of a semiconductor component during manufacture in accordance with another embodiment of the present invention.
- FIG. 13 is a cross-sectional view of the semiconductor component of FIG. 12 at a later stage of manufacture
- FIG. 14 is a cross-sectional view of a semiconductor component during manufacture in accordance with another embodiment of the present invention.
- FIG. 15 is a cross-sectional view of the semiconductor component of FIG. 14 at a later stage of manufacture
- FIG. 16 is a cross-sectional view of a semiconductor component during manufacture in accordance with another embodiment of the present invention.
- FIG. 17 is a cross-sectional view of the semiconductor component of FIG. 16 at a later stage of manufacture
- FIG. 18 is a cross-sectional view of a semiconductor component of FIG. 3 at a later stage of manufacture and in accordance with another embodiment of the present invention.
- FIG. 19 is a cross-sectional view of the semiconductor component of FIG. 18 at a later stage of manufacture
- FIG. 20 is a cross-sectional view of the semiconductor component of FIG. 19 at a later stage of manufacture
- FIG. 21 is a cross-sectional view of the semiconductor component of FIG. 20 at a later stage of manufacture
- FIG. 22 is a cross-sectional view of the semiconductor component of FIG. 21 at a later stage of manufacture
- FIG. 23 is a cross-sectional view of a semiconductor component during manufacture in accordance with another embodiment of the present invention.
- FIG. 24 is a cross-sectional view of a semiconductor component during manufacture in accordance with another embodiment of the present invention.
- FIG. 25 is a cross-sectional view of a semiconductor component during manufacture in accordance with another embodiment of the present invention.
- FIG. 26 is a cross-sectional view of a semiconductor component during manufacture in accordance with another embodiment of the present invention.
- current carrying electrode means an element of a device that carries current through the device such as a source or a drain of an MOS transistor or an emitter or a collector of a bipolar transistor or a cathode or anode of a diode
- a control electrode means an element of the device that controls current flow through the device such as a gate of an MOS transistor or a base of a bipolar transistor.
- the devices are explained herein as certain n-channel or p-channel devices, or certain n-type or p-type doped regions, a person of ordinary skill in the art will appreciate that complementary devices are also possible in accordance with embodiments of the present invention.
- the words during, while, and when as used herein are not exact terms that mean an action takes place instantly upon an initiating action but that there may be some small but reasonable delay, such as a propagation delay, between the reaction that is initiated by the initial action.
- the use of the words approximately, about, or substantially means that a value of an element has a parameter that is expected to be very close to a stated value or position.
- the present invention provides a semiconductor component and a method for manufacturing the semiconductor component wherein the semiconductor component comprises at least one stepped contact in contact with a semiconductor material.
- the semiconductor material may be comprised of a compound semiconductor material formed on a silicon substrate.
- the semiconductor material may be configured such that a nucleation layer is formed on a silicon substrate, a buffer layer is formed on the nucleation layer, a channel layer is formed on the buffer layer, and a strained layer is formed on the channel layer.
- a passivation layer is formed on the semiconductor material and portions of the passivation layer are removed to form openings in the passivation layer that expose portions of the semiconductor material.
- a layer of dielectric material is formed on the passivation layer and on the portions of the semiconductor material exposed by the openings formed in the passivation layer. Openings are formed in the layer of dielectric material that re-expose the previously exposed portions of the semiconductor material, where a first opening is configured to have a sidewall that is configured as a portion of a field plate, wherein the portion of the field plate faces a second opening.
- a metallization system is formed in the first and second openings, wherein the metallization system forms first and second electrodes from the first and second openings, respectively.
- the method includes forming the single sidewall of the opening from which a contact is formed to have a step shape, wherein the opening is referred to as a single-sidewall step shaped opening or a single-sidewall stepped opening and the contact formed from this structure is referred to as a single-sided stepped contact.
- the method includes forming the first cavity portion with at least first and second sidewalls.
- the first opening has opposing sidewalls that are configured as steps and the second opening is configured as a T-shaped opening.
- a contact having step shaped opposing sidewalls is formed from the first opening and a contact having a T-shape is formed from the other opening. Because two sidewalls of the opening from which a contact is formed are stepped or step shaped, the opening is referred to as a double-sidewall step shaped opening or a double-sidewall stepped opening and the contact formed from this structure is referred to as a double-sided stepped contact.
- the first opening has opposing sidewalls that are configured as steps and the second opening has opposing sidewalls where the sidewall of the opposing sidewalls facing the first opening is configured to have steps. Because two sidewalls of the first opening from which a contact is formed are stepped or step shaped, the first opening is referred to as a double-sidewall step shaped opening or a double-sidewall stepped opening and the contact formed from this structure is referred to as a double-sided stepped contact. A contact having step shaped opposing sidewalls is formed from the first opening and a contact having a stepped sidewall is formed from the other opening.
- the second opening is referred to as a single-sidewall step shaped opening or a single-sidewall stepped opening and the contact formed from this structure is referred to as a single-sided stepped contact.
- the first opening has opposing sidewalls wherein one of the opposing sidewalls is configured to have a step shape and the other opposing sidewall is configured to have sloped shape
- the second opening is configured as a T-shaped opening.
- the sidewall in the first opening that has the sloped shape faces the T-shaped opening.
- a contact having a step shaped sidewall and a sloped sidewall is formed from the first opening and a contact having a T-shape is formed from the second opening.
- the sloped sidewall may be referred to as an angled sidewall, a slanted sidewall, or a beveled sidewall.
- the opening is referred to as a stepped-sloped opening or a stepped-angled opening or a stepped-beveled opening or a stepped-slanted opening and the contact formed from this structure is referred to as a stepped-sloped contact or a stepped-angled contact, or a stepped-beveled contact or a stepped-slanted contact.
- the second opening has a T-shape, the contact formed from this structure is referred to as a T-shaped contact.
- the first opening has opposing sidewalls wherein one of the sidewalls is configured to have a step shape and the other sidewall is configured to have a sloped shape
- the second opening has opposing sidewalls where the sidewall of the opposing sidewalls facing the first opening is configured to have steps.
- a stepped-sloped contact is formed from the first opening and a beveled sidewall is formed from the first opening and a single-sided stepped contact is formed from the second opening.
- the first opening has opposing sidewalls wherein the opposing sidewalls of the first opening are configured to be sloped and the second opening is configured as a T-shaped opening.
- the first opening having the having the sloped sidewalls is referred to as a double-sided sloped opening, or a double-sided angled opening, or a double-sided beveled opening, or a double-sided slanted opening.
- a contact is formed from the double-sided sloped opening is referred to as a double-sided sloped contact, or a double-sided angled contact, or a double-sided beveled contact, or a double-sided slanted contact.
- a T-shaped contact is formed from the second opening.
- the method includes forming the first sidewall of the first cavity portion to have a first step having a first step distance and forming the second cavity portion to have at least first and second sidewalls, the first sidewall of the second cavity portion having a second step that has a second step distance, the first step distance greater than the second step distance.
- the method includes forming a third cavity portion having at least first and second sidewalls, the first sidewall of the third cavity portion having a third step that has a third step distance, the second step distance greater than the third step distance.
- the method includes providing a semiconductor material comprising a semiconductor substrate, a nucleation layer on the semiconductor substrate; a buffer region over the nucleation layer; a channel layer over the buffer region; and a strained layer over the channel layer.
- the method includes forming a buffer region that includes one or more layers of a III-N material configured to be a buffer region.
- a method for manufacturing a semiconductor component comprises: providing a semiconductor material, wherein the semiconductor material comprises a plurality of layers including a strained layer having a surface; forming a first layer of dielectric material on the strained layer; exposing first and second portions of the strained layer; forming first and second cavities in the exposed portions of the first and second portions of the strained layer; forming a second layer of dielectric material over the first layer of dielectric material and in the first and second cavities; forming a first contact cavity in the second layer of dielectric material and a second contact cavity in the second layer of dielectric material, the first contact cavity exposing the first portion of the strained layer and the second contact cavity exposing the second portion; and forming a first contact in the first contact cavity and a second contact in the second contact cavity, the first contact extending towards the second contact and serving as a field plate.
- a first contact cavity having a plurality of asymmetric steps and a cavity having a symmetric step are formed in the a layer of dielectric material.
- a first contact cavity having a plurality of asymmetric steps is formed in the layer of dielectric material by forming a first portion of the first contact cavity having a first lateral dimension; forming a second portion of the first contact cavity having a second lateral dimension, the second portion vertically adjacent the first portion and the first lateral dimension greater than the second lateral dimension; and forming a third portion of the first contact cavity having a third lateral dimension, the third portion vertically adjacent the second portion and the second lateral dimension greater than the third lateral dimension.
- a contact cavity having a plurality of asymmetric steps and a cavity having a T-shape are formed in the layer of dielectric material.
- a first contact cavity having first and second opposing sidewalls is formed, the first opposing sidewall having a sloped shape.
- a first contact cavity having first and second opposing sidewalls is formed, the first opposing sidewall having a sloped shape and the second opposing sidewall having a sloped shape.
- a first contact cavity having first and second opposing sidewalls is formed wherein the first opposing sidewall has a sloped shape and the second opposing sidewall has a stepped shape.
- a first contact cavity having first and second opposing sidewalls is formed wherein the first opposing sidewall has a stepped shape and the second opposing sidewall has a stepped shape.
- a first contact cavity having first and second opposing sidewalls is formed, the first opposing sidewall having a sloped shape and the second opposing sidewall having a sloped shape and wherein a second contact cavity having first and second opposing sidewalls is formed, the first opposing sidewall having a stepped shape.
- a first contact cavity having first and second opposing sidewalls is formed, the first opposing sidewall having a sloped shape and the second opposing sidewall having a sloped shape and wherein a second contact cavity having a T-shape is formed.
- a first contact cavity having first and second opposing sidewalls is formed, the first opposing sidewall having a step shape and the second opposing sidewall having a stepped shape and wherein a second contact cavity having first and second opposing sidewalls is formed, the first opposing sidewall having a stepped shape.
- a semiconductor component comprises: a compound semiconductor material having a surface; a dielectric layer over the compound semiconductor material; a first contact extending through the dielectric layer and contacting a first portion of the compound semiconductor material; and a second contact having first and second portions, the first portion extending vertically through the dielectric layer and contacting a first portion of the compound semiconductor material and the second portion extending horizontally toward the first contact.
- the semiconductor component includes a first contact having a T-shape.
- the semiconductor component includes a first contact having a T-shape and a second semiconductor contact having first and second sidewalls, the first sidewall having a stepped configuration and the second sidewall having a sloped configuration.
- the semiconductor component includes a first contact having a T-shape and a second semiconductor contact having first and second sidewalls, the first sidewall having a sloped configuration and the second sidewall having a sloped configuration.
- the semiconductor component includes a first contact having first and second sidewalls, the first sidewall having a stepped configuration.
- FIG. 1 is a cross-sectional view of a portion of a semiconductor component 10 such as, for example, a Light Emitting Diode (LED), a power switching device, a regulator, a protection circuit, a driver circuit, etc. during manufacture in accordance with an embodiment of the present invention.
- a semiconductor substrate 12 having opposing surfaces 14 and 16 .
- Surface 14 may be referred to as a front or top surface and surface 16 may be referred to as a bottom or back surface.
- Semiconductor substrate 12 may be of p-type conductivity, n-type conductivity, or an intrinsic semiconductor material.
- semiconductor substrate 12 is silicon doped with an impurity material of p-type conductivity and has a resistivity ranging from about 1 ⁇ 10 ⁇ 3 Ohm-centimeters ( ⁇ -cm) to about 100 ⁇ -cm.
- suitable materials for substrate 12 include carbon doped silicon, compound semiconductor materials such as, for example, gallium nitride, gallium arsenide, indium phosphide, Group III-V semiconductor materials, Group II-VI semiconductor materials, or the like.
- a nucleation layer 22 having a thickness ranging from about 0.001 ⁇ m to about 1.0 ⁇ m is formed on substrate 12 .
- nucleation layer 22 is aluminum nitride.
- Other suitable materials for nucleation layer 22 include silicon and aluminum nitride, aluminum gallium nitride, silicon carbide, or the like.
- Nucleation layer 22 can be formed using Molecular Beam Epitaxy (MBE), Physical Vapor Deposition (PVD), or chemical vapor deposition techniques such as, for example, a Metalorganic Chemical Vapor Deposition (MOCVD) technique, a Plasma-enhanced Chemical Vapor Deposition (PECVD) technique, a Low Pressure Chemical Vapor Deposition (LPCVD) technique, or the like.
- MBE Molecular Beam Epitaxy
- PVD Physical Vapor Deposition
- chemical vapor deposition techniques such as, for example, a Metalorganic Chemical Vapor Deposition (MOCVD) technique, a Plasma-enhanced
- a buffer layer 24 having a thickness ranging from about 0.1 ⁇ m to about 100 ⁇ m is formed on nucleation layer 22 at a temperature ranging from about 150 degrees Celsius (° C.) to about 1,500° C.
- Suitable materials for buffer layer 24 include Group III-N materials such as, for example, aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), aluminum indium gallium nitride (AlInGaN), indium gallium nitride (InGaN), or the like.
- Buffer layer 24 may be formed using MBE, PECVD, MOCVD, Metal Organic Vapor Phase Epitaxy (MOVPE), Remote Plasma Enhanced Chemical Vapor Deposition (RP-CVD), hydride vapor phase epitaxy (HVPE), liquid phase Epitaxy (LPE), Chloride Vapor Phase Epitaxy (Cl-VPE), or the like. It should be noted that buffer layer 24 may be comprised of a plurality of layers such as for example a plurality of AlN layers, a plurality of GaN layers, or alternating stacked MN and GaN layers. Buffer layer 24 may be of p-type, n-type, or it may be an intrinsic semiconductor material.
- a channel layer 26 having a thickness ranging from about 0.01 ⁇ m to about 10 ⁇ m is formed on buffer layer 24 using one or more techniques selected from the group of techniques comprising MBE, PECVD, MOCVD, MOVPE, RP-CVD, HVPE, LPE, Cl-VPE, or the like.
- channel layer 26 is a GaN layer having a thickness ranging from about 0.1 ⁇ m to about 0.5 ⁇ m.
- Buffer layer 24 may be comprised of an aluminum gallium nitride (AlGaN) superlattice, an aluminum gallium nitride/gallium nitride (AlGaN/GaN) superlattice, an aluminum nitride/gallium nitride (AlN/GaN) superlattice, or the like.
- AlGaN aluminum gallium nitride
- AlGaN/GaN aluminum gallium nitride/gallium nitride
- AlN/GaN aluminum nitride/gallium nitride
- a layer of dielectric material 30 having a thickness ranging from about 1 nm to about 1 ⁇ m is formed on strained layer 28 .
- Dielectric layer 30 may be referred to as a field oxide or a field oxide layer. Suitable materials for dielectric layer 30 include oxide, nitride, silicon dioxide, silicon nitride, or the like.
- a layer of photoresist is patterned over dielectric layer 30 to form a masking structure 32 having masking elements 34 and openings 36 that expose portions of dielectric layer 30 .
- the portions of dielectric layer 30 unprotected by masking elements 34 are removed using a wet etchant that selectively etches the material of dielectric layer 30 .
- the wet etchant is a buffered oxide etchant. The etch leaves portions 30 A, 30 B, and 30 C of dielectric layer 30 and exposes portions of strained layer 28 . Cavities 38 A and 38 B are formed through the exposed portions of strained layer 28 .
- Masking elements 34 are removed and a layer of dielectric material 40 having a thickness ranging from about 1 ⁇ m to about 1,000 ⁇ m is formed on the exposed portions of strained layer 28 , i.e., in cavities 38 A and 38 B, and on portions 30 A, 30 B, and 30 C of dielectric layer 30 .
- a layer of photoresist is patterned over dielectric layer 40 to form a masking structure 42 having masking elements 44 and openings 46 that expose portions of dielectric layer 40 .
- the portions of dielectric layer 40 unprotected by masking elements 44 are removed using a wet etch that selectively etches the material of dielectric layer 40 to form cavity portion 50 A having sidewalls 50 A 1 and 50 A 2 and to form a cavity portion 52 A having sidewalls 52 A 1 and 52 A 2 .
- the wet etch is a timed etch and the etchant for the wet etch is a buffered oxide etchant when the material of dielectric layer 40 is oxide.
- Masking elements 44 are removed and a layer of photoresist is patterned over dielectric layer 40 to form a masking structure 54 having masking elements 56 and openings 58 that expose portions of dielectric layer 40 within cavity portions 50 A and 52 A.
- the portions of dielectric layer 40 unprotected by masking elements 56 are removed using a wet etch that selectively etches the material of dielectric layer 40 to form cavity portions 50 B and 52 B, wherein cavity portion 50 B has sidewalls 50 B 1 and 50 B 2 and cavity portion 52 B has sidewalls 52 B 1 and 52 B 2 .
- the wet etch is a timed etch and the etchant for the wet etch is a buffered oxide etchant when the material of dielectric layer 40 is oxide.
- Masking elements 56 are removed and a layer of photoresist is patterned over dielectric layer 40 to form a masking structure 60 having masking elements 62 and openings 64 that expose a portion 66 of dielectric layer 40 within cavity portions 50 A and 50 B and a portion 68 of dielectric layer 40 within cavity portions 52 A and 52 B.
- the portions of dielectric layer 40 unprotected by masking elements 62 are removed using a wet etch that selectively etches the material of dielectric layer 40 to form cavity portions 50 C and 52 C, wherein cavity portion 50 C has sidewalls 50 C 1 and 50 C 2 and cavity portion 52 C has sidewalls 52 C 1 and 52 C 2 .
- Cavity portion 52 C may be referred to as an extension of cavity portion 52 B.
- the wet etch is a timed etch and the etchant for the wet etch is a buffered oxide etchant when the material of dielectric layer 40 is oxide.
- Masking elements 62 are removed and a layer of photoresist is patterned over dielectric layer 40 to form a masking structure 70 having masking elements 72 and openings 74 that expose a portion 76 of dielectric layer 40 within cavity portions 50 A, 50 B, and 50 C and a portion 78 of dielectric layer 40 within cavity portions 52 A, 52 B, and 52 C.
- the portions of dielectric layer 40 unprotected by masking elements 72 are removed using a wet etch that selectively etches the material of dielectric layer 40 to form cavity portions 50 D and 52 D, wherein cavity portion 50 D has sidewalls 50 D 1 and 50 D 2 and cavity portion 52 D has sidewalls 52 D 1 and 52 D 2 .
- Cavity portion 52 D may be referred to as an extension of one or all of cavity portions 52 A, 52 B, and 52 C.
- the wet etch is a timed etch and the etchant for the wet etch is a buffered oxide etchant when the material of dielectric layer 40 is oxide.
- Masking elements 72 are removed and a layer of photoresist is patterned over dielectric layer 40 to form a masking structure 80 having masking elements 82 and openings 84 that expose a portion 86 of dielectric layer 40 within cavity portions 50 A, 50 B, 50 C, and 50 D and a portion 88 of dielectric layer 40 within cavity portions 52 A, 52 B, 52 C, and 52 D.
- the portions of dielectric layer 40 unprotected by masking elements 82 are removed using a wet etch that selectively etches the material of dielectric layer 40 to form cavity portions 50 E and 52 E and expose portions 90 and 92 , respectively, of strained layer 28 .
- Cavity portion 50 E has sidewalls 50 E 1 and 50 E 2
- cavity portion 52 E has sidewalls 52 E 1 and 52 E 2 .
- the wet etch is a timed etch and the etchant for the wet etch is a buffered oxide etchant when the material of dielectric layer 40 is oxide.
- Masking elements 82 are removed.
- Cavity portions 50 A- 50 E form a stepped cavity 50 or a stepped cavity structure 50 and cavity portions 52 A- 52 E form a T-shaped cavity 52 or a T-shaped cavity structure.
- Stepped cavity structure 50 may be referred to as a stepped cavity and T-shaped cavity structure 52 may be referred to a T-shaped cavity. Because two sidewalls of stepped cavity or opening 50 from which a contact is to be formed are stepped or step shaped, cavity 50 may be referred to as a double-sidewall step shaped opening or a double-sidewall stepped opening.
- cavity portions 50 A- 50 E form a contact opening having a plurality of steps.
- the step formed by cavity portion 50 A is wider than the step formed by cavity portion 50 B; the step formed by cavity portion 50 B is wider than the step formed by cavity portion 50 C; the step formed by cavity portion 50 C is wider than the step formed by cavity portion 50 D; and the step formed by cavity portion 50 D is wider than the step formed by cavity portion 50 E.
- the distance between sidewalls 50 A 1 and 50 A 2 is greater than the distance between sidewalls 50 B 1 and 50 B 2 ; the distance between sidewalls 50 B 1 and 50 B 2 is greater than the distance between sidewalls 50 C 1 and 50 C 2 ; the distance between sidewalls 50 C 1 and 50 C 2 is greater than the distance between sidewalls 50 D 1 and 50 D 2 ; and the distance between sidewalls 50 D 1 and 5 D 2 is greater than the distance between sidewalls 50 E 1 and 50 E 2 .
- the steps formed by cavity portions 50 A- 50 E are asymmetric, wherein a horizontal distance from sidewall 50 B 1 of cavity portion 50 B to sidewall 50 A 1 of cavity portion 50 A, referred to as a step distance or lateral dimension, is less than a horizontal distance from sidewall 50 B 2 of cavity portion 50 B to sidewall 50 A 2 of cavity portion 50 A, referred to as a step distance or lateral dimension.
- a horizontal distance from sidewall 50 C 1 of cavity portion 50 C to sidewall 50 A 1 of cavity portion 50 A referred to as a step distance or lateral dimension
- a horizontal distance from sidewall 50 D 1 of cavity portion 50 D to sidewall 50 A 1 of cavity portion 50 A is less than a horizontal distance from sidewall 50 D 2 of cavity portion 50 D to sidewall 50 A 2 of cavity portion 50 A, referred to as a step distance or lateral dimension.
- a horizontal distance from sidewall 50 E 1 of cavity portion 50 E to sidewall 50 A 1 of cavity portion 50 A is less than a horizontal distance from sidewall 50 E 2 of cavity portion 50 E to sidewall 50 A 2 of cavity portion 50 A, referred to as a step distance or lateral dimension.
- cavity portions 50 A, 50 B, 50 C, 50 D, and 50 E form a stepped cavity having a plurality of asymmetric steps and cavity portions 52 A, 52 B, 52 C, 52 D, and 52 E form a T-shaped cavity, wherein cavity portions 50 A- 50 E of cavity 50 are referred to as having a stepped configuration.
- a contact 94 is formed from stepped cavity 50 and a contact 96 is formed from T-shaped cavity 52 . Because contact 94 is formed from a double-sidewall stepped opening, contact 94 may be referred to double-sided stepped contact. Because contact 96 is formed from a T-shaped cavity or opening, it may be referred to as a T-shaped contact. Contacts 94 and 96 may be formed from metallization systems that include a refractory metal layer formed on dielectric layer 40 and on the exposed portions 90 and 92 of strained layer 28 , one or more barrier metal layers may be formed on the refractory metal layer, and a contact metal may be formed on the one or more barrier metal layers.
- Contact 94 formed in stepped cavity 50 is a step shaped contact and may be referred to as a field plate having a stepped configuration or a step-shaped field plate.
- field plate 94 serves as a cathode of the diode and T-shaped contact 96 serves as an anode of the diode.
- FIG. 9 is an expanded view of the portion of semiconductor component 10 shown in broken circle 95 of FIG. 8 .
- FIG. 10 is a cross-sectional view of a semiconductor component 100 during manufacture in accordance with another embodiment of the present invention.
- semiconductor component 100 is similar to semiconductor component 10 except that T-shaped contact opening 52 is replaced by a stepped contact opening 53 , i.e., a contact opening having stepped or step-shaped sides, wherein the steps of contact opening 53 are on a side of stepped contact opening 53 facing stepped contact opening 50 .
- Stepped contact opening 53 is comprised of cavity portions 53 A, 53 B, 53 C, 53 D, and 53 E formed from dielectric layer 40 .
- Cavity portion 53 A has sidewalls 53 A 1 and 53 A 2
- cavity portion 53 B has sidewalls 53 B 1 and 53 B 2
- cavity portion 53 C has sidewalls 53 C 1 and 53 C 2
- cavity portion 53 D has sidewalls 53 D 1 and 53 D 2
- cavity portion 53 E has sidewalls 53 E 1 and 53 E 2 .
- Techniques for forming stepped contact opening 53 may be similar to those for forming stepped contact opening 50 . Because a single sidewall of the opening from which a contact to be formed is stepped or step shaped, the opening is referred to as a single-sidewall step shaped opening or a single sidewall stepped opening.
- stepped contact 96 A an electrically conductive material is formed in stepped contact openings 50 and 53 to form stepped contacts 94 and 96 A, respectively.
- Techniques for forming stepped contact 96 A may be similar to those for forming stepped contact 94 or T-shaped contact 96 . Because contact 94 is formed from a double-sidewall stepped opening, it may be referred to as a double-sided stepped contact and because contact 96 A is formed from a single-sidewall step shaped opening, it may be referred to as a single sided stepped contact.
- FIGS. 12 and 13 are cross-sectional views of a semiconductor component 120 during manufacture in accordance with another embodiment of the present invention. It should be noted that semiconductor component 120 is similar to semiconductor component 10 except that stepped contact 94 has been replaced by a stepped-sloped contact 94 A, wherein the steps of stepped-sloped contact 94 A that are on a side of stepped-sloped contact 94 A facing T-shaped contact 96 are sloped or have a sloped configuration.
- FIG. 12 illustrates a stepped-sloped contact opening 55 formed in dielectric layer 40 , comprising cavity portions 55 A- 55 E.
- Cavity portion 55 A has sidewalls 55 A 1 and 55 A 2
- cavity portion 55 B has sidewalls 55 B 1 and 55 B 2
- cavity portion 55 C has sidewalls 55 C 1 and 55 C 2
- cavity portion 55 D has sidewalls 55 D 1 and 55 D 2
- cavity portion 55 E has sidewalls 55 E 1 and 55 E 2 .
- Techniques for forming stepped-sloped contact opening 55 may be similar to those for forming stepped contact opening 50 .
- Contact opening 55 is referred to as a stepped beveled contact opening or a stepped sloped contact opening because sidewalls 55 A 1 - 55 E 1 form a stepped sidewall or are in a stepped configuration and sidewalls 55 A 2 - 55 E 2 form a beveled sidewall or in a beveled configuration.
- the beveled configuration may be referred to as an angled configuration or a sloped configuration.
- an electrically conductive material is formed in stepped-sloped contact opening 55 to form a stepped-sloped contact 94 A and an electrically conductive material is formed in contact opening 52 to form a T-shaped contact 96 .
- Techniques for forming the electrically conductive material of stepped-sloped contact 96 A may be similar to those for forming single-sided stepped contact 94 or T-shaped contact 96 . Because contact 94 A is formed from a stepped-sloped opening, it may be referred to as a stepped-sloped contact and because contact 96 is formed from T-shaped contact opening 52 , it may be referred to as a T-shaped contact.
- FIGS. 14 and 15 are cross-sectional views of a semiconductor component 140 during manufacture in accordance with another embodiment of the present invention. It should be noted that semiconductor component 140 is similar to semiconductor component 120 except that T-shaped contact 96 has been replaced by a stepped contact 96 A. The sloped portion of stepped-sloped contact 94 A is on a side of stepped-sloped contact 94 A that faces the stepped portion of stepped contact 96 A.
- FIG. 14 illustrates a stepped-sloped contact opening 55 formed in dielectric layer 40 , comprising cavity portions 55 A- 55 E and a stepped contact opening 53 comprising cavity portions 53 A- 53 E. The formation of stepped-sloped contact opening 55 has been described with reference to FIGS. 12 and 13 and the formation of single-sided stepped contact opening 53 has been described with reference to FIGS. 10 and 11 .
- an electrically conductive material is formed in stepped-sloped contact opening 55 and in single-sided stepped contact opening 53 to form a stepped-sloped contact 94 A and an electrically conductive material is formed in single-sided contact opening 53 to a single-sided stepped contact 96 A.
- FIGS. 16 and 17 are cross-sectional views of a semiconductor component 160 during manufacture in accordance with another embodiment of the present invention. It should be noted that semiconductor component 160 is similar to semiconductor component 140 except that stepped-sloped contact 94 A has been replaced by a double-sided beveled contact 94 B. The stepped portion of stepped contact 96 A contact is on a side that faces the sloped contact 94 B.
- FIG. 16 illustrates a double-sided sloped contact opening 57 formed in dielectric layer 40 , comprising cavity portions 57 A- 57 E and a single-sided stepped contact opening 53 comprising cavity portions 53 A- 53 E.
- Cavity portion 57 A has sidewalls 57 A 1 and 57 A 2
- cavity portion 57 B has sidewalls 57 B 1 and 57 B 2
- cavity portion 57 C has sidewalls 57 C 1 and 57 C 2
- cavity portion 57 D has sidewalls 57 D 1 and 57 D 2
- cavity portion 57 E has sidewalls 57 E 1 and 57 E 2 .
- Single-sided stepped contact opening 53 has been described with reference to FIGS. 10 and 11 .
- Double-sided sloped contact opening 57 may be referred to as a double-sided beveled contact opening or a double-sided angled contact opening or a double-sided slanted contact opening because sidewalls 57 A 1 - 57 C 1 form a beveled or sloped sidewall and sidewalls 57 A 2 - 57 C 2 form a beveled or sloped sidewall.
- contact double-sided opening 57 may be referred to as being in a sloped configuration or an angled configuration, or a beveled configuration, or a slanged configuration.
- an electrically conductive material is formed in double-sided sloped contact opening 57 and in single-sided stepped contact opening 53 to form a double-sided sloped contact 94 B and an electrically conductive material is formed in single-sided stepped contact opening 53 to form a single-sided stepped contact 96 .
- FIG. 18 is a cross-sectional view of a semiconductor component 170 in accordance with another embodiment of the present invention, wherein the description of FIG. 18 continues from the description of FIG. 3 .
- reference character 10 in FIGS. 1-3 has been replaced by reference character 170 beginning with FIG. 18 .
- the portions of dielectric layer 40 unprotected by masking elements 56 are removed using a wet etch that selectively etches the material of dielectric layer 40 to form cavity portions 50 B and 52 B, wherein cavity portion 50 B has sidewalls 50 B 1 and 50 B 2 and cavity portion 52 B has sidewalls 52 B 1 and 52 B 2 .
- the width of cavity portion 52 B is less than that of cavity portion 52 A.
- the wet etch is a timed etch and the etchant for the wet etch is a buffered oxide etchant when the material of dielectric layer 40 is oxide.
- Cavity portions 50 A-Masking elements 56 are removed and a layer of photoresist is patterned over dielectric layer 40 to form a masking structure 60 having masking elements 62 and openings 64 that expose a portion 66 of dielectric layer 40 within cavity portions 50 A and 50 B and a portion 68 of dielectric layer 40 within cavity portions 52 A and 52 B.
- the portions of dielectric layer 40 unprotected by masking elements 62 are removed using a wet etch that selectively etches the material of dielectric layer 40 to form cavity portions 50 C and 52 C, where cavity portion 50 C has sidewalls 50 C 1 and 50 C 2 and cavity portion 52 C has sidewalls 52 C 1 and 52 C 2 .
- the wet etch is a timed etch and the etchant for the wet etch is a buffered oxide etchant when the material of dielectric layer 40 is oxide.
- Masking elements 62 are removed and a layer of photoresist is patterned over dielectric layer 40 to form a masking structure 70 having masking elements 72 and openings 74 that expose a portion 76 of dielectric layer 40 within cavity portions 50 A, 50 B, and 50 C and a portion 78 of dielectric layer 40 within cavity portions 52 A, 52 B, and 52 C.
- the portions of dielectric layer 40 unprotected by masking elements 72 are removed using a wet etch that selectively etches the material of dielectric layer 40 to form cavity portions 50 D and 52 D, wherein cavity portion 50 D has sidewalls 50 D 1 and 50 D 2 and cavity portion 52 D has sidewalls 52 D 1 and 52 D 2 .
- the wet etch is a timed etch and the etchant for the wet etch is a buffered oxide etchant when the material of dielectric layer 40 is oxide.
- Masking elements 72 are removed and a layer of photoresist is patterned over dielectric layer 40 to form a masking structure 80 having masking elements 82 and openings 84 that expose a portion 86 of dielectric layer 40 within cavity portions 50 A, 50 B, 50 C, and 50 D and a portion 88 of dielectric layer 40 within cavity portions 52 A, 52 B, 52 C, and 52 D.
- the portions of dielectric layer 40 unprotected by masking elements 82 are removed using a wet etch that selectively etches the material of dielectric layer 40 to form cavity portions 50 E and 52 E that expose portions 90 and 92 , respectively, of strained layer 28 .
- Cavity portion 50 E has sidewalls 50 E 1 and 50 E 2
- cavity portion 52 E has sidewalls 52 E 1 and 52 E 2 .
- the wet etch is a timed etch and the etchant for the wet etch is a buffered oxide etchant when the material of dielectric layer 40 is oxide.
- Masking elements 82 are removed.
- Cavity portions 50 A- 50 E form a double-sided stepped cavity 50 or a double-sided stepped cavity structure 50 and cavity portions 52 A- 52 E form a T-shaped cavity 52 or a T-shaped cavity structure. It should be noted that the formation of stepped cavity 50 and T-shaped cavity 52 have been described with reference to FIGS. 1-7 . The reference characters for these cavities has been retained in FIGS. 18-21 because the structures differ regarding their centering or position formation relative to cavity 38 B, i.e., cavity 52 of FIG. 21 is positioned such that edges 52 E 1 and 52 E 2 are spaced apart from the sidewalls of cavity 38 B.
- a contact 94 is formed from double-sided stepped cavity 50 and a contact 96 is formed from T-shaped cavity 52 .
- Contacts 94 and 96 may be formed from metallization systems that include a refractory metal layer formed on dielectric layer 40 and on exposed portions 90 and 92 of strained layer 28 , one or more barrier metal layers may be formed on the refractory metal layer, and a contact metal may be formed on the one or more barrier metal layers.
- Contact 94 formed in double-sided stepped cavity 50 is a step shaped contact and may be referred to as a field plate having a stepped configuration or a step-shaped configuration and contact 96 may be referred to as a T-shaped contact.
- field plate 94 serves as a cathode of the diode and T-shaped contact 96 serves as an anode of the diode.
- FIG. 23 is a cross-sectional view of a semiconductor component 180 during manufacture in accordance with another embodiment of the present invention.
- semiconductor component 180 is similar to semiconductor component 170 except that T-shaped contact 96 has been replaced by a single-sided stepped contact 96 A, wherein the steps of single-sided contact 96 A are on a side of stepped contact 96 that faces stepped contact 94 .
- a single-sided stepped contact opening 53 comprised of cavity portions 53 A- 53 E is formed from dielectric layer 40 .
- Techniques for forming single-sided stepped contact opening 53 may be similar to those for forming stepped contact opening 50 .
- techniques for forming single-sided stepped contact 96 A may be similar to those for forming double-sided stepped contact 94 or T-shaped contact 96 .
- FIG. 24 is a cross-sectional view of a semiconductor component 190 during manufacture in accordance with another embodiment of the present invention.
- semiconductor component 190 is similar to semiconductor component 170 except that double-sided stepped contact 94 has been replaced by a stepped-sloped contact 94 A, wherein the sidewall of single-sided stepped contact 94 that comprises steps is on a side of single-sided stepped contact 94 facing T-shaped contact 96 have been replaced with a sidewall having a sloped configuration.
- a stepped-sloped contact opening 55 comprised of cavity portions 55 A- 55 E is formed from dielectric layer 40 .
- the sloped sidewall of the contact opening or cavity may be referred to as an angled sidewall, or a beveled sidewall or a slanted sidewall and opening 55 may be referred to as a stepped-sloped opening or stepped-sloped contact opening.
- Techniques for forming stepped-sloped contact opening 55 may be similar to those for forming double-sided stepped contact opening 50 .
- techniques for forming stepped-sloped contact 94 A may be similar to those for forming double-sided stepped contact 94 or T-shaped contact 96 .
- FIG. 25 is a cross-sectional view of a semiconductor component 200 during manufacture in accordance with another embodiment of the present invention. It should be noted that semiconductor component 200 is similar to semiconductor components 170 and 180 in that semiconductor component 200 includes stepped-sloped contact 94 A and single-sided stepped contact 96 A, wherein the sloped portion of stepped-sloped contact 94 A is on the side of stepped-sloped contact 94 A facing the single-sided stepped portion of contact 96 A.
- FIG. 26 is a cross-sectional view of a semiconductor component 220 during manufacture in accordance with an embodiment of the present invention.
- semiconductor component 220 is similar to semiconductor component 10 except that double-sided stepped contact 94 has been replaced by a double-sided sloped contact 94 B.
- a double-sided stepped contact opening 57 comprised of cavity portions 57 A- 57 E is formed from dielectric layer 40 .
- Techniques for forming double-sided stepped contact opening 57 may be similar to those for forming double-sided stepped contact opening 50 .
- techniques for forming double-sided sloped contact 94 B may be similar to those for forming double-sided stepped contact 94 or T-shaped contact 96 .
- the semiconductor component includes a contact that serves as field plate wherein the contact has sidewalls with different shapes. In one shape the sidewalls are stepped, in another shape the sidewalls are sloped, and in another shape one sidewall is stepped and the other sidewall is sloped.
- the semiconductor includes a second contact that may be T-shaped, or has a sidewall that is stepped or a sidewall that is sloped.
- the field plate may serve as either an anode, a cathode, or both and anode and a cathode, wherein the field plates reduce electric fields at the contact edges and expand the depletion regions which increases the breakdown voltages.
- the field plates can be stepped, slanted, slope, and floated over the drift region between the anode and cathode. The number of steps, the ratios of the field plate lengths, slanting or sloping angles, and lengths can be optimized for dynamic Rdson and breakdown voltage.
- Field plates in accordance with embodiments of the present invention can be used with combinations of anode dielectric, recessed Schottky anode, and recessed cathode ohmic contacts.
- the field plates can be used with combination and stacks of different anode dielectric layers, passivation materials, and field dielectric materials such as nitrides and oxides (SiNx, AlNx, SiOx, SiONx, AlxOy) and high or low dielectric constant materials.
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US10651304B2 (en) | 2016-05-30 | 2020-05-12 | Stmicroelectronics S.R.L. | High-power and high-frequency heterostructure field-effect transistor |
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US20160043185A1 (en) | 2016-02-11 |
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