JP5918945B2 - トランジスタの作製方法 - Google Patents
トランジスタの作製方法 Download PDFInfo
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- JP5918945B2 JP5918945B2 JP2011184381A JP2011184381A JP5918945B2 JP 5918945 B2 JP5918945 B2 JP 5918945B2 JP 2011184381 A JP2011184381 A JP 2011184381A JP 2011184381 A JP2011184381 A JP 2011184381A JP 5918945 B2 JP5918945 B2 JP 5918945B2
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- film
- oxide semiconductor
- substrate
- insulating film
- transistor
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Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- Thin Film Transistor (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
- Electrodes Of Semiconductors (AREA)
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Description
本実施の形態では、膜中および膜と膜との界面への水素の混入が少ないトップゲートトップコンタクト構造の酸化物半導体を用いたトランジスタの作製方法について説明する。
本実施の形態では、膜中および膜と膜との界面への水素の混入が少ないボトムゲートトップコンタクト構造の酸化物半導体を用いたトランジスタの作製方法について説明する。
本実施の形態では、実施の形態2とは異なる膜中および膜と膜との界面への水素の混入が少ないボトムゲートトップコンタクト構造の酸化物半導体を用いたトランジスタの作製方法について図10を用いて説明する。なお、図6のフローおよび図7までは、実施の形態2と同様の作製工程である。
本実施の形態では、酸素放出する絶縁膜の形成方法について図2および図18を用いて説明する。
本実施の形態では、フォトマスク数およびフォトリソグラフィ工程数を削減した液晶表示装置の画素に用いるトランジスタの作製方法について、図11乃至図13を用いて説明する。
本実施の形態では、高速動作が可能で、かつ信頼性の高いトランジスタの一例を図17を用いて示す。
実施の形態1乃至実施の形態6において、トランジスタの半導体膜に用いることのできる酸化物半導体膜の成膜方法の一形態を説明する。
実施の形態1乃至実施の形態6において、トランジスタの半導体膜に用いることのできる酸化物半導体膜の成膜方法の一形態を、図14を用いて説明する。
実施の形態1乃至実施の形態6で例示したトランジスタを用いた表示装置の一形態を図15に示す。
本発明の一態様である半導体装置は、さまざまな電子機器(遊技機も含む)に適用することができる。電子機器としては、例えば、テレビジョン装置(テレビまたはテレビジョン受信機ともいう)、コンピュータ用などのモニタ、デジタルカメラ、デジタルビデオカメラなどのカメラ、デジタルフォトフレーム、携帯電話機(携帯電話、携帯電話装置ともいう)、携帯型ゲーム機、携帯情報端末、音響再生装置、パチンコ機などの大型ゲーム機などが挙げられる。上記実施の形態で説明した半導体装置を具備する電子機器の例について説明する。
10b 成膜室
10c 成膜室
11 基板供給室
12a ロードロック室
12b ロードロック室
13 搬送室
14 カセットポート
15 基板処理室
100 基板
102 下地絶縁膜
106 酸化物半導体膜
108a ソース電極
108b ドレイン電極
112 ゲート絶縁膜
114 ゲート電極
128 酸化物導電膜
150 トランジスタ
200 基板
202 下地絶縁膜
206 酸化物半導体膜
208a ソース電極
208b ドレイン電極
212 ゲート絶縁膜
213 導電膜
214 ゲート電極
216 層間絶縁膜
222 導電膜
224 バックゲート電極
226 保護絶縁膜
228 酸化物導電膜
250 トランジスタ
252 トランジスタ
308 導電膜
308a ソース電極
308b ドレイン電極
328 酸化物導電膜
350 トランジスタ
400 基板
402 下地絶縁膜
406 酸化物半導体膜
408 導電膜
408a ソース電極
408b ドレイン電極
412 ゲート絶縁膜
414 ゲート電極
415 コンタクトホール
416 層間絶縁膜
431 画素電極
440 配線
442 画素
444 配線
445 電極
446 液晶素子
447 容量配線
448 容量素子
450 トランジスタ
500 基板
502 下地絶縁膜
506 酸化物半導体膜
508a ソース電極
508b ドレイン電極
512 ゲート絶縁膜
514 ゲート電極
516 層間絶縁膜
518 配線
524 バックゲート電極
526 保護絶縁膜
528 酸化物導電膜
550 トランジスタ
600 基板
602 下地絶縁膜
606 酸化物半導体膜
606a 結晶性酸化物半導体膜
606b 結晶性酸化物半導体膜
701 基板
702 画素部
703 信号線駆動回路
704 走査線駆動回路
705 シール材
706 基板
708 液晶層
713 液晶素子
715 電極
716 配線
718a FPC
718b FPC
719 異方性導電膜
720 入力端子
730 電極
731 電極
732 絶縁膜
733 絶縁膜
750 トランジスタ
801 本体
802 筐体
803 表示部
804 キーボード
811 本体
812 スタイラス
813 表示部
814 操作ボタン
815 外部インターフェイス
820 電子書籍
821 筐体
822 筐体
823 表示部
824 表示部
825 軸部
826 電源
827 操作キー
828 スピーカー
830 筐体
831 筐体
832 表示パネル
833 スピーカー
834 マイクロフォン
835 操作キー
836 ポインティングデバイス
837 カメラ用レンズ
838 外部接続端子
840 太陽電池セル
841 外部メモリスロット
851 本体
860 テレビジョン装置
861 筐体
863 表示部
865 スタンド
Claims (4)
- 基板上に絶縁膜を形成し、
イオンインプランテーション法により、前記絶縁膜に酸素を注入し、
酸素が注入された前記絶縁膜上に、酸化物半導体膜を形成し、
前記酸化物半導体膜を形成後、熱処理を行うことを特徴とするトランジスタの作製方法。 - 基板上に絶縁膜を形成し、
イオンインプランテーション法により、前記絶縁膜に酸素を注入し、
酸素が注入された前記絶縁膜上に、酸化物半導体膜を形成し、
前記酸化物半導体膜を形成後、熱処理を行うことで、前記絶縁膜から前記酸化物半導体膜に酸素を供給することを特徴とするトランジスタの作製方法。 - 基板上に絶縁膜を形成し、
イオンインプランテーション法により、前記絶縁膜に酸素を注入し、
酸素が注入された前記絶縁膜上に、酸化物半導体膜を形成し、
前記酸化物半導体膜を形成後、熱処理を行うことで、前記絶縁膜から前記酸化物半導体膜に酸素を供給すると同時に、前記酸化物半導体膜中の水素を低減することを特徴とするトランジスタの作製方法。 - 請求項1乃至請求項3のいずれか一において、
前記熱処理後に、前記酸化物半導体膜上にゲート絶縁膜を介してゲート電極を形成することを特徴とするトランジスタの作製方法。
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US20120058598A1 (en) | 2012-03-08 |
TW201630189A (zh) | 2016-08-16 |
US20160111280A1 (en) | 2016-04-21 |
TWI542002B (zh) | 2016-07-11 |
WO2012029596A1 (en) | 2012-03-08 |
US10269563B2 (en) | 2019-04-23 |
JP2019216276A (ja) | 2019-12-19 |
JP2012146946A (ja) | 2012-08-02 |
TW201743454A (zh) | 2017-12-16 |
TW201227964A (en) | 2012-07-01 |
JP2016106422A (ja) | 2016-06-16 |
TWI604615B (zh) | 2017-11-01 |
US9355844B2 (en) | 2016-05-31 |
JP2018032874A (ja) | 2018-03-01 |
US20140242749A1 (en) | 2014-08-28 |
US8728860B2 (en) | 2014-05-20 |
TWI661563B (zh) | 2019-06-01 |
JP6590891B2 (ja) | 2019-10-16 |
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