JP2012009838A - 半導体装置及びその作製方法 - Google Patents
半導体装置及びその作製方法 Download PDFInfo
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- JP2012009838A JP2012009838A JP2011110530A JP2011110530A JP2012009838A JP 2012009838 A JP2012009838 A JP 2012009838A JP 2011110530 A JP2011110530 A JP 2011110530A JP 2011110530 A JP2011110530 A JP 2011110530A JP 2012009838 A JP2012009838 A JP 2012009838A
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- oxide semiconductor
- insulating layer
- semiconductor layer
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- electrode
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Abstract
【解決手段】チャネルを形成する脱水化または脱水素化された酸化物半導体層に接する絶縁層に、シリコン過酸化ラジカルを含む絶縁層を用いる。絶縁層から酸素が放出されることにより、酸化物半導体層中の酸素欠損及び絶縁層と酸化物半導体層の界面準位を低減することができ、電気的特性の変動が小さく、信頼性の高い半導体装置を作製することができる。
【選択図】図1
Description
本実施の形態では、半導体装置及び半導体装置の作製方法の一形態を、図1乃至図7を用いて説明する。
実施の形態1で例示したトランジスタを用いて表示機能を有する半導体装置(表示装置ともいう)を作製することができる。また、トランジスタを含む駆動回路の一部または全体を、画素部と同じ基板上に一体形成し、システムオンパネルを形成することができる。
本発明の一態様である半導体装置は、さまざまな電子機器(遊技機も含む)に適用することができる。電子機器としては、例えば、テレビジョン装置(テレビまたはテレビジョン受信機ともいう)、コンピュータ用などのモニタ、デジタルカメラ、デジタルビデオカメラなどのカメラ、デジタルフォトフレーム、携帯電話機(携帯電話、携帯電話装置ともいう)、携帯型ゲーム機、携帯情報端末、音響再生装置、パチンコ機などの大型ゲーム機などが挙げられる。上記実施の形態で説明した半導体装置を具備する電子機器の例について説明する。
・膜種:酸化シリコン
・成膜法:RFスパッタリング法
・ターゲット:シリコンターゲット
・成膜ガス:Ar(10sccm)、O2(40sccm)
・電力:3kW(13.56MHz)
・圧力:0.6Pa
・T−S間距離:60mm
・成膜時基板温度:室温
・厚さ:300nm
・膜種:酸化シリコン
・成膜法:RFスパッタリング法
・ターゲット:シリコンターゲット
・成膜ガス:Ar(10sccm)、O2(40sccm)
・電力:3kW(13.56MHz)
・圧力:0.6Pa
・T−S間距離:60mm
・成膜時基板温度:100℃
・厚さ:300nm
・膜種:酸化シリコン
・成膜法:RFスパッタリング法
・ターゲット:シリコンターゲット
・成膜ガス:Ar(40sccm)、O2(10sccm)
・電力:3kW(13.56MHz)
・圧力:0.6Pa
・T−S間距離:60mm
・成膜時基板温度:100℃
・厚さ:300nm
・膜種:酸化シリコン
・成膜法:RFスパッタリング法
・ターゲット:石英ターゲット
・成膜ガス:Ar(40sccm)、O2(10sccm)
・電力:1.5kW(13.56MHz)
・圧力:0.4Pa
・T−S間距離:60mm
・成膜時基板温度:100℃
・厚さ:300nm
・膜種:酸化窒化シリコン
・成膜法:プラズマCVD法
・原料ガス:SiH4(25sccm)、N2O(1000sccm)
・電力:35W(13.56MHz)
・圧力:133.3Pa
・電極−基板間距離:20mm
・成膜時基板温度:200℃
・厚さ:300nm
・成膜法:RFスパッタリング法
・ターゲット:石英ターゲット
・成膜ガス:Ar(25sccm)、O2(25sccm)
・電力:1.5kW(13.56MHz)
・圧力:0.4Pa
・T−S間距離:60mm
・基板温度:100℃
・成膜法:DCスパッタリング法
・ターゲット:In−Ga−Zn−O(In2O3:Ga2O3:ZnO=1:1:2[mol数比])ターゲット
・成膜ガス:Ar(30sccm)、O2(15sccm)
・電力:0.5kW(DC)
・圧力:0.4Pa
・T−S間距離:60mm
・基板温度:200℃
102 絶縁層
106 酸化物半導体層
108a ソース電極
108b ドレイン電極
112 ゲート絶縁層
114 ゲート電極
122a ソース領域
122b ドレイン領域
124 保護絶縁層
126 チャネル領域
151 トランジスタ
152 トランジスタ
153 トランジスタ
154 トランジスタ
155 トランジスタ
201 第1の基板
202 画素部
203 信号線駆動回路
204 走査線駆動回路
205 シール材
206 第2の基板
208 液晶層
210 トランジスタ
211 トランジスタ
213 液晶素子
215 接続端子電極
216 端子電極
218 FPC
218a FPC
218b FPC
219 異方性導電層
221 絶縁層
230 第1の電極層
231 第2の電極層
232 絶縁層
233 絶縁層
235 スペーサ
240 隔壁
241 電界発光層
243 発光素子
244 充填材
252 キャビティ
253 球形粒子
254 充填材
255a 黒色領域
255b 白色領域
301 本体
302 筐体
303 表示部
304 キーボード
311 本体
312 スタイラス
313 表示部
314 操作ボタン
315 外部インターフェイス
320 電子書籍
321 筐体
322 筐体
323 表示部
324 表示部
325 軸部
326 電源
327 操作キー
328 スピーカー
330 筐体
331 筐体
332 表示パネル
333 スピーカー
334 マイクロフォン
335 操作キー
336 ポインティングデバイス
337 カメラ用レンズ
338 外部接続端子
340 太陽電池セル
341 外部メモリスロット
351 本体
353 接眼部
354 操作スイッチ
355 表示部(B)
356 バッテリー
357 表示部(A)
360 テレビジョン装置
361 筐体
363 表示部
365 スタンド
500 基板
502 絶縁層
506 酸化物半導体層
508a ソース電極
508b ドレイン電極
512 ゲート絶縁層
514 ゲート電極
516 保護絶縁層
518a ソース配線
518b ドレイン配線
522 細線
524 太線
532 細線
534 太線
Claims (19)
- 基板と、
ゲート電極と、
脱水化または脱水素化された酸化物半導体層と、
前記酸化物半導体層と電気的に接続されるソース電極及びドレイン電極と、
前記ゲート電極と前記酸化物半導体層の間に形成されるゲート絶縁層と、
前記酸化物半導体層を介して、前記ゲート絶縁層と対向し、且つ前記酸化物半導体層に接するシリコン過酸化ラジカルを含む絶縁層と、を有する半導体装置。 - 請求項1において、
前記酸化物半導体層は、水素濃度が1×1018cm−3未満であることを特徴とする半導体装置。 - 請求項1または請求項2において、
前記酸化物半導体層は、キャリア濃度が1×1014cm−3未満であることを特徴とする半導体装置。 - 請求項1乃至請求項3のいずれか一において、
前記ゲート電極は、前記ゲート絶縁層を介して、前記酸化物半導体層に重なり、
該酸化物半導体層が前記ゲート電極よりも前記基板側であることを特徴とする半導体装置。 - 請求項4において、
前記ソース電極及び前記ドレイン電極は、前記ゲート絶縁層及び前記酸化物半導体層の間に形成されることを特徴とする半導体装置。 - 請求項4において、
前記ソース電極及び前記ドレイン電極は、前記絶縁層及び前記酸化物半導体層の間に形成されることを特徴とする半導体装置。 - 請求項1乃至請求項3のいずれか一において、
前記酸化物半導体層は、前記ゲート絶縁層を介して、前記ゲート電極に重なり、
該ゲート電極が前記酸化物半導体層よりも前記基板側であることを特徴とする半導体装置。 - 請求項7において、
前記ソース電極及び前記ドレイン電極は、前記酸化物半導体層及び前記絶縁層の間に形成されることを特徴とする半導体装置。 - 請求項7において、
前記ソース電極及び前記ドレイン電極は、前記ゲート絶縁層及び前記酸化物半導体層の間に形成されることを特徴とする半導体装置。 - 請求項1乃至請求項9のいずれか一において、
前記ゲート絶縁層は、シリコン過酸化ラジカルを含む絶縁層であることを特徴とする半導体装置。 - 請求項1乃至請求項10のいずれか一において、
前記酸化物半導体層は、チャネル領域と、前記酸化物半導体層を低抵抗化したソース領域及びドレイン領域と、を有し、
前記ソース領域及び前記ドレイン領域は、それぞれ前記ソース電極及び前記ドレイン電極と接続することを特徴とする半導体装置。 - 請求項1乃至請求項11のいずれか一において、
前記シリコン過酸化ラジカルを含む絶縁層は、電子スピン共鳴法で得られたスペクトルにおいて、g値が2.0016及び2.0078に信号を有することを特徴とする半導体装置。 - 基板上にシリコン過酸化ラジカルを含む下地絶縁層を形成し、
前記下地絶縁層上に酸化物半導体層を形成し、
前記酸化物半導体層上に接してソース電極及びドレイン電極を離間して形成し、
前記ソース電極及び前記ドレイン電極上に前記酸化物半導体層と一部が接するゲート絶縁層を形成し、
前記酸化物半導体層上に前記ゲート絶縁層を介してゲート電極を形成し、
前記酸化物半導体層の形成時の基板加熱、または前記酸化物半導体層の形成後に熱処理を行うことを特徴とする半導体装置の作製方法。 - 基板上にシリコン過酸化ラジカルを含む下地絶縁層を形成し、
前記下地絶縁層上に接してソース電極及びドレイン電極を離間して形成し、
前記ソース電極及び前記ドレイン電極上に前記下地絶縁層と一部が接する酸化物半導体層を形成し、
前記酸化物半導体層上にゲート絶縁層を形成し、
前記酸化物半導体層上に前記ゲート絶縁層を介してゲート電極を形成し、
前記酸化物半導体層の形成時の基板加熱、または前記酸化物半導体層の形成後に熱処理を行うことを特徴とする半導体装置の作製方法。 - 基板上に下地絶縁層を形成し、
前記下地絶縁層上にゲート電極を形成し、
前記ゲート電極上にゲート絶縁層を形成し、
前記ゲート絶縁層上に酸化物半導体層を形成し、
前記酸化物半導体層上に接してソース電極及びドレイン電極を離間して形成し、
前記ソース電極及び前記ドレイン電極上に前記酸化物半導体層と一部が接するシリコン過酸化ラジカルを含む保護絶縁層を形成し、
前記酸化物半導体層の形成時の基板加熱、または前記酸化物半導体層の形成後に熱処理を行うことを特徴とする半導体装置の作製方法。 - 基板上に下地絶縁層を形成し、
前記下地絶縁層上にゲート電極を形成し、
前記ゲート電極上にゲート絶縁層を形成し、
前記ゲート絶縁層上に接してソース電極及びドレイン電極を離間して形成し、
前記ソース電極及び前記ドレイン電極上に前記ゲート絶縁層と一部が接する酸化物半導体層を形成し、
前記酸化物半導体層上にシリコン過酸化ラジカルを含む保護絶縁層を形成し、
前記酸化物半導体層の形成時の基板加熱、または前記酸化物半導体層の形成後に熱処理を行うことを特徴とする半導体装置の作製方法。 - 請求項13乃至請求項16のいずれか一において、
前記下地絶縁層は、スパッタリング法により、シリコンターゲットもしくは石英ターゲットを用い、酸素または、酸素とアルゴンの混合ガスを用いて形成することを特徴とする半導体装置の作製方法。 - 請求項13乃至請求項16のいずれか一において、
前記ゲート絶縁層は、スパッタリング法により、シリコンターゲットもしくは石英ターゲットを用い、酸素または、酸素とアルゴンの混合ガスを用いて形成することを特徴とする半導体装置の作製方法。 - 請求項15または請求項16において、
前記保護絶縁層は、スパッタリング法により、シリコンターゲットもしくは石英ターゲットを用い、酸素または、酸素とアルゴンの混合ガスを用いて形成することを特徴とする半導体装置の作製方法。
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US8476719B2 (en) | 2013-07-02 |
US20110284846A1 (en) | 2011-11-24 |
JP5723216B2 (ja) | 2015-05-27 |
JP5235243B2 (ja) | 2013-07-10 |
TWI535010B (zh) | 2016-05-21 |
CN102906882A (zh) | 2013-01-30 |
WO2011145632A1 (en) | 2011-11-24 |
KR20130077839A (ko) | 2013-07-09 |
TW201203552A (en) | 2012-01-16 |
CN102906882B (zh) | 2015-11-25 |
JP2012256938A (ja) | 2012-12-27 |
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