1251877 九、發明說明： 【發明所屬之技術領域】 t本發㈣、詩—種半導體元件及其製作方法，特別是 才曰種具有氮化漸層結構之半導體元件及其製作方法。 【先前技術】 在半導體元件的製程中，常需要定義出許多微細的圖 二’而這些圖案主要的形成方式，乃藉由姓刻（Etch㈣技 術，將微影（Mlcro-iithography)後所產生的光阻圖案忠實地 轉印至光阻下的材質上，以造成複雜的架構。因此，钱刻 技術在半導體製程中佔有極為重要的地位。 蝕J技術可以刀為換钮亥j (wet etchi呢）及乾姓刻（的 吋咖呢）兩類。其中，乾蝕刻的最大優點即是非等向性蝕 刻（anisotropic etching)，可以獲得較為精確的钱刻輪廓。 然而’乾钱刻不但設備昂貴，由於必須使用真空系統，豆 維修費用也相對高昂。因此，一般取代的方法是濕似卜、 濕蝕刻通常對不同材料會具有相當高的選擇比 (selectivity)。除了結晶方向可能影響蝕刻速率外，由於 =學反應並不會對特定方向有任何的偏好，所以賴刻本 :上：是-種等向性蝕刻(iso加pic etching)。等向性蝕刻 意味著，濕蝕刻不但會在縱向進行蝕刻，而且也會有橫向 的蝕刻效果。橫向蝕刻會導致所謂『底切』（祕㈣、的 現象發生，而無法精確地將圖形轉移。 因此，對於經常使用多層結構之薄膜電晶體而言，餘 6 1251877 刻輪廓的控制往往會是非常困難的，若不同層所使用材料 的餘刻速率差異過多，很容易造成嚴重的底切。例如，一 般閉極是使用AINd/AmiN(純/㈣氮化物）之雙層结構 ，因AINd/AINdN中AINd與A1MN之蝕刻速率相差^7曰=之 f ’於是底切的現象更是無法避免。所以，有人則使用°阻 障層於餘刻速率差異大的多層之間，以作為緩衝，如以 鳥作㈣極’相Τι/α1/μ_作為祕與沒極。 ^疋，攻種方&需要加裝額外革巴材或裝置，i無法一次 艇’也容易於各層間產生材料介面問題’而導致瑕疵。 【發明内容】 半導ί於:之問題’本發明之主要目的為提供-種 成且：： 作方法，於製程中變化氮氣的流量，形 =層：構之半導體元件，以改善底切的現象。 因此’基於上述構想，本發明提供—種半導體 W純與位於基板上之氮化㈣結構的閉極。 本發明也提供一種半導， 極，位於基板上；半導有、：基板；間 位於半導體層上，且源極：立於閘極上’源極與没極， 道，位於源極與沒極之間Γ 化漸層結構；及通 極，供:種半導體元件，包含有··基板;間 立於基板上’且間極為氮】 於閉極上，·源極與汲極’位於 ，+>體層，位 為氮化漸層結構；及通 、版卩上，且源極與汲極 通逷，位於源極與汲極之間。 7 1251877 驟包二種半導一製作方法，其步 數，形成气化： 斤進式6周整虱氣流量或其他製程參 數升7成虱化漸層結構之閘極於基板上。 本發明也提供一種丰逡雕_ 含··提供基板；形成門朽二牛之衣作方法，其步驟包 上，·漸進式調整板^形成半導體層於閉極 結構之源極盥汲 麥數’形成氮化漸層 極之間。及極於+導體層上·及形成通道於源極與沒 本發明更提供一種半導體 含:提供基板;漸進式調整氮氣流量:形 化=半導體層於閘極上;漸進式。氮 及形成通道於 了解"的 【實施方式】 用於供r導體元件及其製作方法，主要可應 膜期間：二製程？於閑極、及源極與汲極之成 化漸層社構之m正μ"里變化或其他製程參數，形成氮 件。：；構=·、及源極與汲極，並陸續構成半導體元 的濃度分佈tr謂氮化漸層結構是指含氮量成漸進式 第一實施例 8 1251877 首先，請參考第1圖與第2圖，說明本發明之包含氮 化漸層結構之閘極之半導體元件及其主要Μ，其製作過 程如下： 提供基板（步驟100 ):在此為提供-玻璃基板10。 形成氮化漸層結構之閘極（步驟110):沉積A1Nd (紹鈥σ * )之金屬層於玻璃基板1G上，其工作氣體為氮 氣（流量維持在 100 SCCM(standard cubic centimeters per minute ))，並同時通入氮氣，且隨著沉積過程的進行， 將氮氣流量自〇逐漸調整至刚SCCM，以形成氮化漸層結 構之閘極11，其膜厚約為2520埃（A )。 其中，由於氮氣的流量是漸進式的調整，因此閘極U 2氮化濃度與深度的關係並非保持一定；亦即，不同於先 别技術之多層結構之閘極，本發明之半導體元件之閘極Η 係於垂直方向上具有不同的氮化程度，且其氮化程度是由 接近基板朝运離基板方向遞增。 第二實施例 再請參考第3圖與第4圖，說明本發明之包含氮化漸1251877 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly to a semiconductor device having a nitrided gradation structure and a method of fabricating the same. [Prior Art] In the manufacturing process of semiconductor devices, it is often necessary to define a plurality of fine patterns 2' and the main formation modes of these patterns are generated by the method of lasting (Etch (4) technology, after lithography (Mlcro-iithography) The photoresist pattern is faithfully transferred to the material under the photoresist to create a complicated structure. Therefore, the money engraving technology occupies an extremely important position in the semiconductor process. The etch J technology can be used as a knife (wet etchi) There are two types of dry etching: the most important advantage of dry etching is that it is anisotropic etching, which can obtain a more accurate outline of money. However, 'dry money is not only expensive, Due to the necessity of using a vacuum system, the cost of bean maintenance is relatively high. Therefore, the general method of substitution is wet, wet etching usually has a relatively high selectivity for different materials. In addition to the crystallization rate may affect the etching rate, Since the = learning response does not have any preference for a particular direction, the etched: top: is an isotropic etch (iso plus pic etching). Etching means that wet etching not only etches in the longitudinal direction, but also has a lateral etching effect. Lateral etching causes the phenomenon of so-called "undercutting" (the secret (4), which cannot be accurately transferred. Therefore, In the case of thin-film transistors with a multi-layer structure, the control of the contour of the remaining 6 1251877 is often very difficult. If the difference in the residual rate of the materials used in different layers is too large, it is easy to cause serious undercuts. For example, general closure It is a two-layer structure using AINd/AmiN (pure/(tetra) nitride), because the etch rate of AINd and A1MN in AINd/AINdN is different from that of ^1曰=f', so the undercut phenomenon is even more unavoidable. So, someone Then use the ° barrier layer between the multiple layers with large difference in the residual rate, as a buffer, such as the bird (four) pole 'phase Τ ι / α 1 / μ _ as secret and immersed. ^ 疋, attacker & needs The addition of additional leather materials or devices, i can not be a single boat 'is also easy to create a material interface problem between the layers' resulting in defects. [Summary of the invention] Semi-guided: The problem of the main purpose of the present invention is to provide :: The method of changing the flow rate of nitrogen in the process, forming a layer: a semiconductor component to improve the undercut phenomenon. Therefore, based on the above concept, the present invention provides a semiconductor W pure and nitrided on a substrate. (4) The closed pole of the structure. The invention also provides a semiconducting pole, which is located on the substrate; a semiconducting layer is: a substrate; is located on the semiconductor layer, and the source is: standing on the gate; 'source and immersion, track, Located between the source and the pole, the gradation structure; and the passer, for: a semiconductor component, including a substrate; standing on the substrate 'and extremely nitrogen' on the closed pole, · source and 汲The pole 'is located at the +> body layer, which is located in a nitrided gradation structure; and on the pass, the plate, and the source and the bungee are all around, between the source and the drain. 7 1251877 Two kinds of semi-conducting methods are produced, and the number of steps is formed to form gasification: the enthalpy flow rate of 6 weeks of enthalpy or other process parameters is increased by 70% of the gate of the gradation structure on the substrate. The invention also provides a method for providing a substrate of the 逡 逡 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 'Formed between the nitriding gradient poles. And on the +conductor layer and forming the channel at the source and not. The invention further provides a semiconductor comprising: providing a substrate; progressively adjusting the nitrogen flow rate: morphing = semiconductor layer on the gate; progressive. Nitrogen and forming channels are understood. [Embodiment] For r conductor components and their manufacturing methods, mainly for film period: two processes? In the idle pole, and the source and the bungee, the m positive μ" changes or other process parameters form a nitrogen component. :; = =, and the source and the bungee, and successively constitute the concentration distribution of the semiconductor element tr said that the nitriding structure refers to the nitrogen content into a progressive first embodiment 8 1251877 First, please refer to Figure 1 2 is a view showing a semiconductor device including a gate of a nitrided gradation structure of the present invention and a main structure thereof, which are produced as follows: A substrate is provided (step 100): Here, a glass substrate 10 is provided. Forming a gate of a nitrided gradation structure (step 110): depositing a metal layer of A1Nd (Sho鈥σ*) on the glass substrate 1G, and the working gas is nitrogen (the flow rate is maintained at 100 SCCM (standard cubic centimeters per minute)) At the same time, nitrogen gas was introduced, and as the deposition process progressed, the nitrogen gas flow rate was gradually adjusted from the enthalpy to just SCCM to form a nitriding stepped gate 11 having a film thickness of about 2520 angstroms (A). Wherein, since the flow rate of the nitrogen gas is a gradual adjustment, the relationship between the nitriding concentration of the gate U 2 and the depth is not kept constant; that is, the gate of the semiconductor device of the present invention is different from the gate of the multilayer structure of the prior art. The crucibles have different degrees of nitridation in the vertical direction, and the degree of nitridation is increased from the proximity of the substrate toward the transporting substrate. Second Embodiment Referring again to FIGS. 3 and 4, the present invention includes a nitriding process.
層結構之源極與汲極之半導體元件及其主要流程，其製作 過程如下： I 提供基板（步驟200 ):在此為提供一玻璃基板2〇。 形成閘極（步驟210):於玻璃基板2〇上沉積—金严 形成閘極絕緣層（步驟220 ):於閘極21上以電裝你 9 1251877The source and drain electrodes of the layer structure and the main processes thereof are as follows: I provide a substrate (step 200): here a glass substrate 2 is provided. Forming a gate (step 210): depositing on the glass substrate 2 - forming a gate insulating layer (step 220): on the gate 21 to electrify you 9 1251877
SiNx 強式化學氣相沈積法（PECVD)沉積 以形成閘極絕緣層22。 -丰幵=導體層（步驟230 ):於閑極絕緣層22上沉積 +蜍體層23，以作為薄膜電晶體的電子通道。 η型妾觸層(，驟24。）：於半導體層23上沉積 夕（n Si )，以形成歐姆接觸層24。 形成氮化漸層結構之源極與没極（步驟，）：於歐 姆接觸層24上沉積AINd之全;| # , ' I雜姓―1ΛΛ 屬層’其工作氣體為氬氣（流 、、隹持在100 SCCM )，並同時诵入翁> , srnu、 、、入虱乳（流量維持在100 SCC1V[、㈣儿積輕的進行，將氮氣流量自100 、雨入> U㈣至〇SCCM ’待沉積一定厚度之AINd後，再 並逐漸調至·CCM，以形成作為氮化漸層結構 之源極與汲極25的訊號線，來控制 厚約為2_埃（A)。 ⑽心虎傳遞。且其膜 欧姆源極錢極之間（步驟:钱刻部分 £人姆接觸層24與部分源極與汲極％， 成一薄膜電晶體結構。 / L、，而構 、及極2^1:由t氮氣的流量是漸進式的調整，因此源極與 =Xt與深度的關係並非保持-定，·亦即，不 == 技術之多層結構之源極與汲極，本發明之半導體 極極25係於垂直方向上具有不同的氮化程 向遞增。 ？間刀別在遠離 基板與接近基板方 10 1251877 第三實施例 一一妾著明芩考第5圖與第6圖，顯示本發明所提供之 :二實施例之半導體元件，乃包含前述之 層社 構之間極、及源極與沒極，且其製作流程於下：曰、、口 提供基板（步驟300 ):在此為提供一玻璃基㈣。 :成閑極（步驟31〇):沉積湖之金屬層於破璃基 士、，其工作氣體為氬氣（流量維持在100SCCM)，並 人虱乳’且隨著沉積過程的進行，將氮氣流量自0 W。逐漸調整至100SCCM，以形成氮化漸層結構之閘極 形成間極絕緣層（步驟32〇 ) ··於閉極31上以電裝择 ^式化學氣相沈積法沉積錢化物，以形成閉極絕緣層日 導體層（步驟33〇 ):於間極絕緣料 - +導體層33,以作為薄膜電晶體的電子通道。 、 :姐姆接觸層（步驟:於半導體層％上沉積 夕（n Si )，以形成歐姆接觸層34。 心成氮化漸層結構之源極與没極（步驟现）：於歐 上沉積·之金屬層，其工作氣體為氬氣：流 里、'、寺在100SCCM)，並同時通入氮氣1〇〇sccm,且隨著 ϊίΓΙ進行，將氮氣流量自觸_逐漸調整至0 rrs〇r積—定厚度之綱後，再通入氮氣並逐漸調 形成作為氮化漸層結構之源極與汲㈣的 詋5虎線，來控制〇/1訊號傳遞。 11 1251877 形成通道於源極與汲極之間（步驟360 ) ·•蝕刻部分 區人姆接觸層34與部分源極與波極35，以形成通道％，而構 成一薄膜電晶體結構。 形成鈍化層（步驟370 ):在整個基板3〇上，覆蓋石夕 I化物作為鈍化層37，以避免水氣的腐蝕。 形成接觸孔（步，驟迦）：於鈍化層π上敍刻出數個 接觸孔38，而露出部分源極與汲極35。 形成晝素電極（步驟，）：最後，覆蓋氧化銦錫 induim-tm-oxKie，ITO )透明金屬於整個鈍化層37上，以形 = = 畫素電極39可透過接觸孔％電性連接至鈍 化層37下方之溥膜電晶體。 m其!7、’由於氮氣的流量是漸進式的調整，因此閘極31 口 响及極35之氮化濃度與深度的_並 . 先前技術之多層結構之間極、和源極與沒， 首卷月之半導體兀件之閘極31和源極與汲極35皆於垂 _ 不同的氮化程度，且閑極31之氮化程度是^ ，近基板朝遠離基板方向遞增，㈣ = 度則是由中間分別往遠離基板與接近基板方向遞2化秋 上述各貫施例中，具有氮化漸 W銘鈥合金及其氮化物，亦可為紹、銅極與 鉻、鈦、或其合金及其氮化物。 1 ' 而且，本發明之具有氮化漸層結構 極之半導體元件中，其上 ]桎或源極與汲 用，氮化程度較低之南的部位可作為保護作 低之其他部位則可作為緩衝作用，而改善 12 1251877 钱刻時之底切現象。 綜而言之，本發明所提供之-法’乃於開極或源極與没極成膜時口及其製作方 成氮化漸層結構，而減少底切的 4職的流量，形 真空室（chamber )内一次忐瞪 而且，此結構可在 料介面問題的產生，另外，4 π免;:衣私間早，也降低材 材，所以不會增加設備成本。 衣，、餘衣置或靶 虽!然本發明之較佳實施例揭露如 以限定本發明，任何熟習相關 ^、…、亚非用 精神和範圍内，當可作此呼之^在不脫離本發明之 專刹仅w 二°午之更動與潤飾，因此本發明之 專利保瘦乾圍須視本說明書所 為準。 甲巧專利靶圍所界定者 【圖式簡單說明】SiNx Strong Chemical Vapor Deposition (PECVD) deposition is performed to form the gate insulating layer 22. - Feng Wei = conductor layer (step 230): a germanium layer 23 is deposited on the idler insulating layer 22 to serve as an electron channel for the thin film transistor. The n-type germanium contact layer (step 24) is deposited on the semiconductor layer 23 (n Si ) to form the ohmic contact layer 24. Forming the source and the immersion of the nitriding layer structure (step): depositing the entire AINd on the ohmic contact layer 24; | # , 'I 姓 ― ΛΛ ΛΛ ' ' 其 其 其 其 其 其 其 其 其 其 其 其 其 其 其 其 其 其 其 其Hold at 100 SCCM), and simultaneously enter Weng >, srnu, ,, and sputum milk (flow is maintained at 100 SCC1V [, (4) light accumulation, nitrogen flow from 100, rain into > U (four) to 〇 SCCM 'After depositing a certain thickness of AINd, it is gradually adjusted to CCM to form a signal line which is the source of the nitrided gradation structure and the drain 25 to control the thickness of about 2 angstroms (A). (10) The heart and the tiger pass. And the membrane ohmic source between the poles (step: money engraved part of the human contact layer 24 and part of the source and the drain pole, into a thin film transistor structure. / L,, and structure, and pole 2^1: The flow rate of nitrogen gas is progressively adjusted, so the relationship between source and =Xt and depth is not constant-fixed, that is, not == source and drain of the multilayer structure of the technology, the present invention The semiconductor pole 25 has different nitriding direction increments in the vertical direction. The knives are away from the substrate and close to the substrate side. 877. The third embodiment shows a semiconductor device according to the second embodiment of the present invention. The semiconductor device of the second embodiment includes the layer between the foregoing layers and the source and the source. a pole, and the manufacturing process is as follows: 曰, 口 provides a substrate (step 300): here is to provide a glass base (four). : into a leisure pole (step 31 〇): depositing a metal layer of the lake in the broken glass, The working gas is argon gas (the flow rate is maintained at 100 SCCM), and the human milk is sucked' and as the deposition process progresses, the nitrogen flow rate is gradually adjusted from 0 W to 100 SCCM to form a gate structure of a nitrided gradation structure. Inter-electrode insulating layer (step 32〇) · Depositing the bulk material on the closed pole 31 by electro-optic chemical vapor deposition to form a closed-pole insulating layer daily conductor layer (step 33〇): inter-electrode insulation - + conductor layer 33, as an electron channel of the thin film transistor., : ohmic contact layer (step: depositing on the semiconductor layer % (n Si ) to form the ohmic contact layer 34. The source and the immersion of the structure (steps now): the metal layer deposited on the ground in Europe, the working gas is Argon gas: in the stream, ', temple in 100SCCM), and at the same time pass nitrogen 1〇〇sccm, and with the ϊίΓΙ, the nitrogen flow from the contact _ gradually adjusted to 0 rrs〇r product - the thickness of the outline, Then pass nitrogen gas and gradually adjust to form the source of the nitriding layer structure and the 詋5 tiger line of 汲(4) to control the 〇/1 signal transmission. 11 1251877 Form the channel between the source and the drain (step 360) • The partial contact region 34 and a portion of the source and wave 35 are etched to form a channel % to form a thin film transistor structure. A passivation layer is formed (step 370): over the entire substrate 3, a coating is applied as the passivation layer 37 to avoid corrosion of moisture. Contact holes are formed (steps, steps): a plurality of contact holes 38 are formed on the passivation layer π, and a part of the source and drain electrodes 35 are exposed. Forming a halogen electrode (step,): finally, covering the indium oxide tin induim-tm-oxKie, ITO) transparent metal on the entire passivation layer 37, with the shape == the pixel electrode 39 can be electrically connected to the passivation through the contact hole % A ruthenium film transistor below layer 37. m!7, 'Because the flow rate of nitrogen is a gradual adjustment, the gate 31 sounds and the nitriding concentration and depth of the pole 35 _ and. The prior art multilayer structure between the pole and the source is not, The gate 31 and the source and drain 35 of the semiconductor element of the first volume are both different in nitridation, and the nitridation degree of the idler 31 is ^, and the near substrate is increasing away from the substrate, (4) = degree In the above-mentioned embodiments, the nitriding alloy and the nitride thereof may be used in the middle, respectively, in the direction away from the substrate and in the direction close to the substrate, and may also be a copper electrode and chromium, titanium, or Alloys and their nitrides. 1 ' Moreover, in the semiconductor device having a nitrided-protrusion structure of the present invention, the upper portion of the semiconductor element or the source is used, and the portion having a lower degree of nitridation can be used as the other portion where the protection is low. Buffering effect, while improving the undercut phenomenon of 12 1251877 money. In summary, the method provided by the present invention is a nitrided gradation structure of the opening and the source and the electrodeless film formation, and reduces the flow rate of the undercut 4, the vacuum The chamber is once smashed and the structure can be generated in the material interface problem. In addition, 4 π is free; the clothing is early and the material is lowered, so the equipment cost is not increased. Although the preferred embodiment of the present invention is disclosed to limit the present invention, any familiarity, scope, and scope of use of the invention may be The special brake of the present invention is only used for the change and retouching of the second half of the afternoon. Therefore, the patented thin dry wrap of the present invention is subject to the present specification. The definition of the patented target area of Jiaqiao [Simple description]
化漸層結構之閑極之半導體 化漸層結構之閘極之半導體 第1圖為本發明之包含氮 元件之示意圖； 苐2圖為本發明之包含氮 元件之流程圖； 之本2圖為本發明製作包含氮㈣層結構之源極與汲極 之半V體兀件之示意圖； ，第4圖為本發明製作包含氮化漸層結構之源極與汲 之半導體元件之流程圖； 乐5圖為本發明製作包含氮化漸層結構之閘極和 與汲極之半導體元件之示意圖；及 ” 13 1251877 氮化漸層結構之閉極和源極 【主要元件符號說明】 10 基板 11 閘極 20 基板 21 閘極 22 閘極絕緣層 23 半導體層 24 歐姆接觸層 25 源極與汲極 26 通道 30 基板 31 閘極 32 閘極絕緣層 33 半導體層 34 歐姆接觸層 35 源極與汲極 36 通道 37 鈍化層 38 接觸孔 39 畫素電極 步驟100 提供基 步驟110 形成氮 層結構之閘極 14 1251877The semiconductor of the semiconductor structure of the gradation structure of the immersed structure is shown in the first embodiment of the present invention as a nitrogen-containing element; FIG. 2 is a flow chart of the nitrogen-containing element of the present invention; The present invention is a schematic diagram of fabricating a half V body element comprising a source and a drain of a nitrogen (four) layer structure; and FIG. 4 is a flow chart of fabricating a semiconductor element including a source and a germanium of a nitrided layered structure; 5 is a schematic view of a semiconductor device including a gate and a drain of a nitrided gradation structure according to the present invention; and a closed and a source of a 13 1251877 nitrided gradation structure [Major component symbol description] 10 substrate 11 gate Pole 20 substrate 21 gate 22 gate insulating layer 23 semiconductor layer 24 ohmic contact layer 25 source and drain 26 channel 30 substrate 31 gate 32 gate insulating layer 33 semiconductor layer 34 ohmic contact layer 35 source and drain 36 Channel 37 passivation layer 38 contact hole 39 pixel electrode step 100 provides a step 110 to form a nitride layer of the gate 14 1251877
步驟200 提供基板 步驟210 形成閘極 步驟220 形成閘極絕緣層 步驟230 形成半導體層 步驟240 形成歐姆接觸層 步驟250 形成氮化漸層結構之源極與汲極 步驟260 形成通道於源極與汲極之間 步驟300 提供基板 步驟310 形成閘極 步驟320 形成閘極絕緣層 步驟330 形成半導體層 步驟340 形成歐姆接觸層 步驟350 形成氮化漸層結構之源極與汲極 步驟360 形成通道於源極與汲極之間 步驟370 形成鈍化層 步驟380 形成接觸孔 步驟390 形成晝素電極 15Step 200 provides a substrate step 210 forms a gate step 220 forms a gate insulating layer step 230 forms a semiconductor layer step 240 forms an ohmic contact layer step 250 forms a nitrided gradation structure source and drain step 260 forms a channel at the source and drain Step 300 is provided between the electrodes to provide the substrate step 310 to form the gate electrode step 320 to form the gate insulating layer step 330 to form the semiconductor layer step 340 to form the ohmic contact layer step 350 to form the source of the nitrided gradation structure and the drain step 360 to form the channel in the source Step 370 is formed between the pole and the drain to form a passivation layer. Step 380 is formed to form a contact hole. Step 390 is to form a halogen electrode 15