TWI254973B - Switching device for a pixel electrode and methods for fabricating the same - Google Patents

Abstract

The invention discloses a switching device for a pixel electrode of display device and methods for fabricating the same. A gate is formed on a portion of a substrate. A semiconductor layer is formed on the gate. A source and a drain are formed on a portion of the semiconductor layer. A low-k (low dielectric constant) material layer, such as a layer of a-SiC:H or a-SiCN:H, is formed between the gate and the semiconductor layer and/or on the source/drain.

Description

1254973 IX. Description of the Invention: [Technical Field] The present invention relates to a display, and more particularly to a switching element of a halogen electrode and a method of manufacturing the same. [Prior Art] A bottom-gate type thin film transistor element has been widely used in a thin film transistor liquid crystal display (TFT-LCD). Please refer to Figure 1 for a conventional bottom gate type thin film transistor structure. The thin film transistor structure 100 includes a substrate 110, a gate 120, a gate insulating layer 130, a channel layer 104, an ohmic contact layer 150, and a source/drain layer 160/170. In a thin film transistor structure of a conventional liquid crystal flat panel display, tantalum nitride (SiNx) is used as a cover passivation dielectric layer. However, since tantalum nitride (SiNx) has a dielectric constant of about 7, it may result in a higher resistance-capacitance time delay (RC delay). Especially when applied to large-size TFT LCD circuits, more severe time delays occur. SUMMARY OF THE INVENTION In view of the above, one of the main objects of the present invention is to reduce the resistance and capacitance time delay. In order to achieve the above object, the method of the present invention mainly comprises the following steps. 0632-A50435-TWf 5 1254973 First, a metal threat is formed on the substrate by chemical vapor deposition, dectrochemical plating (ECP) or physical vapor deposition. Receiver, perform a lithography process to form a gate, and form a gate to the part of one! The latter is compliantly formed with a low dielectric constant material layer over the interpole to cover the upper surface and sidewalls of the doping as a gate insulating layer (purchasing y y ' GIL ). Then, a semiconductor layer is formed on this gate insulating layer. The method for forming the interpolar insulating layer includes a chemical vapor deposition method and a plasma enhanced chemical vapor deposition method. The semiconductor layer includes an amorphous smcon layer (m〇^〇us smcon layer) ^M##0^^ (impunty„d〇ped ^ 〇^) deposited by the scale vapor deposition method. The traditional system "Wei Shang Ci Hui formed to form - channel layer and one ohmic contact layer., the receiver, using chemical vapor deposition, electrochemical electric coffee (4) network or physical vapor deposition method - Jin Gu An ohmic contact layer. Thereafter, the metal layer is selectively engraved with the ohmic portion to expose a portion of the surface of the channel layer to form a source-level extremely reduced body layer composed of a metal. The electrode is electrically connected to the source or the drain to obtain a thin film transistor structure. The method of the moon month further comprises: forming a chemical vapor deposition method or a plasma pressure type chemical vapor deposition method. a low dielectric constant layer is formed on the source/drain as the overlying protective layer. In addition, the gate insulating layer (G][L) may also include oxynitride (SiOxNy) or nitrite (SiNx). Stacking structure, such as double layer, structure: gate insulating layer / nitriding (GIL/SiNx,); or three-layer structure: gate insulation reoxygenation/nitridite (GIL/SiOxNy/SiNx,) or yttria/gate insulation/zinc nitride (si〇xNy/ GIL/s^^. 〇632-A50435-TWf 6 1254973 In addition, the above cap-passiVation layer (CPL) may also be a stacked structure containing bismuth oxynitride (SiOxNy) or tantalum nitride (SiNx). , for example, a two-layer structure: a cover protective layer / bismuth oxynitride (CPL /Si〇xNy) or a cover protective layer / tantalum nitride (CPL / SiNx) or tantalum nitride / cover protective layer (SiNx / cpL) or bismuth oxynitride / cover protective layer (Si〇xNy / CPL); or three-layer structure: cover protective layer / bismuth oxynitride / tantalum nitride (CPL / SiOxNy / SiNx) or cover protective layer / tantalum nitride / bismuth oxynitride (CPL) /SiNx/Si〇xNy) or yttrium oxynitride/covering protective layer/zinc nitride (Si〇xNy/CPL/SiNx) or yttrium niobium oxide/tantalum nitride/covering protective layer (SiOxNy/SiNx/CPL) or nitrogen ε / / cover protective layer / nitrous oxide Xi (SiNx / CPL / SiOxNy) or tantalum nitride / yttrium oxynitride / cover protective layer (SiNx / SiOxNy / CPL). The method of the present invention is a low dielectric constant material Replace the traditional A low dielectric constant layer is formed on the source/drain of the thin film transistor as a cover protective layer or as a metal gate dielectric layer. Alternatively, a low dielectric constant material can be substituted for the conventional nitride. Oh, as a dielectric layer of storage capacitors. # Moreover, according to the method of the present invention, it is not necessary to have a mask and the process is simple, and the resistance-capacitance time delay can be effectively reduced. The method of the present invention can be applied to a top gate type (t〇p_gate type) thin film transistor element, in addition to being applicable to a bottom-gate type. The above and other objects, features, and advantages of the present invention will become more <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Modes] The first embodiment is a preferred embodiment of the invention, which comprises the following main steps. As shown in FIG. 2A, a metal layer (not shown) is formed over a substrate 2i〇 using a chemical vapor deposition method, an electrochemical electric glazing plating; ECP) or a physical vapor deposition method, followed by a microscopic view. The etching process forms a substrate 22 (1) with a gate 22 and a portion of the substrate 210. The substrate 210 includes a glass substrate. The gate 22Q comprises copper, slag, silver, or an alloy of the above metals, and has a thickness of between about 100 and 500 nm. As shown in Fig. 2B, a layer of low dielectric constant material is first conformally formed over the gate 22G to cover the upper surface and sidewalls of the interpole as the gate insulating layer 230. A semiconductor layer (not shown) is formed at this gate and then, as shown in Fig. 2C, on the edge layer 230. The method for forming the gate insulating layer 230 includes a chemical vapor deposition method and a plasma enhanced chemical vapor deposition method. The pole insulating layer 23 includes carbon

A non-crystalline austenite (a-Sic: H) or a carbon-hydrogen-nitrogen-containing amorphous alumite (a-SlCN: H) having a thickness of between about 50 and 500 nm. And the semiconductor phase includes a conventional lithography process via a chemical gas, amethiphous silicon layer #^##^^^(impurity.d〇ped ^ 〇^ Forming a conductor layer to form a channel layer and an ohmic contact layer 250. The ohmic contact layer (4) is, for example, doped n-type_column such as p or AS) layer or _pwei·such as B wealth layer, and The thickness is between about 300 meters. The paste is an undoped non-four layer, and the thickness is about 6332-A50435-TWf 8 '1254973 as shown in Figure 2D. The chemical vapor deposition method and the electrochemical tree are used. (4) PMng; E〇&gt; M physical vapor deposition method formation - Jin Gu (not shown) on the ohmic contact layer 25A. Then, the metal layer and the contact layer are selectively engraved, and a portion of the surface of the channel layer 24 is exposed to form - from the source of the gold poplar and the top (4) above the semiconductor layer. Thereafter, the 'forming-pixel electrode' is electrically connected to the source or the secret 26Q/27G, and a thin film transistor structure 2GG is obtained. This secret 260/270 includes m or an alloy of the above metals. The thickness of this source/drain 260/270 is between about 1 and 5 nanometers. In other embodiments, the above-mentioned interlayer insulating layer 23 (gate inulating _; muscle) may be a stacked structure including oxynitride (10) x Ny) or nitrogen cut (SiNx), for example, a two-layer structure: inter-electrode insulating layer / nitriding ^GIL/SiNx,), or three-layer structure: gate insulating layer / oxynitride eve / II fossil eve (GIL / SiOxNy / SiNx,) or nitrous oxide oxide / gate insulating layer / tantalum nitride (SiOxNy /GIL/SiNx) 〇Second Embodiment The method of the present embodiment is similar to the first embodiment, but a conventional low-dielectric constant material is substituted for the conventional nitrogen cut as a cover protective layer. This embodiment includes the following

The main steps. In Fig. 3, π, using chemical vapor deposition, electrochemical microscopy, electroplating, ECP or physical vapor deposition to form a metal layer (not shown) above a substrate and then inserting U to perform the engraving process. And a gate 32 is formed over a portion of the substrate. This substrate 310 includes a glass substrate or a plastic substrate. The gate 32 〇 includes copper tone silver, or an alloy of the above metals, and has a thickness between about and 5 (8) nm. V &amp; compliantly formed - a layer of low dielectric constant material over the gate 320 as a gate insulating layer 33 〇. Then, a semiconductor layer (not shown in 0632-A50435-TWf 9 1254973) is formed on the dummy insulating layer 330. Wherein, the formation of the pole insulating layer 33〇 includes a chemical vapor deposition method and a plasma enhanced chemical vapor deposition method. The idler insulating layer 330 includes a carbon-hydrogen-containing amorphous alumite (which h) or a carbon-nitrogen-containing amorphous alumite (a-SlCN:H)' and has a thickness of about 5 〇 and 5 〇〇. Between the rice. The semiconductor layer includes, for example, an amorph〇us siHcon layer# deposited after chemical vapor deposition (impunty.d^^^^^^' by conventional lithography process patterning a semiconductor layer _ a channel layer 34 〇 and an ohmic contact layer 350. The ohmic contact layer 35Q is, for example, a doped n-type paste such as p or a layer of doped layer or a doped p such as B) layer, and The thickness is between ω and (10). The channel layer 340 is an undoped amorphous layer and has a thickness between about % and nanometer. ^ As shown in Fig. 3, a metal layer (not shown) is formed on the ohmic contact layer 350 by chemical vapor deposition, electrochemical recording, or physical vapor deposition, followed by selectivity. The metal layer and the ohmic contact layer 35 are grounded to a portion of the surface of the channel layer 340 to form a source/drain 36/37 of metal. Thereafter, a halogen electrode ' is electrically connected to the source or the electrodeless 360/370, and a thin film transistor structure 300 is obtained. This source grade 360/370 includes copper, ingot, silver, or an alloy of the above metals. The thickness of this source/bungee 360/370 is between about 1 and 5 nanometers. As shown in Fig. 3, chemical vapor deposition and Wei-enhanced chemical vapor deposition are then used. A low dielectric constant layer is formed on the source/dot pole 360/370± as the overlying protective layer 38〇. The overlying protective layer 380 comprises a hydrocarbon-containing amorphous germanide (a-Sic:H) or a hydrocarbon-containing amorphous germanide (a-SiCN:H). The thickness of the cover protective layer 380 is between about 1 and 4 nanometers. In other embodiments, the gate insulating layer 330 (gate mulating layer) can be 0632-A50435-TWf 10 1254973 structure, for example, a two-layer structure: a closed insulating layer / argon oxynitride / a very insulating layer / tantalum nitride It is a stacked gate insulating layer/tantalum nitride (GIL/SiNX5) containing yttrium oxynitride (Si〇xNy) or tantalum nitride (SiNx), or a three-layer structure: lanthanum nitride (GIL/SiOxNy/SiNX5) Or bismuth oxynitride / gate (Si〇xNy/GIL/SiNx).

The above capping layer (cap-passivation layer; CPT W can be included)

a stack structure of bismuth oxynitride (S:iOxNy) or lanthanum nitride (SlNx), such as a two-layer structure: a cover protective layer / bismuth oxynitride (CPL / SiOxNy) or a cover protective layer / tantalum nitride (CPL / SiNx) or Tantalum nitride/covering protective layer (SiNx/cPL) or niobium oxynitride/covering protective layer (SiOxNy/CPL); or three-layer structure·covering protective layer/niobium oxynitride/tantalum nitride (CPL/SiOxNy/SiNx ) or cover protective layer / tantalum nitride / bismuth oxynitride (CPL / SiNx / Si〇xNy) or bismuth oxynitride / cover protective layer / nitride eve (SiOxNy / CPL / SiNx) or nitrous oxide eve / nitrite / cover protective layer (SiOxNy / SiNx / CPL) or tantalum nitride / cover protective layer / bismuth oxynitride (SiNx / CPL / SiOxNy) or tantalum nitride / bismuth oxynitride / cover protective layer (SiNx / SiOxNy / CPL). In other embodiments, it is also possible to replace the conventional tantalum nitride with a low dielectric constant material as the dielectric of the storage capacitor. Moreover, according to the embodiment of the present invention, it is not necessary to have a mask and the process is simple, and the resistance-capacitance time delay can be effectively reduced. Embodiments of the present invention can be applied to a top gate type (t〇p_gate type) thin film transistor device, except that it can be applied outside the b〇ttom-gate type. Although the present invention has been disclosed above in several preferred embodiments, it is not intended to limit the invention by the use of the singularity of the present invention, and it is within the spirit and scope of the present invention. The scope of protection of the present invention is defined by the scope of the appended claims.

0632-A50435-TWf 12 ^ 1254973 [Simple description of the drawings] Fig. 1 is a schematic cross-sectional view showing the structure of a conventional thin film transistor. 2A-2D is a schematic cross-sectional view showing a structure of a thin film transistor according to a first embodiment of the present invention. Figure 3 is a schematic cross-sectional view showing the structure of a thin film transistor according to a second embodiment of the present invention. [Description of main component symbols] 100, 200, 300~ thin film transistor structure 110, 210, 310~ 〃 substrate, 120, 220, 320~ 〃 gate; 130, 230, 330~ &lt; gate insulating layer; 140 240, 340~ / channel layer, 150, 250, 350~ &gt; ohmic contact layer; 160, 260 '360~-source; 170^270 &gt; 370~ &gt;bungee; 38 (l·^ cover protection: Cover 0 0632-A50435-TWf 13

Claims (1)

, 1254973 &lt; X. Patent application scope · · · · The switch tree of the halogen element electrode, suitable for display, including · a gate, located above a part of the substrate; a semiconductor layer, located above the gate; a source/drain, located above a portion of the semiconductor layer, and a layer of low dielectric constant material between the gate and the semiconductor layer and/or at the source/level of the low dielectric constant material The layer includes a hydrocarbon-containing amorphous material (hands-up) or a carbon-hydrogen-nitrogen-containing amorphous stone compound (}% Ν··Ή). 2. For example, please refer to the patented element of the halogen electrode described in Item 1, which further includes: a halogen electrode electrically connected to the source or the drain. ~ ,, 3. If you apply for a patent Gu Di! The touch element of the present invention, wherein the low dielectric constant material layer covers the upper surface and the sidewall of the gate. 4. The material of the element of the electrode of the first embodiment is described in the above, wherein the substrate comprises a glass substrate or a plastic substrate. 5. The switching element of the pixel electrode of claim 1, wherein the gate comprises copper, samarium, silver or an alloy of the above metals. 6. The switching element of a halogen electrode according to the invention of claim 2, wherein the semiconductor layer comprises a stone eve. 7. The switching element of the halogen electrode according to the first aspect of the invention, wherein the source electrode comprises copper, inscription, silver or an alloy of the above metals. The switching element of the halogen electrode according to the first aspect of the invention, wherein the low dielectric constant material layer comprises a gate insulating layer. 9. The switching element of a pixel electrode according to claim 1, wherein the low dielectric constant material layer comprises a cover protective layer. 10) A method for manufacturing a switching element of a halogen electrode, comprising: forming a gate over a portion of a substrate; 0632-A50435-TWf 14 1254973 forming a semiconductor layer over the gate; forming a source/drain And a portion of the low dielectric f-number material layer comprising hydrocarbon-containing material (a) -slC:H) or alumite (a_SicN:H) of bismuth hydrocarbon. The method for manufacturing a switching element of a halogen electrode according to claim 10, comprising: forming a halogen electrode electrically connected to the source or the drain. 12. If the application is turned over (4), the method of manufacturing the switch phase is φ. The 戎 low dielectric constant material layer covers the upper surface and the sidewall of the gate. 13. The method of manufacturing a pixel element for a pixel electrode according to the patent application, wherein the δ ray substrate comprises a glass substrate or a plastic substrate. The method of manufacturing a switching element of a halogen electrode according to claim 10, wherein the gate comprises copper, Ilu, silver, or an alloy of the above metals. 15. The switching element system of the elemental f-pole described in claim 1Q of the patent application, wherein the semiconductor layer comprises germanium. The method of manufacturing a switching element of a halogen electrode as described in claim 10, wherein the source/drain includes copper, aluminum, silver, or an alloy of the above metals. The method of manufacturing a switching element of a halogen electrode according to the first aspect of the invention, wherein the low dielectric constant material layer comprises a gate insulating layer. 18. The method of manufacturing a switching element for a halogen electrode according to claim 10, wherein the low dielectric constant material layer comprises a frost layer and a wind% composite layer. 0632-A50435-TWf 15