JP5561485B2 - ピッチマルチプリケーションされた材料のループの一部分を分離するための方法およびその関連構造 - Google Patents
ピッチマルチプリケーションされた材料のループの一部分を分離するための方法およびその関連構造 Download PDFInfo
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- JP5561485B2 JP5561485B2 JP2010539709A JP2010539709A JP5561485B2 JP 5561485 B2 JP5561485 B2 JP 5561485B2 JP 2010539709 A JP2010539709 A JP 2010539709A JP 2010539709 A JP2010539709 A JP 2010539709A JP 5561485 B2 JP5561485 B2 JP 5561485B2
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Description
本出願は、以下に関連し、以下を参照により、その全体を組み入れる。それは、2004年9月2日に出願された、Abatchevらによる米国特許出願整理番号10/934,778(代理人整理番号:MICRON.294A)、2004年8月31日に出願された、Tranらによる米国特許出願整理番号10/931,771(代理人整理番号:MICRON.295A)、2005年8月31日に出願された、Tranらによる米国特許出願整理番号11/216,477(代理人整理番号:MICRON.314A)および2005年8月29日に出願された、Tranらによる米国特許出願整理番号11/214,544(代理人整理番号:MICRON.316A)である。
本発明は、概して集積回路および電子デバイスの作製に関し、より詳細には、作製方法および関連構造に関する。
携帯性、計算能力、メモリ容量およびエネルギー効率を増加させる要求を含む、多数の要因の結果として、集積回路はそのサイズが絶えず縮小している。例えば電気デバイスおよび相互接続配線などの集積回路を形成する構成フィーチャのサイズもまた、集積回路のサイズ縮小を容易にするために、絶えず縮小されている。
Claims (10)
- スペーサによって規定される、半導体材料で形成された複数のループを有する基板を提供するステップであって、前記複数のループの各々は、前記ループのうちの前記各々の第一の端部および逆の第二の端部で結合される、第一および第二の細長い部分によって画定される、ステップと、
前記複数のループの各々のうちの、第一の細長い部分に沿って、第一の対のトランジスタの各々を提供するステップであって、前記第一の対のトランジスタのうちの一つのトランジスタは、前記複数のループの前記第一の端部の近傍にあり、前記第一の対のトランジスタのうちの別のトランジスタは、前記複数のループの前記第二の端部の近傍にあり、各々のループは、前記第一の対のトランジスタのうちの各一つのアクティブ領域を形成する、ステップと、
を含み、
前記第一の対のトランジスタの各々一つを提供するステップは、
複数のソース/ドレイン領域を形成するために、前記トランジスタの前記アクティブ領域の両側をそれぞれドープするステップと、
前記アクティブ領域を形成する前記ループを直接覆ってトランジスタゲートを形成するステップであって、前記ゲートは、前記アクティブ領域を自体の下に画定するステップと、を含み、
前記複数のループの前記第一の端部は、ソース/ドレイン領域であり、前記ループの前記第1の端部をトランジスタの前記第一の対の前記ゲートと直接接続する電気的接続を提供し、前記ソース/ドレイン領域と前記ゲートとを電気的に短絡するステップを含むことを特徴とする集積回路作成方法。 - 前記一つのトランジスタは、前記第一の細長い部分に沿って配置され、
前記ループの対が、前記別のトランジスタのアクティブ領域を形成するステップをさらに含み、
前記一つのトランジスタと前記別のトランジスタは、前記ループ端部の近傍に配置される、
ことを特徴とする、請求項1に記載の方法。 - 前記ループを有する前記基板を提供するステップは、ピッチマルチプリケーションを実施するステップによって前記ループを形成するステップを含み、ピッチマルチプリケーションを実施するステップは、
前記基板の上にマンドリルを形成するステップと、
前記マンドリルの複数の側壁に接してスペーサを形成するステップと、
独立した複数のスペーサのパターンを残すために、前記複数のマンドリルを除去するステップと、
前記半導体材料を含む層中へと、前記独立した複数のスペーサによって画定されたパターンをエッチングするステップと、
を含む、
ことを特徴とする、請求項1に記載の方法。 - 前記複数のループの上に半導体材料層を形成するステップと、
前記半導体材料層の上にマスク材料層を形成するステップと、
前記複数のループの各々を横切って伸長する、一つ以上のマスキング材料のストリップ
を形成するために、前記マスク材料層をパターン化するステップと、
半導体材料の複数のストリップを形成するために、前記複数のストリップよって画定されるパターンを、前記半導体材料層に転写するステップと、
を含む、
ことを特徴とする、請求項1に記載の方法。 - 集積回路を形成するためのプロセスであって、
基板の上に存在する複数のマンドリルを提供するステップと、
前記複数のマンドリルの複数の側壁に複数のスペーサを提供するステップと、
前記複数のスペーサに対して、前記複数のマンドリルを選択的に除去するステップと、
前記複数のスペーサを覆ってマスク材料の層を堆積するステップと、
前記マスク材料のラテラル方向に分離された第一および第二のブロックを形成するために、前記マスク材料層をパターン化するステップであって、前記第一のブロックは、前記複数のスペーサの各々の第一の端部と接触し、前記第二のブロックは、前記複数のスペーサの各々の第二の端部と接触する、ステップと、
前記複数のスペーサならびに前記第一および第二のブロックによって画定された第一のパターンを前記基板へと転写し、それによって、基板上にピッチマルチプリケーションが施された複数のラインおよびブロックが形成され、前記ピッチマルチプリケーションが施された複数のラインの各々は、前記ブロックと接触し、前記第一及び第二のブロックと隣接するループを形成するステップと、
前記第一のブロックの近くに第一のトランジスタゲートを、前記第二のブロックの近くに第二のトランジスタゲートを形成するステップと、
前記第一のブロックを前記第一のトランジスタゲートと、前記第二のブロックを前記第二のトランジスタゲートと直接に接続する電気的接続を提供し、前記第一のブロックと第一のトランジスタゲートを、前記第二のブロックと前記第二のトランジスタゲートと電気的に短絡し、前記トランジスタゲートは、前記ループの延伸部分を電気的に隔離するように構成されているステップと、
を含む
ことを特徴とするプロセス。 - 複数のマンドリルを提供するステップは、
前記基板の上に存在するフォトレジスト層を提供するステップと、
複数のフォトレジストフィーチャを形成するために、前記フォトレジスト層をパターン化するステップと、
前記複数のフォトレジストフィーチャをトリミングするステップと、
を含み、
前記トリミングされた複数のフォトレジストフィーチャは、前記複数のマンドリルを形成する、
ことを特徴とする、請求項5に記載のプロセス。 - 前記複数のマンドリルの複数の側壁に複数のスペーサを提供するステップは、
前記複数のフォトレジストフィーチャを覆って、スペーサ材料の層をブランケット堆積するステップと、
前記複数のフォトレジストフィーチャの複数の側壁上に複数のスペーサを画定するために、複数の水平表面から前記スペーサ材料を除去するステップと、
を含む、
ことを特徴とする、請求項5に記載のプロセス。 - 前記基板へと、前記複数のスペーサならびに前記第一および第二のブロックによって画定された前記第一のパターンを転写するステップは、
ハードマスク層へと、前記複数のスペーサならびに前記第一および第二のブロックによって画定された前記第一のパターンを転写するステップと、
前記ハードマスク層から前記基板へと前記第一のパターンを転写するステップと、
を含む、
ことを特徴とする、請求項5に記載のプロセス。 - 前記複数のスペーサと前記ハードマスク層との間のレベルに一つ以上のさらなるハードマスク層を提供するステップと、
前記ハードマスク層へと前記第一のパターンを転写するステップの前に、前記一つ以上のさらなるハードマスク層へと前記第一のパターンを転写するステップと、
をさらに含む、
ことを特徴とする、請求項8に記載のプロセス。 - 前記ハードマスク層は、非晶質炭素で形成される、
ことを特徴とする、請求項8に記載のプロセス。
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US9941155B2 (en) | 2018-04-10 |
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US20170250110A1 (en) | 2017-08-31 |
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KR101603800B1 (ko) | 2016-03-25 |
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US20130171784A1 (en) | 2013-07-04 |
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US20090152645A1 (en) | 2009-06-18 |
US9666695B2 (en) | 2017-05-30 |
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US8390034B2 (en) | 2013-03-05 |
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US8932960B2 (en) | 2015-01-13 |
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