JP5719911B2 - ピッチマルチプリケーションされた材料のループの一部分を分離するための方法およびその関連構造 - Google Patents
ピッチマルチプリケーションされた材料のループの一部分を分離するための方法およびその関連構造 Download PDFInfo
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- JP5719911B2 JP5719911B2 JP2013242620A JP2013242620A JP5719911B2 JP 5719911 B2 JP5719911 B2 JP 5719911B2 JP 2013242620 A JP2013242620 A JP 2013242620A JP 2013242620 A JP2013242620 A JP 2013242620A JP 5719911 B2 JP5719911 B2 JP 5719911B2
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Description
本出願は、以下に関連し、以下を参照により、その全体を組み入れる。それは、2004年9月2日に出願された、Abatchevらによる米国特許出願整理番号10/934,778(代理人整理番号:MICRON.294A)、2004年8月31日に出願された、Tranらによる米国特許出願整理番号10/931,771(代理人整理番号:MICRON.295A)、2005年8月31日に出願された、Tranらによる米国特許出願整理番号11/216,477(代理人整理番号:MICRON.314A)および2005年8月29日に出願された、Tranらによる米国特許出願整理番号11/214,544(代理人整理番号:MICRON.316A)である。
本発明は、概して集積回路および電子デバイスの作製に関し、より詳細には、作製方法および関連構造に関する。
携帯性、計算能力、メモリ容量およびエネルギー効率を増加させる要求を含む、多数の要因の結果として、集積回路はそのサイズが絶えず縮小している。例えば電気デバイスおよび相互接続配線などの集積回路を形成する構成フィーチャのサイズもまた、集積回路のサイズ縮小を容易にするために、絶えず縮小されている。
ョン”は、実際には、その係数でのピッチの縮小に関係している。本明細書では、従来用語がそのまま使用される。
一のパターン化、ドーピングおよび堆積ステップを使用して分離トランジスタを形成することが可能であることが理解されるであろう。結果として、多くの実施形態においては、分離トランジスタの形成は、このプロセスフローに対して、いかなる追加ステップも導入しない。さらには、ループエッチングを不要にすることによって、ループエッチングに関連するプロセスステップを省略することが可能である。したがって、プロセスフローは単純化され、プロセススループットは増加する。
であり、これは、例えばフォトレジストで形成される。このフォトレジストには、あらゆるポジティブもしくはネガティブフォトレジストを含む本技術分野で既知のあらゆるフォトレジストが含まれる。例えば、このフォトレジストは、157nm、193nm、248nm、もしくは365nm波長システム、193nm波長液浸システム、(13.7nm波長システムを含む)極紫外線システム、または電子ビームリソグラフィーシステムと適合する任意のフォトレジストでよい。さらには、マスクレスリソグラフィーもしくはマスクレスフォトリソグラフィーを、選択的画定可能層120を画定するために使用することができる。フォトレジスト材料の例は、フッ化アルゴン(ArF)感受性フォトレジスト、つまりArF光源と使用するのに適切なフォトレジスト、およびフッ化クリプトン(KrF)感受性フォトレジスト、つまりKrF光源と使用するのに適切なフォトレジストを含む。ArFフォトレジストは、比較的短い波長の光、例えば193nm波長光を使用するフォトリソグラフィーシステムで使用される。KrFフォトレジストは、248nmシステムなどのより長い波長のフォトリソグラフィーシステムで使用される。他の実施形態においては、層120およびそれに続くレジスト層があればそれを、ナノインプリントリソグラフィーによって(例えば、モールド(mold)もしくは機械力を使用してレジストをパターン化することによって)パターン化することのできるレジストで形成することが
できる。
る米国特許整理番号6,573,030B1に記述され、その全開示は本明細書に参照として組み
入れられる。幾つかの実施形態においては、非晶質炭素は、光に対する高い透過性を有するとともに、光配向(photo alignment)に使用される光波長に対して透過性を有するこ
とによってその光配向に対してさらなる改善を提供する型の非晶質炭素である。このような透過性炭素を形成するための堆積技術は、A.HelmboldおよびD.MeissnerによるThin Solid Films, 283 (1996), 196-203に見出すことができ、その全開示は本明細書に参照として組み入れられる。さらには、非晶質炭素は、ドープされてもよい。ドープされた非晶質炭素を形成するのに適切な一方法が、Yinらによる米国特許出願整理番号10/652,174に記
述され、その全開示は本明細書に参照として組み入れられる。
ルスへと導入される。ALD(原子層堆積)を、比較的低温、例えば、約200℃未満もしくは約100℃未満で実施することができ、これには、フォトレジスト層や非晶質炭素層などの下部の炭素ベースの材料に対する熱的損傷を防ぐという利点がある。他の実施形態においては、スペーサ材料を堆積するために化学蒸着を使用するが、例えば、O3およ
びTEOSを使用してシリコン酸化物を形成する。
ク層130の異方性エッチングによって達成することができる。
ることによって、個々のビット線をお互いから電気的に分離する。短絡された端部は、ブロック320および322(図17B)に相当し、選択トランジスタ412、414のゲートは、フィーチャ342、343(図17B)に相当する。
ことがある。例えば、材料が別の理由のために短絡される場合、例えば、ループを形成するラインが、一端で全て接地に結合される場合には、接地に結合された端部におけるラインを電気的に分離するための分離トランジスタを形成する必要をなくすことができる。しかしながら、上述されたように、ループの端部における材料のブロック形成は、ラインによって画定されるトレンチの充填を改善するという利点を有する。結果として、ループ両端におけるブロックを形成することは、一端における電気的分離が必要ではない場合でさえも望ましいことがある。
Claims (11)
- 半導体材料の間隔の開いた細長い複数のストリップと、
半導体材料の前記細長い複数のストリップと同一レベル上にあり、前記細長い複数のストリップの各々の第一の端部と接触する、半導体材料の第一のブロックと、
前記細長いストリップの前記第一の端部と近接して配置された第一の複数のトランジスタゲートであって、前記第一の複数のトランジスタゲートの各々は前記細長いストリップのうちの一つと関連付けられ、前記細長いストリップのそれぞれの一部分は、関連する第一のトランジスタゲートのアクティブ領域を形成する、第一の複数のトランジスタゲートと、
前記第一の複数のトランジスタゲートが前記第一のブロックと電気的に短絡されるよう、前記第一の複数のトランジスタゲートを前記第一のブロックと接続する電気的相互接続と、
を含む、ことを特徴とする集積回路。 - 半導体材料の間隔の開いた細長い複数のストリップと、
半導体材料の前記細長い複数のストリップと同一レベル上にあり、前記細長い複数のストリップの各々の第一の端部と接触する、半導体材料の第一のブロックと、
前記細長いストリップの前記第一の端部と近接して配置された第一の複数のトランジスタゲートであって、前記第一の複数のトランジスタゲートの各々は前記細長いストリップのうちの一つと関連付けられ、前記細長いストリップのそれぞれの一部分は、関連する第一のトランジスタゲートのアクティブ領域を形成する、第一の複数のトランジスタゲートと、
前記第一の複数のトランジスタゲートが前記第一のブロックと電気的に短絡されるよう、前記第一の複数のトランジスタゲートを前記第一のブロックと接続する電気的相互接続と、
を含み、
前記細長いストリップのそれぞれは、前記細長いストリップ上の選択トランジスタを更に含み、前記選択トランジスタは、前記第一のトランジスタゲートの、前記第一の端部とは反対側にある、ことを特徴とする集積回路。 - 前記細長いストリップと同一レベル上にあり、前記細長いストリップの第二の端部と接触する、半導体材料を含む第二のブロックと、
前記細長いストリップの前記第二の端部と近接して配置された第二の複数のトランジスタゲートであって、前記第二の複数のトランジスタゲートの各々は前記細長いストリップのうちの一つと関連付けられ、前記細長いストリップのそれぞれの一部分は、関連する第二のトランジスタゲートのアクティブ領域を形成する、第二の複数のトランジスタゲートと、
前記第二の複数のトランジスタゲートが前記第二のブロックと電気的に短絡されるよう、前記第二の複数のトランジスタゲートを前記第二のブロックと接続する電気的相互接続と、
を更に含むことを特徴とする請求項2に記載の集積回路。 - 前記第一のブロックは、前記第一の複数のトランジスタゲートに対する第一のソース/ドレインを形成し、前記第二のブロックは、前記第二の複数のトランジスタゲートに対する第二のソース/ドレインを形成することを特徴とする請求項3に記載の集積回路。
- 半導体材料の前記細長いストリップは、メモリデバイスのビット線をなし、前記第一の複数のトランジスタゲートは、メモリデバイスのワード線の一部をなすことを特徴とする請求項2に記載の集積回路。
- 集積回路を形成するためのプロセスであって、
基板の上に存在する第一のマスク材料の複数の細長いループを提供するステップと、
前記ループを覆って第二のマスク材料の層を提供するステップと、
前記第二のマスク材料のブロックを形成するために前記層をパターン化するステップであって、前記ブロックは前記ループの各々の端部と接触する、ステップと、
前記複数のループおよび前記ブロックによって画定された第一のパターンを前記基板へと転写するステップと、
続いて、前記基板の上に半導体材料の層を形成するステップと、
前記半導体材料の上にマスク材料の他の層を形成するステップと、
前記ループの各々を横切って伸長し、前記複数のループの各々と接触する一つ以上のマスキング材料のストリップを形成するために、前記他の層をパターン化するステップと、
前記複数のストリップによって画定された第二のパターンを、半導体材料の複数のストリップを形成するために前記半導体材料層へと転写するステップと、
前記半導体材料の前記複数のストリップと、前記第二のマスク材料の前記ブロックによって画定された複数の基板フィーチャとを、電気的に接続するステップと、
を含み、
前記半導体材料の前記複数のストリップを電気的に接続するステップは、前記半導体材料の前記ストリップの上にトランジスタゲートを形成するステップと、複数のソース/ドレイン領域を形成するために、前記トランジスタゲートの両側をそれぞれドープするステップと、を含み、
前記第二のマスク材料の前記ブロックによって画定された複数の基板フィーチャは、ソース領域であり、前記半導体材料の前記複数のストリップを電気的に接続するステップは、前記ソース領域と前記ゲートとを電気的に短絡するステップを含む、ことを特徴とするプロセス。 - 前記第二のパターンを転写するステップは、トランジスタのゲートを画定し、前記第一のパターンを転写するステップは、前記トランジスタのソース/ドレイン領域を画定する、ことを特徴とする、請求項6に記載のプロセス。
- 前記第一のパターンを転写するステップは、メモリデバイスのビット線を画定する、ことを特徴とする、請求項6に記載のプロセス。
- 前記第二のパターンを転写するステップは、前記メモリデバイスのワード線を画定する、ことを特徴とする、請求項8に記載のプロセス。
- 前記集積回路はフラッシュメモリ回路であり、前記第一および前記第二のパターンを転写するステップは、前記フラッシュメモリ回路のアレイ領域における複数の浮遊ゲートトランジスタを画定する、ことを特徴とする、請求項6に記載のプロセス。
- 前記層をパターン化するステップは、前記フラッシュメモリ回路の周辺領域におけるフィーチャを画定する、ことを特徴とする、請求項6に記載のプロセス。
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Families Citing this family (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7923373B2 (en) | 2007-06-04 | 2011-04-12 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
US8980756B2 (en) | 2007-07-30 | 2015-03-17 | Micron Technology, Inc. | Methods for device fabrication using pitch reduction |
US8481417B2 (en) | 2007-08-03 | 2013-07-09 | Micron Technology, Inc. | Semiconductor structures including tight pitch contacts and methods to form same |
US7790531B2 (en) | 2007-12-18 | 2010-09-07 | Micron Technology, Inc. | Methods for isolating portions of a loop of pitch-multiplied material and related structures |
US8030218B2 (en) | 2008-03-21 | 2011-10-04 | Micron Technology, Inc. | Method for selectively modifying spacing between pitch multiplied structures |
JP2009295785A (ja) * | 2008-06-05 | 2009-12-17 | Toshiba Corp | 半導体装置の製造方法 |
US8076208B2 (en) | 2008-07-03 | 2011-12-13 | Micron Technology, Inc. | Method for forming transistor with high breakdown voltage using pitch multiplication technique |
JP5665289B2 (ja) | 2008-10-29 | 2015-02-04 | 株式会社日立国際電気 | 半導体装置の製造方法、基板処理方法および基板処理装置 |
KR101045090B1 (ko) * | 2008-11-13 | 2011-06-29 | 주식회사 하이닉스반도체 | 반도체 소자의 미세 패턴 형성방법 |
US8492282B2 (en) | 2008-11-24 | 2013-07-23 | Micron Technology, Inc. | Methods of forming a masking pattern for integrated circuits |
KR101077453B1 (ko) * | 2009-03-31 | 2011-10-26 | 주식회사 하이닉스반도체 | 반도체 소자의 패턴 형성 방법 |
JP4982582B2 (ja) * | 2010-03-31 | 2012-07-25 | 株式会社東芝 | マスクの製造方法 |
KR101150639B1 (ko) * | 2010-06-17 | 2012-07-03 | 에스케이하이닉스 주식회사 | 반도체 소자의 패턴 형성 방법 |
US8940475B2 (en) * | 2010-11-23 | 2015-01-27 | Tokyo Electron Limited | Double patterning with inline critical dimension slimming |
KR20120062385A (ko) * | 2010-12-06 | 2012-06-14 | 에스케이하이닉스 주식회사 | 반도체 메모리 소자의 형성방법 |
US8536674B2 (en) | 2010-12-20 | 2013-09-17 | General Electric Company | Integrated circuit and method of fabricating same |
US9525007B2 (en) * | 2010-12-28 | 2016-12-20 | Micron Technology, Inc. | Phase change memory device with voltage control elements |
TWI473205B (zh) * | 2011-11-24 | 2015-02-11 | Powerchip Technology Corp | 接觸窗開口的形成方法 |
US8802510B2 (en) * | 2012-02-22 | 2014-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for controlling line dimensions in spacer alignment double patterning semiconductor processing |
US8889561B2 (en) * | 2012-12-10 | 2014-11-18 | Globalfoundries Inc. | Double sidewall image transfer process |
KR102059183B1 (ko) | 2013-03-07 | 2019-12-24 | 삼성전자주식회사 | 반도체 장치의 제조 방법 및 이에 의해 제조된 반도체 장치 |
JP6091940B2 (ja) * | 2013-03-11 | 2017-03-08 | 株式会社日立国際電気 | 半導体装置の製造方法、基板処理装置およびプログラム |
US9177797B2 (en) * | 2013-12-04 | 2015-11-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lithography using high selectivity spacers for pitch reduction |
US9029263B1 (en) * | 2013-12-12 | 2015-05-12 | Texas Instruments Incorporated | Method of printing multiple structure widths using spacer double patterning |
KR102290460B1 (ko) * | 2014-08-25 | 2021-08-19 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
US9324619B2 (en) * | 2014-08-25 | 2016-04-26 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
JP6382055B2 (ja) * | 2014-10-07 | 2018-08-29 | 東京エレクトロン株式会社 | 被処理体を処理する方法 |
US9673055B2 (en) | 2015-02-04 | 2017-06-06 | Globalfoundries Inc. | Method for quadruple frequency FinFETs with single-fin removal |
US9882028B2 (en) * | 2016-06-29 | 2018-01-30 | International Business Machines Corporation | Pitch split patterning for semiconductor devices |
JP6814377B2 (ja) * | 2016-10-20 | 2021-01-20 | 東京エレクトロン株式会社 | ビア対グリッドのパターニングにおけるオーバレイエラーを減少する方法 |
EP3419047A1 (en) * | 2017-06-22 | 2018-12-26 | IMEC vzw | A method for patterning a target layer |
CN110581066B (zh) * | 2018-06-07 | 2024-06-21 | 长鑫存储技术有限公司 | 多倍掩膜层的制作方法 |
CN110767538B (zh) * | 2018-07-26 | 2024-06-07 | 长鑫存储技术有限公司 | 版图结构以及半导体集成电路器件的形成方法 |
US11011581B2 (en) * | 2019-06-10 | 2021-05-18 | Western Digital Technologies, Inc. | Multi-level loop cut process for a three-dimensional memory device using pitch-doubled metal lines |
US10978482B2 (en) * | 2019-06-28 | 2021-04-13 | Sandisk Technologies Llc | Ferroelectric memory device with select gate transistor and method of forming the same |
Family Cites Families (240)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5748237Y2 (ja) | 1978-12-28 | 1982-10-22 | ||
US4234362A (en) | 1978-11-03 | 1980-11-18 | International Business Machines Corporation | Method for forming an insulator between layers of conductive material |
JPS5748237A (en) | 1980-09-05 | 1982-03-19 | Nec Corp | Manufacture of 2n doubling pattern |
US4508579A (en) | 1981-03-30 | 1985-04-02 | International Business Machines Corporation | Lateral device structures using self-aligned fabrication techniques |
US4432132A (en) | 1981-12-07 | 1984-02-21 | Bell Telephone Laboratories, Incorporated | Formation of sidewall oxide layers by reactive oxygen ion etching to define submicron features |
US4419809A (en) | 1981-12-30 | 1983-12-13 | International Business Machines Corporation | Fabrication process of sub-micrometer channel length MOSFETs |
DE3242113A1 (de) | 1982-11-13 | 1984-05-24 | Ibm Deutschland Gmbh, 7000 Stuttgart | Verfahren zur herstellung einer duennen dielektrischen isolation in einem siliciumhalbleiterkoerper |
US4716131A (en) | 1983-11-28 | 1987-12-29 | Nec Corporation | Method of manufacturing semiconductor device having polycrystalline silicon layer with metal silicide film |
US4648937A (en) | 1985-10-30 | 1987-03-10 | International Business Machines Corporation | Method of preventing asymmetric etching of lines in sub-micrometer range sidewall images transfer |
GB8528967D0 (en) | 1985-11-25 | 1986-01-02 | Plessey Co Plc | Semiconductor device manufacture |
DE3682395D1 (de) * | 1986-03-27 | 1991-12-12 | Ibm | Verfahren zur herstellung von seitenstrukturen. |
US4778922A (en) | 1986-06-17 | 1988-10-18 | Hoechst Celanese Corporation | Process for producing N,O-diacetyl-6-amino-2-naphthol |
US5514885A (en) | 1986-10-09 | 1996-05-07 | Myrick; James J. | SOI methods and apparatus |
JPS63302252A (ja) | 1987-05-30 | 1988-12-09 | Nitto Kohki Co Ltd | 液体加熱貯留装置 |
JPS6435916A (en) | 1987-07-31 | 1989-02-07 | Hitachi Ltd | Formation of fine pattern |
JPS6435916U (ja) | 1987-08-28 | 1989-03-03 | ||
US4776922A (en) | 1987-10-30 | 1988-10-11 | International Business Machines Corporation | Formation of variable-width sidewall structures |
US4838991A (en) | 1987-10-30 | 1989-06-13 | International Business Machines Corporation | Process for defining organic sidewall structures |
US5328810A (en) | 1990-05-07 | 1994-07-12 | Micron Technology, Inc. | Method for reducing, by a factor or 2-N, the minimum masking pitch of a photolithographic process |
JPH0414255A (ja) * | 1990-05-07 | 1992-01-20 | Toshiba Corp | Mos型半導体装置 |
US5013680A (en) | 1990-07-18 | 1991-05-07 | Micron Technology, Inc. | Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography |
WO1992002044A1 (en) | 1990-07-18 | 1992-02-06 | Seiko Epson Corporation | Semiconductor device |
US5053105A (en) | 1990-07-19 | 1991-10-01 | Micron Technology, Inc. | Process for creating an etch mask suitable for deep plasma etches employing self-aligned silicidation of a metal layer masked with a silicon dioxide template |
DE4034612A1 (de) | 1990-10-31 | 1992-05-07 | Huels Chemische Werke Ag | Verfahren zur herstellung von methacryloxy- oder acryloxygruppen enthaltenden organosilanen |
IT1243919B (it) | 1990-11-20 | 1994-06-28 | Cons Ric Microelettronica | Procedimento per l'ottenimento di solchi submicrometrici planarizzati in circuiti integrati realizzati con tecnologia ulsi |
JP3098786B2 (ja) | 1991-04-05 | 2000-10-16 | 株式会社日立製作所 | 半導体集積回路装置 |
JPH05343370A (ja) | 1992-06-10 | 1993-12-24 | Toshiba Corp | 微細パタ−ンの形成方法 |
US5330879A (en) | 1992-07-16 | 1994-07-19 | Micron Technology, Inc. | Method for fabrication of close-tolerance lines and sharp emission tips on a semiconductor wafer |
DE4236609A1 (de) | 1992-10-29 | 1994-05-05 | Siemens Ag | Verfahren zur Erzeugung einer Struktur in der Oberfläche eines Substrats |
US5407785A (en) | 1992-12-18 | 1995-04-18 | Vlsi Technology, Inc. | Method for generating dense lines on a semiconductor wafer using phase-shifting and multiple exposures |
US5470661A (en) | 1993-01-07 | 1995-11-28 | International Business Machines Corporation | Diamond-like carbon films from a hydrocarbon helium plasma |
US6042998A (en) | 1993-09-30 | 2000-03-28 | The University Of New Mexico | Method and apparatus for extending spatial frequencies in photolithography images |
KR0122315B1 (ko) | 1993-12-27 | 1997-11-26 | 김주용 | 고집적 반도체 소자의 미세패턴 형성방법 |
KR950034748A (ko) | 1994-05-30 | 1995-12-28 | 김주용 | 포토레지스트 패턴 형성방법 |
KR970007173B1 (ko) | 1994-07-14 | 1997-05-03 | 현대전자산업 주식회사 | 미세패턴 형성방법 |
JPH0855920A (ja) * | 1994-08-15 | 1996-02-27 | Toshiba Corp | 半導体装置の製造方法 |
JPH0855908A (ja) | 1994-08-17 | 1996-02-27 | Toshiba Corp | 半導体装置 |
US5600153A (en) | 1994-10-07 | 1997-02-04 | Micron Technology, Inc. | Conductive polysilicon lines and thin film transistors |
TW366367B (en) | 1995-01-26 | 1999-08-11 | Ibm | Sputter deposition of hydrogenated amorphous carbon film |
US5795830A (en) | 1995-06-06 | 1998-08-18 | International Business Machines Corporation | Reducing pitch with continuously adjustable line and space dimensions |
KR100190757B1 (ko) | 1995-06-30 | 1999-06-01 | 김영환 | 모스 전계 효과 트랜지스터 형성방법 |
JP3393286B2 (ja) | 1995-09-08 | 2003-04-07 | ソニー株式会社 | パターンの形成方法 |
US5789320A (en) | 1996-04-23 | 1998-08-04 | International Business Machines Corporation | Plating of noble metal electrodes for DRAM and FRAM |
TW329539B (en) * | 1996-07-05 | 1998-04-11 | Mitsubishi Electric Corp | The semiconductor device and its manufacturing method |
JP3164026B2 (ja) | 1996-08-21 | 2001-05-08 | 日本電気株式会社 | 半導体装置及びその製造方法 |
US5753548A (en) * | 1996-09-24 | 1998-05-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for preventing fluorine outgassing-induced interlevel dielectric delamination on P-channel FETS |
US5998256A (en) | 1996-11-01 | 1999-12-07 | Micron Technology, Inc. | Semiconductor processing methods of forming devices on a substrate, forming device arrays on a substrate, forming conductive lines on a substrate, and forming capacitor arrays on a substrate, and integrated circuitry |
US6395613B1 (en) | 2000-08-30 | 2002-05-28 | Micron Technology, Inc. | Semiconductor processing methods of forming a plurality of capacitors on a substrate, bit line contacts and method of forming bit line contacts |
US5895740A (en) | 1996-11-13 | 1999-04-20 | Vanguard International Semiconductor Corp. | Method of forming contact holes of reduced dimensions by using in-situ formed polymeric sidewall spacers |
TW365691B (en) | 1997-02-05 | 1999-08-01 | Samsung Electronics Co Ltd | Method for etching Pt film of semiconductor device |
KR100231134B1 (ko) | 1997-06-14 | 1999-11-15 | 문정환 | 반도체장치의 배선 형성 방법 |
KR200173196Y1 (ko) | 1997-06-19 | 2000-03-02 | 에릭 발리베 | 모터의 브러시홀더 |
JP3519583B2 (ja) * | 1997-09-19 | 2004-04-19 | 株式会社東芝 | 不揮発性半導体記憶装置およびその製造方法 |
US6063688A (en) | 1997-09-29 | 2000-05-16 | Intel Corporation | Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition |
KR19990027887A (ko) | 1997-09-30 | 1999-04-15 | 윤종용 | 스페이서를 이용한 반도체장치의 미세 패턴 형성방법 |
KR100247862B1 (ko) | 1997-12-11 | 2000-03-15 | 윤종용 | 반도체 장치 및 그 제조방법 |
US6143476A (en) | 1997-12-12 | 2000-11-07 | Applied Materials Inc | Method for high temperature etching of patterned layers using an organic mask stack |
US6291334B1 (en) | 1997-12-19 | 2001-09-18 | Applied Materials, Inc. | Etch stop layer for dual damascene process |
US6004862A (en) | 1998-01-20 | 1999-12-21 | Advanced Micro Devices, Inc. | Core array and periphery isolation technique |
JP2975917B2 (ja) | 1998-02-06 | 1999-11-10 | 株式会社半導体プロセス研究所 | 半導体装置の製造方法及び半導体装置の製造装置 |
US5933725A (en) | 1998-05-27 | 1999-08-03 | Vanguard International Semiconductor Corporation | Word line resistance reduction method and design for high density memory with relaxed metal pitch |
US6020255A (en) | 1998-07-13 | 2000-02-01 | Taiwan Semiconductor Manufacturing Company | Dual damascene interconnect process with borderless contact |
US6245662B1 (en) | 1998-07-23 | 2001-06-12 | Applied Materials, Inc. | Method of producing an interconnect structure for an integrated circuit |
US6071789A (en) | 1998-11-10 | 2000-06-06 | Vanguard International Semiconductor Corporation | Method for simultaneously fabricating a DRAM capacitor and metal interconnections |
FR2786776B1 (fr) * | 1998-12-07 | 2001-02-16 | Clariant France Sa | Compositions silico-acryliques, procede de preparation et application a l'obtention de revetements resistant a l'abrasion et aux rayures |
US6204187B1 (en) | 1999-01-06 | 2001-03-20 | Infineon Technologies North America, Corp. | Contact and deep trench patterning |
US6211044B1 (en) | 1999-04-12 | 2001-04-03 | Advanced Micro Devices | Process for fabricating a semiconductor device component using a selective silicidation reaction |
JP2000307084A (ja) | 1999-04-23 | 2000-11-02 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
US6110837A (en) | 1999-04-28 | 2000-08-29 | Worldwide Semiconductor Manufacturing Corp. | Method for forming a hard mask of half critical dimension |
US6136662A (en) | 1999-05-13 | 2000-10-24 | Lsi Logic Corporation | Semiconductor wafer having a layer-to-layer alignment mark and method for fabricating the same |
JP2000357736A (ja) | 1999-06-15 | 2000-12-26 | Toshiba Corp | 半導体装置及びその製造方法 |
KR100727901B1 (ko) | 1999-07-10 | 2007-06-14 | 삼성전자주식회사 | 마이크로 스케듈링 방법 및 운영체제 커널 장치 |
JP2001077196A (ja) | 1999-09-08 | 2001-03-23 | Sony Corp | 半導体装置の製造方法 |
US6362057B1 (en) | 1999-10-26 | 2002-03-26 | Motorola, Inc. | Method for forming a semiconductor device |
US6582891B1 (en) | 1999-12-02 | 2003-06-24 | Axcelis Technologies, Inc. | Process for reducing edge roughness in patterned photoresist |
US6573030B1 (en) | 2000-02-17 | 2003-06-03 | Applied Materials, Inc. | Method for depositing an amorphous carbon layer |
US6967140B2 (en) | 2000-03-01 | 2005-11-22 | Intel Corporation | Quantum wire gate device and method of making same |
US6297554B1 (en) | 2000-03-10 | 2001-10-02 | United Microelectronics Corp. | Dual damascene interconnect structure with reduced parasitic capacitance |
US6423474B1 (en) | 2000-03-21 | 2002-07-23 | Micron Technology, Inc. | Use of DARC and BARC in flash memory processing |
JP3805603B2 (ja) | 2000-05-29 | 2006-08-02 | 富士通株式会社 | 半導体装置及びその製造方法 |
US6632741B1 (en) | 2000-07-19 | 2003-10-14 | International Business Machines Corporation | Self-trimming method on looped patterns |
US6455372B1 (en) | 2000-08-14 | 2002-09-24 | Micron Technology, Inc. | Nucleation for improved flash erase characteristics |
US6348380B1 (en) | 2000-08-25 | 2002-02-19 | Micron Technology, Inc. | Use of dilute steam ambient for improvement of flash devices |
SE517275C2 (sv) | 2000-09-20 | 2002-05-21 | Obducat Ab | Sätt vid våtetsning av ett substrat |
US6335257B1 (en) | 2000-09-29 | 2002-01-01 | Vanguard International Semiconductor Corporation | Method of making pillar-type structure on semiconductor substrate |
US6667237B1 (en) | 2000-10-12 | 2003-12-23 | Vram Technologies, Llc | Method and apparatus for patterning fine dimensions |
US6534243B1 (en) | 2000-10-23 | 2003-03-18 | Advanced Micro Devices, Inc. | Chemical feature doubling process |
US6926843B2 (en) | 2000-11-30 | 2005-08-09 | International Business Machines Corporation | Etching of hard masks |
US6664028B2 (en) | 2000-12-04 | 2003-12-16 | United Microelectronics Corp. | Method of forming opening in wafer layer |
JP2002208646A (ja) * | 2001-01-10 | 2002-07-26 | Toshiba Corp | 半導体装置、半導体装置の製造方法 |
JP3406302B2 (ja) | 2001-01-16 | 2003-05-12 | 株式会社半導体先端テクノロジーズ | 微細パターンの形成方法、半導体装置の製造方法および半導体装置 |
JP2002280463A (ja) * | 2001-03-16 | 2002-09-27 | Toshiba Corp | 半導体装置及びその製造方法 |
US6740594B2 (en) | 2001-05-31 | 2004-05-25 | Infineon Technologies Ag | Method for removing carbon-containing polysilane from a semiconductor without stripping |
US6960806B2 (en) | 2001-06-21 | 2005-11-01 | International Business Machines Corporation | Double gated vertical transistor with different first and second gate materials |
US6522584B1 (en) | 2001-08-02 | 2003-02-18 | Micron Technology, Inc. | Programming methods for multi-level flash EEPROMs |
US6744094B2 (en) | 2001-08-24 | 2004-06-01 | Micron Technology Inc. | Floating gate transistor with horizontal gate layers stacked next to vertical body |
TW497138B (en) | 2001-08-28 | 2002-08-01 | Winbond Electronics Corp | Method for improving consistency of critical dimension |
DE10142590A1 (de) | 2001-08-31 | 2003-04-03 | Infineon Technologies Ag | Verfahren zur Seitenwandverstärkung von Resiststrukturen und zur Herstellung von Strukturen mit reduzierter Strukturgröße |
US7045383B2 (en) | 2001-09-19 | 2006-05-16 | BAE Systems Information and Ovonyx, Inc | Method for making tapered opening for programmable resistance memory element |
JP2003133437A (ja) | 2001-10-24 | 2003-05-09 | Hitachi Ltd | 半導体装置の製造方法および半導体装置 |
US7226853B2 (en) | 2001-12-26 | 2007-06-05 | Applied Materials, Inc. | Method of forming a dual damascene structure utilizing a three layer hard mask structure |
TW576864B (en) | 2001-12-28 | 2004-02-21 | Toshiba Corp | Method for manufacturing a light-emitting device |
US6638441B2 (en) | 2002-01-07 | 2003-10-28 | Macronix International Co., Ltd. | Method for pitch reduction |
DE10204688C1 (de) | 2002-02-06 | 2003-10-09 | Infineon Technologies Ag | Speicherbaustein mit verbesserten elektrischen Eigenschaften |
DE10207131B4 (de) | 2002-02-20 | 2007-12-20 | Infineon Technologies Ag | Verfahren zur Bildung einer Hartmaske in einer Schicht auf einer flachen Scheibe |
US6620715B1 (en) | 2002-03-29 | 2003-09-16 | Cypress Semiconductor Corp. | Method for forming sub-critical dimension structures in an integrated circuit |
JP2003297957A (ja) * | 2002-04-05 | 2003-10-17 | Mitsubishi Electric Corp | 半導体装置及び半導体装置の製造方法 |
US6759180B2 (en) | 2002-04-23 | 2004-07-06 | Hewlett-Packard Development Company, L.P. | Method of fabricating sub-lithographic sized line and space patterns for nano-imprinting lithography |
US6992925B2 (en) | 2002-04-26 | 2006-01-31 | Kilopass Technologies, Inc. | High density semiconductor memory cell and memory array using a single transistor and having counter-doped poly and buried diffusion wordline |
US20030207584A1 (en) | 2002-05-01 | 2003-11-06 | Swaminathan Sivakumar | Patterning tighter and looser pitch geometries |
US6951709B2 (en) | 2002-05-03 | 2005-10-04 | Micron Technology, Inc. | Method of fabricating a semiconductor multilevel interconnect structure |
US6602779B1 (en) | 2002-05-13 | 2003-08-05 | Taiwan Semiconductor Manufacturing Co., Ltd | Method for forming low dielectric constant damascene structure while employing carbon doped silicon oxide planarizing stop layer |
US6703312B2 (en) | 2002-05-17 | 2004-03-09 | International Business Machines Corporation | Method of forming active devices of different gatelengths using lithographic printed gate images of same length |
US6818141B1 (en) | 2002-06-10 | 2004-11-16 | Advanced Micro Devices, Inc. | Application of the CVD bilayer ARC as a hard mask for definition of the subresolution trench features between polysilicon wordlines |
US6548385B1 (en) | 2002-06-12 | 2003-04-15 | Jiun-Ren Lai | Method for reducing pitch between conductive features, and structure formed using the method |
US6734107B2 (en) | 2002-06-12 | 2004-05-11 | Macronix International Co., Ltd. | Pitch reduction in semiconductor fabrication |
US6559017B1 (en) | 2002-06-13 | 2003-05-06 | Advanced Micro Devices, Inc. | Method of using amorphous carbon as spacer material in a disposable spacer process |
KR100476924B1 (ko) | 2002-06-14 | 2005-03-17 | 삼성전자주식회사 | 반도체 장치의 미세 패턴 형성 방법 |
US6924191B2 (en) | 2002-06-20 | 2005-08-02 | Applied Materials, Inc. | Method for fabricating a gate structure of a field effect transistor |
WO2004003977A2 (en) | 2002-06-27 | 2004-01-08 | Advanced Micro Devices, Inc. | Method of defining the dimensions of circuit elements by using spacer deposition techniques |
US6835663B2 (en) | 2002-06-28 | 2004-12-28 | Infineon Technologies Ag | Hardmask of amorphous carbon-hydrogen (a-C:H) layers with tunable etch resistivity |
US6500756B1 (en) | 2002-06-28 | 2002-12-31 | Advanced Micro Devices, Inc. | Method of forming sub-lithographic spaces between polysilicon lines |
US6689695B1 (en) | 2002-06-28 | 2004-02-10 | Taiwan Semiconductor Manufacturing Company | Multi-purpose composite mask for dual damascene patterning |
US20040018738A1 (en) | 2002-07-22 | 2004-01-29 | Wei Liu | Method for fabricating a notch gate structure of a field effect transistor |
US6913871B2 (en) | 2002-07-23 | 2005-07-05 | Intel Corporation | Fabricating sub-resolution structures in planar lightwave devices |
US6673684B1 (en) | 2002-07-31 | 2004-01-06 | Advanced Micro Devices, Inc. | Use of diamond as a hard mask material |
US6800930B2 (en) | 2002-07-31 | 2004-10-05 | Micron Technology, Inc. | Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies |
US6764949B2 (en) | 2002-07-31 | 2004-07-20 | Advanced Micro Devices, Inc. | Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication |
US6939808B2 (en) | 2002-08-02 | 2005-09-06 | Applied Materials, Inc. | Undoped and fluorinated amorphous carbon film as pattern mask for metal etch |
KR100480610B1 (ko) | 2002-08-09 | 2005-03-31 | 삼성전자주식회사 | 실리콘 산화막을 이용한 미세 패턴 형성방법 |
US7358121B2 (en) * | 2002-08-23 | 2008-04-15 | Intel Corporation | Tri-gate devices and methods of fabrication |
US6566280B1 (en) | 2002-08-26 | 2003-05-20 | Intel Corporation | Forming polymer features on a substrate |
US6756284B2 (en) | 2002-09-18 | 2004-06-29 | Silicon Storage Technology, Inc. | Method for forming a sublithographic opening in a semiconductor process |
US6706571B1 (en) | 2002-10-22 | 2004-03-16 | Advanced Micro Devices, Inc. | Method for forming multiple structures in a semiconductor device |
JP4034164B2 (ja) | 2002-10-28 | 2008-01-16 | 富士通株式会社 | 微細パターンの作製方法及び半導体装置の製造方法 |
US6888755B2 (en) | 2002-10-28 | 2005-05-03 | Sandisk Corporation | Flash memory cell arrays having dual control gates per memory cell charge storage element |
US7119020B2 (en) | 2002-12-04 | 2006-10-10 | Matsushita Electric Industrial Co., Ltd. | Method for fabricating semiconductor device |
US6686245B1 (en) | 2002-12-20 | 2004-02-03 | Motorola, Inc. | Vertical MOSFET with asymmetric gate structure |
US6916594B2 (en) | 2002-12-30 | 2005-07-12 | Hynix Semiconductor Inc. | Overcoating composition for photoresist and method for forming photoresist pattern using the same |
US7015124B1 (en) | 2003-04-28 | 2006-03-21 | Advanced Micro Devices, Inc. | Use of amorphous carbon for gate patterning |
US6773998B1 (en) | 2003-05-20 | 2004-08-10 | Advanced Micro Devices, Inc. | Modified film stack and patterning strategy for stress compensation and prevention of pattern distortion in amorphous carbon gate patterning |
JP4578785B2 (ja) | 2003-05-21 | 2010-11-10 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US6835662B1 (en) | 2003-07-14 | 2004-12-28 | Advanced Micro Devices, Inc. | Partially de-coupled core and periphery gate module process |
US7105431B2 (en) | 2003-08-22 | 2006-09-12 | Micron Technology, Inc. | Masking methods |
DE10345455A1 (de) | 2003-09-30 | 2005-05-04 | Infineon Technologies Ag | Verfahren zum Erzeugen einer Hartmaske und Hartmasken-Anordnung |
KR100536801B1 (ko) | 2003-10-01 | 2005-12-14 | 동부아남반도체 주식회사 | 반도체 소자 및 그 제조 방법 |
US6867116B1 (en) | 2003-11-10 | 2005-03-15 | Macronix International Co., Ltd. | Fabrication method of sub-resolution pitch for integrated circuits |
JP2005150333A (ja) | 2003-11-14 | 2005-06-09 | Sony Corp | 半導体装置の製造方法 |
US7049651B2 (en) | 2003-11-17 | 2006-05-23 | Infineon Technologies Ag | Charge-trapping memory device including high permittivity strips |
TWI274397B (en) | 2003-11-20 | 2007-02-21 | Winbond Electronics Corp | Method for forming narrow trench structure and method for forming gate structure with narrow spacing |
KR101002928B1 (ko) | 2003-11-29 | 2010-12-27 | 주식회사 하이닉스반도체 | 반도체 소자의 미세 라인 형성방법 |
KR100554514B1 (ko) | 2003-12-26 | 2006-03-03 | 삼성전자주식회사 | 반도체 장치에서 패턴 형성 방법 및 이를 이용한 게이트형성방법. |
US6998332B2 (en) | 2004-01-08 | 2006-02-14 | International Business Machines Corporation | Method of independent P and N gate length control of FET device made by sidewall image transfer technique |
US6875703B1 (en) | 2004-01-20 | 2005-04-05 | International Business Machines Corporation | Method for forming quadruple density sidewall image transfer (SIT) structures |
US7064078B2 (en) | 2004-01-30 | 2006-06-20 | Applied Materials | Techniques for the use of amorphous carbon (APF) for various etch and litho integration scheme |
US8486287B2 (en) | 2004-03-19 | 2013-07-16 | The Regents Of The University Of California | Methods for fabrication of positional and compositionally controlled nanostructures on substrate |
KR100546409B1 (ko) | 2004-05-11 | 2006-01-26 | 삼성전자주식회사 | 리세스 채널을 구비한 2-비트 소노스형 메모리 셀 및 그제조방법 |
US7098105B2 (en) | 2004-05-26 | 2006-08-29 | Micron Technology, Inc. | Methods for forming semiconductor structures |
US6955961B1 (en) | 2004-05-27 | 2005-10-18 | Macronix International Co., Ltd. | Method for defining a minimum pitch in an integrated circuit beyond photolithographic resolution |
US7183205B2 (en) | 2004-06-08 | 2007-02-27 | Macronix International Co., Ltd. | Method of pitch dimension shrinkage |
KR100594282B1 (ko) | 2004-06-28 | 2006-06-30 | 삼성전자주식회사 | FinFET을 포함하는 반도체 소자 및 그 제조방법 |
US7473644B2 (en) | 2004-07-01 | 2009-01-06 | Micron Technology, Inc. | Method for forming controlled geometry hardmasks including subresolution elements |
US7074666B2 (en) | 2004-07-28 | 2006-07-11 | International Business Machines Corporation | Borderless contact structures |
KR100704470B1 (ko) | 2004-07-29 | 2007-04-10 | 주식회사 하이닉스반도체 | 비결정성 탄소막을 희생 하드마스크로 이용하는반도체소자 제조 방법 |
US7151040B2 (en) | 2004-08-31 | 2006-12-19 | Micron Technology, Inc. | Methods for increasing photo alignment margins |
US7175944B2 (en) | 2004-08-31 | 2007-02-13 | Micron Technology, Inc. | Prevention of photoresist scumming |
US7910288B2 (en) | 2004-09-01 | 2011-03-22 | Micron Technology, Inc. | Mask material conversion |
US7442976B2 (en) | 2004-09-01 | 2008-10-28 | Micron Technology, Inc. | DRAM cells with vertical transistors |
US7655387B2 (en) | 2004-09-02 | 2010-02-02 | Micron Technology, Inc. | Method to align mask patterns |
US7115525B2 (en) | 2004-09-02 | 2006-10-03 | Micron Technology, Inc. | Method for integrated circuit fabrication using pitch multiplication |
KR100614651B1 (ko) | 2004-10-11 | 2006-08-22 | 삼성전자주식회사 | 회로 패턴의 노광을 위한 장치 및 방법, 사용되는포토마스크 및 그 설계 방법, 그리고 조명계 및 그 구현방법 |
US7381615B2 (en) | 2004-11-23 | 2008-06-03 | Sandisk Corporation | Methods for self-aligned trench filling with grown dielectric for high coupling ratio in semiconductor devices |
US7208379B2 (en) | 2004-11-29 | 2007-04-24 | Texas Instruments Incorporated | Pitch multiplication process |
US7298004B2 (en) * | 2004-11-30 | 2007-11-20 | Infineon Technologies Ag | Charge-trapping memory cell and method for production |
KR100596795B1 (ko) | 2004-12-16 | 2006-07-05 | 주식회사 하이닉스반도체 | 반도체 소자의 캐패시터 및 그 형성방법 |
WO2006070474A1 (ja) * | 2004-12-28 | 2006-07-06 | Spansion Llc | 半導体装置の製造方法 |
US7183142B2 (en) | 2005-01-13 | 2007-02-27 | International Business Machines Corporation | FinFETs with long gate length at high density |
US7271107B2 (en) | 2005-02-03 | 2007-09-18 | Lam Research Corporation | Reduction of feature critical dimensions using multiple masks |
KR100787352B1 (ko) | 2005-02-23 | 2007-12-18 | 주식회사 하이닉스반도체 | 하드마스크용 조성물 및 이를 이용한 반도체 소자의 패턴형성 방법 |
JP2006237196A (ja) | 2005-02-24 | 2006-09-07 | Matsushita Electric Ind Co Ltd | 半導体記憶装置 |
US7390746B2 (en) | 2005-03-15 | 2008-06-24 | Micron Technology, Inc. | Multiple deposition for integration of spacers in pitch multiplication process |
US7253118B2 (en) | 2005-03-15 | 2007-08-07 | Micron Technology, Inc. | Pitch reduced patterns relative to photolithography features |
CN100555579C (zh) | 2005-03-28 | 2009-10-28 | 美光科技公司 | 集成电路制造 |
US7611944B2 (en) | 2005-03-28 | 2009-11-03 | Micron Technology, Inc. | Integrated circuit fabrication |
KR100640639B1 (ko) | 2005-04-19 | 2006-10-31 | 삼성전자주식회사 | 미세콘택을 포함하는 반도체소자 및 그 제조방법 |
KR100674970B1 (ko) | 2005-04-21 | 2007-01-26 | 삼성전자주식회사 | 이중 스페이서들을 이용한 미세 피치의 패턴 형성 방법 |
US7429536B2 (en) | 2005-05-23 | 2008-09-30 | Micron Technology, Inc. | Methods for forming arrays of small, closely spaced features |
US7547599B2 (en) | 2005-05-26 | 2009-06-16 | Micron Technology, Inc. | Multi-state memory cell |
US7560390B2 (en) | 2005-06-02 | 2009-07-14 | Micron Technology, Inc. | Multiple spacer steps for pitch multiplication |
US7396781B2 (en) | 2005-06-09 | 2008-07-08 | Micron Technology, Inc. | Method and apparatus for adjusting feature size and position |
JP2006351861A (ja) | 2005-06-16 | 2006-12-28 | Toshiba Corp | 半導体装置の製造方法 |
US7279375B2 (en) * | 2005-06-30 | 2007-10-09 | Intel Corporation | Block contact architectures for nanoscale channel transistors |
JP2007035957A (ja) * | 2005-07-27 | 2007-02-08 | Toshiba Corp | 半導体装置とその製造方法 |
US7413981B2 (en) | 2005-07-29 | 2008-08-19 | Micron Technology, Inc. | Pitch doubled circuit layout |
US7291560B2 (en) | 2005-08-01 | 2007-11-06 | Infineon Technologies Ag | Method of production pitch fractionizations in semiconductor technology |
US7816262B2 (en) | 2005-08-30 | 2010-10-19 | Micron Technology, Inc. | Method and algorithm for random half pitched interconnect layout with constant spacing |
US7829262B2 (en) | 2005-08-31 | 2010-11-09 | Micron Technology, Inc. | Method of forming pitch multipled contacts |
US7325215B2 (en) | 2005-08-31 | 2008-01-29 | Lsi Logic Corporation | Timing violation debugging inside place and route tool |
US7572572B2 (en) | 2005-09-01 | 2009-08-11 | Micron Technology, Inc. | Methods for forming arrays of small, closely spaced features |
US7759197B2 (en) | 2005-09-01 | 2010-07-20 | Micron Technology, Inc. | Method of forming isolated features using pitch multiplication |
US7687342B2 (en) | 2005-09-01 | 2010-03-30 | Micron Technology, Inc. | Method of manufacturing a memory device |
US7393789B2 (en) | 2005-09-01 | 2008-07-01 | Micron Technology, Inc. | Protective coating for planarization |
US7776744B2 (en) | 2005-09-01 | 2010-08-17 | Micron Technology, Inc. | Pitch multiplication spacers and methods of forming the same |
KR100842576B1 (ko) * | 2005-09-08 | 2008-07-01 | 삼성전자주식회사 | 휴대 단말기의 안테나 장치 |
US7294888B1 (en) | 2005-09-30 | 2007-11-13 | Xilinx, Inc. | CMOS-compatible non-volatile memory cell with lateral inter-poly programming layer |
KR101200938B1 (ko) | 2005-09-30 | 2012-11-13 | 삼성전자주식회사 | 반도체 장치의 패턴 형성 방법 |
US7244638B2 (en) * | 2005-09-30 | 2007-07-17 | Infineon Technologies Ag | Semiconductor memory device and method of production |
US7271063B2 (en) | 2005-10-13 | 2007-09-18 | Elite Semiconductor Memory Technology, Inc. | Method of forming FLASH cell array having reduced word line pitch |
KR100714305B1 (ko) | 2005-12-26 | 2007-05-02 | 삼성전자주식회사 | 자기정렬 이중패턴의 형성방법 |
KR100672123B1 (ko) | 2006-02-02 | 2007-01-19 | 주식회사 하이닉스반도체 | 반도체 소자의 미세 패턴 형성방법 |
US20070190762A1 (en) | 2006-02-13 | 2007-08-16 | Asml Netherlands B.V. | Device manufacturing method and computer program product |
US7842558B2 (en) | 2006-03-02 | 2010-11-30 | Micron Technology, Inc. | Masking process for simultaneously patterning separate regions |
US20070210449A1 (en) | 2006-03-07 | 2007-09-13 | Dirk Caspary | Memory device and an array of conductive lines and methods of making the same |
US7351666B2 (en) | 2006-03-17 | 2008-04-01 | International Business Machines Corporation | Layout and process to contact sub-lithographic structures |
JP2007273859A (ja) * | 2006-03-31 | 2007-10-18 | Renesas Technology Corp | 半導体装置およびその製造方法 |
US7902074B2 (en) | 2006-04-07 | 2011-03-08 | Micron Technology, Inc. | Simplified pitch doubling process flow |
US8003310B2 (en) | 2006-04-24 | 2011-08-23 | Micron Technology, Inc. | Masking techniques and templates for dense semiconductor fabrication |
US7488685B2 (en) | 2006-04-25 | 2009-02-10 | Micron Technology, Inc. | Process for improving critical dimension uniformity of integrated circuit arrays |
US7537866B2 (en) | 2006-05-24 | 2009-05-26 | Synopsys, Inc. | Patterning a single integrated circuit layer using multiple masks and multiple masking layers |
US7795149B2 (en) | 2006-06-01 | 2010-09-14 | Micron Technology, Inc. | Masking techniques and contact imprint reticles for dense semiconductor fabrication |
KR100763538B1 (ko) | 2006-08-29 | 2007-10-05 | 삼성전자주식회사 | 마스크 패턴의 형성 방법 및 이를 이용한 미세 패턴의 형성방법 |
US7611980B2 (en) | 2006-08-30 | 2009-11-03 | Micron Technology, Inc. | Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures |
US7825460B2 (en) | 2006-09-06 | 2010-11-02 | International Business Machines Corporation | Vertical field effect transistor arrays and methods for fabrication thereof |
US7666578B2 (en) | 2006-09-14 | 2010-02-23 | Micron Technology, Inc. | Efficient pitch multiplication process |
KR100790998B1 (ko) | 2006-10-02 | 2008-01-03 | 삼성전자주식회사 | 셀프 얼라인 더블 패터닝법을 사용한 패드 패턴 형성 방법 및 셀프 얼라인 더블 패터닝법을 사용한 콘택홀 형성방법 |
US8129289B2 (en) | 2006-10-05 | 2012-03-06 | Micron Technology, Inc. | Method to deposit conformal low temperature SiO2 |
US7838948B2 (en) * | 2007-01-30 | 2010-11-23 | Infineon Technologies Ag | Fin interconnects for multigate FET circuit blocks |
JP4950702B2 (ja) * | 2007-03-01 | 2012-06-13 | 株式会社東芝 | 半導体記憶装置の製造方法 |
US20080292991A1 (en) | 2007-05-24 | 2008-11-27 | Advanced Micro Devices, Inc. | High fidelity multiple resist patterning |
US7923373B2 (en) | 2007-06-04 | 2011-04-12 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
US8563229B2 (en) | 2007-07-31 | 2013-10-22 | Micron Technology, Inc. | Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures |
JP2009054956A (ja) * | 2007-08-29 | 2009-03-12 | Toshiba Corp | 半導体メモリ |
EP2201149B1 (en) | 2007-09-14 | 2013-03-13 | Sigma-Aldrich Co. | Methods of preparing titanium containing thin films by atomic layer deposition using monocyclopentadienyl titanium-based precursors |
US7737039B2 (en) | 2007-11-01 | 2010-06-15 | Micron Technology, Inc. | Spacer process for on pitch contacts and related structures |
US7851135B2 (en) | 2007-11-30 | 2010-12-14 | Hynix Semiconductor Inc. | Method of forming an etching mask pattern from developed negative and positive photoresist layers |
US7659208B2 (en) | 2007-12-06 | 2010-02-09 | Micron Technology, Inc | Method for forming high density patterns |
US7790531B2 (en) * | 2007-12-18 | 2010-09-07 | Micron Technology, Inc. | Methods for isolating portions of a loop of pitch-multiplied material and related structures |
DE102008007029B4 (de) * | 2008-01-31 | 2014-07-03 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Betrieb einer elektronischen Schaltung mit körpergesteuertem Doppelkanaltransistor und SRAM-Zelle mit körpergesteuertem Doppelkanaltransistor |
US8884966B2 (en) | 2011-08-24 | 2014-11-11 | Hewlett-Packard Development Company, L.P. | Visualizing a scatter plot using real-time backward rewrite |
JP5806974B2 (ja) | 2012-05-17 | 2015-11-10 | 日本電信電話株式会社 | 近隣情報検索装置及び方法及びプログラム |
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