CN109844905B - 减小通孔至栅格图案化中的套准误差的方法 - Google Patents

减小通孔至栅格图案化中的套准误差的方法 Download PDF

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CN109844905B
CN109844905B CN201780064602.5A CN201780064602A CN109844905B CN 109844905 B CN109844905 B CN 109844905B CN 201780064602 A CN201780064602 A CN 201780064602A CN 109844905 B CN109844905 B CN 109844905B
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尼哈尔·莫汉蒂
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Abstract

本文中的技术包括使基底图案化的方法，所述方法通过使用多种不同材料使用基于自对准的工艺将通孔对准至奇和偶沟槽。本文中的方法使通孔图案分解或分离成间隔物侧通孔和芯轴侧通孔，然后分别顺序到达间隔物侧和芯轴侧。利用这样的技术，显著提高了通孔向栅格的套准。通过使用沟槽记忆层下面的另外的记忆层并且独立地到达沟槽图案的中间的芯轴侧和间隔物侧，实现了通孔对准的显著改善。

Description

减小通孔至栅格图案化中的套准误差的方法
相关申请的交叉引用
本申请要求于2016年10月20日提交的题为“Method of Reducing Overlay Errorin Via to Grid Patterning”的美国临时专利申请第62/410,811号的权益，其全部内容通过引用并入本文。
背景技术
本公开内容涉及包括基底(例如半导体晶片)的处理的半导体制造。
发明内容
半导体器件正在不断地按比例缩小以便基底的每单位面积安装更多个器件。本文中的技术解决通孔图案化所面临的问题，并且这个问题是通孔向栅格套准提高。在高级节点处，当BEOL(back-end-of-line，后段制程)沟槽图案化低于30nm节距时，在奇和偶沟槽之间对准通孔掩模成为挑战。本文中的技术使用基于自对准的工艺通过使用多种不同材料和记忆层而将通孔对准至奇和偶沟槽。
技术包括使基底图案化的方法。在基底的目标层上形成第一记忆层。在第一记忆层上形成第二记忆层。在第二记忆层上方形成多线层。多线层包括具有两种或更多种不同材料的交替线的图案的区域。每条线具有水平厚度、垂直高度并且延伸穿过基底。交替线的图案的每条线形成多线层的顶表面的一部分并且垂直地延伸至多线层的底表面。两种或更多种不同材料中的至少两者通过具有相对于彼此不同的抗蚀刻性而在化学上彼此不同。在多线层上形成第一蚀刻掩模。进行第一蚀刻工艺，所述第一蚀刻工艺使用第一蚀刻掩模和多线层的一种或更多种材料作为第一组合蚀刻掩模来蚀刻到第二记忆层中。在多线层上形成第二蚀刻掩模。进行第二蚀刻工艺，所述第二蚀刻工艺使用第二蚀刻掩模和多线层的一种或更多种材料作为第二组合蚀刻掩模来蚀刻到第二记忆层中。
当然，为了清楚起见，已经呈现了本文描述的不同步骤的讨论顺序。通常，这些步骤可以以任何合适的顺序进行。另外，虽然本文中各个不同的特征、技术、配置等可以在本公开内容的不同地方论述，但是旨在可以彼此独立地或者彼此组合地进行各个构思。因此，本发明可以以许多不同的方式进行实施和观察。
注意，该发明内容部分没有详细说明本公开内容或要求保护的发明的每一个实施方案和/或增加的新方面。相反，本发明内容仅提供了相比于常规技术的不同实施方案和对应的新颖性的要点的初步讨论。对于本发明和实施方案的另外的细节和/或可能的观点，请读者参照如下进一步讨论的本公开内容的具体实施方案部分和对应的附图。
附图说明
参照结合附图考虑的以下详细描述，本发明的各种实施方案的更完整的理解及其许多随之而来的优点将容易变得明显。附图不一定按比例绘制，而是着重于说明特征、原理和构思。
图1是示出根据本文所公开的实施方案的工艺流程的示例基底区段的截面示意性侧视图。
图2是示出根据本文所公开的实施方案的工艺流程的示例基底区段的截面示意性侧视图。
图3是示出根据本文所公开的实施方案的工艺流程的示例基底区段的截面示意性侧视图。
图4是示出根据本文所公开的实施方案的工艺流程的示例基底区段的截面示意性侧视图。
图5是示出根据本文所公开的实施方案的工艺流程的示例基底区段的截面示意性侧视图。
图6是示出根据本文所公开的实施方案的工艺流程的示例基底区段的截面示意性侧视图。
图7是示出根据本文所公开的实施方案的工艺流程的示例基底区段的截面示意性侧视图。
图8是示出根据本文所公开的实施方案的工艺流程的示例基底区段的截面示意性侧视图。
图9是示出根据本文所公开的实施方案的工艺流程的示例基底区段的截面示意性侧视图。
图10是示出根据本文所公开的实施方案的工艺流程的示例基底区段的截面示意性侧视图。
图11是示出根据本文所公开的实施方案的工艺流程的示例基底区段的截面示意性侧视图。
图12是示出根据本文所公开的实施方案的工艺流程的示例基底区段的截面示意性侧视图。
图13是示出根据本文所公开的实施方案的工艺流程的示例基底区段的截面示意性侧视图。
图14是示出根据本文所公开的实施方案的工艺流程的示例基底区段的截面示意性侧视图。
图15是示出根据本文所公开的实施方案的工艺流程的示例基底区段的截面示意性侧视图。
图16是示出根据本文所公开的实施方案的工艺流程的示例基底区段的截面示意性侧视图。
图17是示出根据本文所公开的实施方案的工艺流程的示例基底区段的截面示意性侧视图。
图18是示出根据本文所公开的实施方案的工艺流程的示例基底区段的截面示意性侧视图。
具体实施方式
本文中的技术包括使基底图案化的方法，该方法通过使用多种不同材料使用基于自对准的工艺将通孔对准至奇和偶沟槽。可以将示例实施方案应用至双图案化栅格例如SAQP(自对准四重图案化)栅格或SADP(自对准双图案化)栅格以及其他图案化方案。本文中的方法使通孔图案分解或分离成间隔物侧通孔和芯轴侧通孔，然后分别顺序到达间隔物侧和芯轴侧。利用这样的技术，显著提高了通孔向栅格的套准。通过使用沟槽记忆层下面的另外的记忆层并且独立地到达沟槽图案的中间的芯轴侧和间隔物侧，实现了通孔对准的显著改善。
现在参照图1，在基底100的目标层107上形成第一记忆层111。在第一记忆层111上形成第二记忆层112。可以使用多种材料。在一个示例中，第一记忆层111可以是用于通孔记忆的氮化硅，而第二记忆层112可以是用于沟槽记忆的氮化钛。在第二记忆层112上可以形成中间层115。中间层115是任选的。
在第二记忆层112上方形成多线层121。多线层121可以形成在第二记忆层112上或形成在中间层115上。多线层121包括具有两种或更多种不同材料的交替线的图案的区域。每条线具有水平厚度、垂直高度，并且延伸穿过基底。交替线的图案的每条线形成多线层121的顶表面的一部分并且垂直地延伸至多线层121的底表面。两种或更多种不同材料中的至少两者通过具有相对于彼此不同的抗蚀刻性而在化学上彼此不同。
在一些实施方案中，多线层121包括芯轴131和形成在芯轴131的侧壁上的侧壁间隔物132。侧壁间隔物132具有芯轴侧136和间隔物侧137。芯轴侧136接触相应的芯轴。侧壁间隔物限定相邻侧壁间隔物的间隔物侧之间的开放空间。换句话说，在相邻侧壁间隔物的间隔物侧之间存在开放空间。
两种或更多种不同材料的交替线的图案可以包括A-B-C-B-A-B-C-B的重复序列，其中材料A和材料B具有相对于彼此不同的抗蚀刻性。在一个示例中，芯轴131可以是材料A，而侧壁间隔物是材料B。材料C可以是第三材料或可以是如图所示的开放空间。
在一些实施方案中，芯轴可以形成为两种材料的复合物，所述复合物具有上芯轴层145和下芯轴层144。中间层115和上芯轴层145可以由相同的材料构成。上芯轴层145的垂直厚度可以大于中间层115的垂直厚度。
现在参考图2，可以在多线层121中的开放空间内的预定位置处形成插塞163(或多个插塞)。作为非限制性示例，这样的插塞可以通过氧化钛的原子层沉积来形成。插塞掩模可以用于沉积。形成插塞是任选的，但根据所选择使用的材料和这些材料的抗蚀刻性可以是有益的。或者，可以在多线层121中使用第三材料线。
可以进行这样的蚀刻工艺，其使用多线层121(和任意插塞)作为蚀刻掩模来蚀刻到第二记忆层112中(图3)。具有与中间层115相比更厚的上芯轴层145在能够蚀刻穿过中间层115的同时有助于保留芯轴帽。
在多线层121上形成第一蚀刻掩模151。图4和图5示出示例结果。进行第一蚀刻工艺，其使用第一蚀刻掩模151和多线层121的一种或更多种材料作为第一组合蚀刻掩模来蚀刻到第一记忆层111中(图6)。在一个示例中，第一蚀刻掩模可以包括用于使通孔图案化的狭槽开口。
然后可以去除第一蚀刻掩模151(图7)。任选地，可以在由第一蚀刻工艺创建的开口中形成插塞164(图8)。这样的插塞可以是例如氧化锆。
在图9中，从多线层121中去除芯轴131。在图10中，进行这样的蚀刻工艺，其使用多线层121的剩余材料作为蚀刻掩模来蚀刻第二记忆层112。
在多线层上形成第二蚀刻掩模152(图11)。进行第二蚀刻工艺，其使用第二蚀刻掩模152和多线层121的一种或更多种材料作为第二组合蚀刻掩模来蚀刻到第一记忆层111中(图12)。注意，可以蚀刻多线层材料中的一种或更多种，或多线层可以已经具有开口(特别是当存在与三条或更多条材料线相比的两条材料线加上空间时)并因此不需要蚀刻多线层中的一条或更多条线。一条或更多条线可以在形成任何蚀刻掩模之前在前面的步骤中蚀刻或者在形成给定蚀刻掩模之后蚀刻。
可以将第一蚀刻掩模、第二蚀刻掩模和多线层全部去除(图13和图14)。可以根据期望的工艺流程在前面的步骤中去除第一蚀刻掩模。基底现在具有记忆在第一记忆层111和第二记忆层112中的图案。进行这样的蚀刻工艺，其将由第一记忆层限定的第一记忆层图案转移到目标层中(图15)。接下来，可以进行这样的蚀刻工艺，其将由第二记忆层限定的第二记忆层图案转移到目标层中(图16和图17)。注意，在目标层107是一种材料的情况下，当将第二记忆层图案转移到目标层107中时，使用第一记忆层图案已经蚀刻的特征或开口将被蚀刻得更深。
因此，可以将通孔和沟槽都蚀刻到目标层107中。图18将记忆层去除并且将通孔171和沟槽172图案化到目标层中。另一个优点是可以利用狭槽开口使通孔开口图案化并且通过多线层和双记忆层的蚀刻选择性来使通孔开口变窄至方形或圆形开口，所述双记忆层具有与多线层的线垂直交叉的狭槽开口。这样的技术可以提高产量并且减小边缘放置误差。注意，多种工艺流程可以与多线层下方的双记忆层一起使用。例如，可以首先或其次使两个记忆层中的任一个图案化。可以使用多线层和/或各种蚀刻掩模在各个阶段使记忆层图案化。结果是两种图案在自对准的情况下被记忆并且可以用于使金属化用的沟槽和通孔准确地图案化。
在前面的描述中，已经陈述了具体细节，例如处理系统的特定几何形状以及对其中使用的各种部件和处理的描述。然而，应当理解，本文中的技术可以在脱离这些具体细节的其他实施方案中实施，并且这些细节是为了说明而不是限制的目的。已经参照附图描述了本文公开的实施方案。类似地，出于说明的目的，已经陈述了具体的数字、材料和配置，以便提供透彻的理解。然而，可以在没有这样的具体细节的情况下实行实施方案。具有基本上相同的功能构造的部件由相同的附图标记表示，因而可以省略任何多余的描述。
已经将各种技术描述为多个单独操作，以帮助理解各种实施方案。描述的顺序不应被解释为意味着这些操作一定是顺序相关的。实际上，这些操作不需要按照呈现的顺序进行。可以以与所描述的实施方案不同的顺序来进行所描述的操作。在另外的实施方案中，可以进行各种另外的操作和/或可以省略所描述的操作。
如本文中使用的“基底”或“目标基底”一般是指根据本发明正在处理的对象。基底可以包括器件特别是半导体或其他电子器件的任何材料部分或结构，并且可以例如是基础基底结构，例如半导体晶片、光罩或者在基础基底结构(例如薄膜)上或覆盖基础基底结构的层。因此，基底不限于图案化或未图案化的任何特定的基础结构、下层或覆层，而是预期包括任何这样的层或基础结构以及层和/或基础结构的任意组合。描述可能参照特定类型的基底，但这仅仅是为了说明性目的。
本领域技术人员还应理解，可以对以上说明的技术的操作做出许多改变但仍实现本发明的相同目的。这些变化旨在被本公开内容的范围所涵盖。如此，本发明的实施方案的前述描述并非旨在限制。相反，对本发明的实施方案的任何限制均呈现在权利要求书中。

Claims (15)

1.一种使基底图案化的方法，所述方法包括：
在基底的目标层上形成第一记忆层；
在所述第一记忆层上形成第二记忆层；
在所述第二记忆层上方形成多线层，所述多线层包括具有两种或更多种不同材料的交替线的图案的区域，其中每条线具有水平厚度、垂直高度并且延伸穿过所述基底，其中所述交替线的图案的每条线形成所述多线层的顶表面的一部分并且垂直地延伸至所述多线层的底表面，其中所述两种或更多种不同材料中的至少两者通过具有相对于彼此不同的抗蚀刻性而在化学上彼此不同；
在所述多线层上形成第一蚀刻掩模以及进行第一蚀刻工艺，所述第一蚀刻工艺使用所述第一蚀刻掩模和所述多线层的一种或更多种材料作为第一组合蚀刻掩模来蚀刻到所述第一记忆层中；以及
在执行所述第一蚀刻工艺之后，从所述多线层去除特定材料，以及将由所述多线层限定的图案转移到所述第一记忆层中；以及
在将由所述多线层限定的所述图案转移到所述第一记忆层中之后，在所述多线层上形成第二蚀刻掩模以及进行第二蚀刻工艺，所述第二蚀刻工艺使用所述第二蚀刻掩模和所述多线层的一种或更多种材料作为第二组合蚀刻掩模来蚀刻到所述第一记忆层中。
2.根据权利要求1所述的方法，还包括：
去除所述第一蚀刻掩模、所述第二蚀刻掩模和所述多线层；
将由所述第一记忆层限定的第一记忆层图案转移到所述目标层中；以及
将由所述第二记忆层限定的第二记忆层图案转移到所述目标层中。
3.根据权利要求2所述的方法，其中所述目标层包括介电材料；
其中所述第一记忆层图案限定通孔；以及
其中所述第二记忆层图案限定沟槽。
4.根据权利要求2所述的方法，其中所述多线层包括芯轴和形成在所述芯轴的侧壁上的侧壁间隔物，所述侧壁间隔物具有芯轴侧和间隔物侧，其中所述芯轴侧接触相应的芯轴，所述侧壁间隔物限定相邻侧壁间隔物的间隔物侧之间的开放空间。
5.根据权利要求2所述的方法，其中所述两种或更多种不同材料的交替线的图案包括A-B-C-B-A-B-C-B的重复序列，其中材料A和材料B具有相对于彼此不同的抗蚀刻性。
6.根据权利要求4所述的方法，还包括在所述第二记忆层与所述多线层之间的中间层。
7.根据权利要求6所述的方法，其中所述芯轴形成为两种材料的复合物，所述复合物具有上芯轴层和下芯轴层。
8.根据权利要求7所述的方法，其中所述中间层和所述上芯轴层包含相同的材料，以及其中所述上芯轴层的垂直厚度大于所述中间层的垂直厚度。
9.根据权利要求4所述的方法，还包括：
在形成所述第一蚀刻掩模之前，在所述多线层中的开放空间内的预定位置处形成插塞。
10.根据权利要求9所述的方法，还包括：
在进行所述第一蚀刻工艺之后并且在形成所述第二蚀刻掩模之前，在所述多线层中的开放空间内的露出位置处形成插塞。
11.根据权利要求2所述的方法，其中在形成所述第二蚀刻掩模之前从所述基底去除所述第一蚀刻掩模。
12.根据权利要求1所述的方法，其中进行所述第一蚀刻工艺包括选择性地去除所述多线层的所述两种或更多种不同材料中的至少一者的露出部分。
13.根据权利要求12所述的方法，其中所述两种或更多种不同材料包括三种或更多种不同材料，其中选择性地去除所述两种或更多种不同材料中的至少一者包括选择性地去除所述三种或更多种不同材料中的两者，导致所述目标层的对应部分被露出。
14.根据权利要求1所述的方法，其中进行所述第二蚀刻工艺包括选择性地去除所述多线层的所述两种或更多种不同材料中的至少一者的露出部分。
15.根据权利要求1所述的方法，还包括：
在形成所述第一蚀刻掩模之前，将由所述多线层限定的图案转移到所述第一记忆层中。
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