TWI694486B - 減少通孔至格柵圖案化中之覆蓋誤差的方法 - Google Patents

減少通孔至格柵圖案化中之覆蓋誤差的方法 Download PDF

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TWI694486B
TWI694486B TW106136075A TW106136075A TWI694486B TW I694486 B TWI694486 B TW I694486B TW 106136075 A TW106136075 A TW 106136075A TW 106136075 A TW106136075 A TW 106136075A TW I694486 B TWI694486 B TW I694486B
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尼哈爾 莫漢蒂
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日商東京威力科創股份有限公司
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Abstract

本文中的技術包含基板圖案化方法，其利用基於自對準的製程，以藉由使用複數不同材料使通孔對準奇數及偶數凹槽。本文中的方法將通孔圖案分解或分離成間隔件側通孔及心軸側通孔，且然後後續分別使用間隔件側及心軸側。利用如此之技術，顯著地改善了通孔至格柵的覆蓋。藉由使用位於凹槽記憶層下方的額外記憶層、以及獨立地使用凹槽圖案中間的間隔件側及心軸側，在通孔對準方面達成顯著的改善。

Description

減少通孔至格柵圖案化中之覆蓋誤差的方法
本揭露內容相關於包含例如半導體晶圓之基板的處理的半導體製造。
[相關申請案之交互參考]
本申請案主張2016年10月20日申請、名為「Method of Reducing Overlay Error in Via to Grid Patterning」之美國臨時專利申請案第62/410,811號的權利，其係整體併入於此，以供參考。
半導體元件係持續縮小以在基板的每單位面積容納更多的元件。本文中的技術解決了通孔圖案化(via patterning)所面臨的問題，且該問題為通孔至格柵的覆蓋改善。在先進節點的情形中，當BEOL(產線後段)凹槽圖案化發展至30nm節距以下時，在奇數與偶數凹槽之間對準通孔遮罩成為挑戰。本文中的技術利用基於自對準的製程，以藉由利用複數不同的材料及記憶層使通孔對準奇數及偶數凹槽。
技術包含基板圖案化方法。第一記憶層係形成於基板的目標層上。第二記憶層係形成於第一記憶層上。多線層係形成於第二記憶層上方。多線層包含具有交替線圖案的區域，該交替線圖案具有二或更多不同材料。每一 線具有水平厚度、垂直高度、且在基板之範圍延伸。交替線圖案的每一線形成多線層之頂部表面的一部分，且垂直延伸至多線層的底部表面。二或更多不同材料其中至少兩者藉由具有相對於彼此不同的耐蝕刻性而在化學上彼此不同。第一蝕刻遮罩係形成於多線層上。執行第一蝕刻製程，其利用第一蝕刻遮罩及多線層的一或更多材料作為第一組合蝕刻遮罩而蝕刻進入第一記憶層。第二蝕刻遮罩係形成於多線層上。執行第二蝕刻製程，其利用第二蝕刻遮罩及多線層的一或更多材料作為第二組合蝕刻遮罩而蝕刻進入第一記憶層。
當然，如本文中所描述之不同步驟的討論順序已為清楚起見而呈現。一般而言，該等步驟可按照任何適當的順序執行。此外，儘管本文中之不同特徵、技術、配置等的每一者可在本揭露內容的不同位置加以討論，但其意圖在於概念的每一者可獨立於彼此、或與彼此結合而執行。據此，本發明可以許多不同的方式加以實施及審視。
注意到，本發明內容部分不具體說明本揭露內容或所請發明的每一實施例及/或漸增新穎實施態樣。反而，本發明內容僅提供不同實施例的初步討論、以及優於習知技術之新穎性的對應點。對於本發明及實施例的額外細節及/或可能觀點，引導讀者至如以下進一步討論之本揭露內容的實施方式部分及對應圖式。
100:基板
107:目標層
111:第一記憶層
112:第二記憶層
115:中間層
121:多線層
131:心軸
132:側壁間隔件
136:心軸側
137:間隔件側
144:下心軸層
145:上心軸層
151:第一蝕刻遮罩
152:第二蝕刻遮罩
163:栓塞部
164:栓塞部
171:通孔
172:凹槽
結合隨附圖式考量的情況下，參照以下詳細說明，本發明之諸多實施例的更完整的理解及其許多伴隨的優勢將變得顯而易見。圖式未必依比例繪製，而是強調說明特徵、原理、及概念。
圖1為例示性基板部分的示意性橫剖面側面圖，其顯示根據本文中所揭露之實施例的製程流程。
圖2為例示性基板部分的示意性橫剖面側面圖，其顯示根據本文中所揭露之實施例的製程流程。
圖3為例示性基板部分的示意性橫剖面側面圖，其顯示根據本文中所揭露之實施例的製程流程。
圖4為例示性基板部分的示意性橫剖面側面圖，其顯示根據本文中所揭露之實施例的製程流程。
圖5為例示性基板部分的示意性橫剖面側面圖，其顯示根據本文中所揭露之實施例的製程流程。
圖6為例示性基板部分的示意性橫剖面側面圖，其顯示根據本文中所揭露之實施例的製程流程。
圖7為例示性基板部分的示意性橫剖面側面圖，其顯示根據本文中所揭露之實施例的製程流程。
圖8為例示性基板部分的示意性橫剖面側面圖，其顯示根據本文中所揭露之實施例的製程流程。
圖9為例示性基板部分的示意性橫剖面側面圖，其顯示根據本文中所揭露之實施例的製程流程。
圖10為例示性基板部分的示意性橫剖面側面圖，其顯示根據本文中所揭露之實施例的製程流程。
圖11為例示性基板部分的示意性橫剖面側面圖，其顯示根據本文中所揭露之實施例的製程流程。
圖12為例示性基板部分的示意性橫剖面側面圖，其顯示根據本文中所揭露之實施例的製程流程。
圖13為例示性基板部分的示意性橫剖面側面圖，其顯示根據本文中所揭露之實施例的製程流程。
圖14為例示性基板部分的示意性橫剖面側面圖，其顯示根據本文中所揭露之實施例的製程流程。
圖15為例示性基板部分的示意性橫剖面側面圖，其顯示根據本文中所揭露之實施例的製程流程。
圖16為例示性基板部分的示意性橫剖面側面圖，其顯示根據本文中所揭露之實施例的製程流程。
圖17為例示性基板部分的示意性橫剖面側面圖，其顯示根據本文中所揭露之實施例的製程流程。
圖18為例示性基板部分的示意性橫剖面側面圖，其顯示根據本文中所揭露之實施例的製程流程。
本文中的技術包含基板圖案化方法，其利用基於自對準的製程，以藉由使用複數不同材料使通孔對準奇數及偶數凹槽。例示性實施例可適用於雙重圖案化格柵(例如，SAQP(自對準四重圖案化)格柵或SADP(自對準雙重圖案化)格柵)及其他圖案化方法。本文中的方法將通孔圖案分解或分離成間隔件側通孔及心軸側通孔，且然後後續分別使用間隔件側及心軸側。利用如此之技術，顯著地改善了通孔至格柵的覆蓋。藉由使用位於凹槽記憶層下方的額外記憶層、以及獨立地使用凹槽圖案中間的間隔件側及心軸側，在通孔對準方面達成顯著的改善。
現在參考圖1，第一記憶層111係形成於基板100的目標層107上。第二記憶層112係形成於第一記憶層111上。可使用諸多不同的材料。在一範例 中，第一記憶層111可為用於通孔記憶化的矽氮化物，而第二記憶層112可為用於凹槽記憶化的鈦氮化物。中間層115可形成於第二記憶層112上。中間層115為選用。
多線層121係形成於第二記憶層112上方。多線層121可形成於第二記憶層112上或中間層115上。多線層121包含具有交替線圖案的區域，該交替線圖案具有二或更多不同材料。每一線具有水平厚度、垂直高度、且在基板之範圍延伸。交替線圖案的每一線形成多線層121之頂部表面的一部分，且垂直延伸至多線層121的底部表面。二或更多不同材料其中至少二者藉由具有相對於彼此不同的耐蝕刻性而在化學上彼此不同。
在一些實施例中，多線層121包含心軸131及形成於心軸131之側壁上的側壁間隔件132。側壁間隔件132具有心軸側136及間隔件側137。心軸側136與分別的心軸131接觸。側壁間隔件132在相鄰側壁間隔件132的間隔件側137之間定義開放空間。換言之，在相鄰側壁間隔件132之間隔件側137之間有開放空間。
具有二或更多不同材料的交替線圖案可包含A-B-C-B-A-B-C-B之重複序列，其中材料A及材料B具有相對於彼此不同的耐蝕刻性。在一範例中，心軸131可為材料A，而側壁間隔件132係材料B。材料C可為第三材料，或可為圖中所示的開放空間。
在一些實施例中，心軸131可形成為具有上心軸層145及下心軸層144之兩材料的複合物。中間層115及上心軸層145可由相同材料組成。上心軸層145的垂直厚度可比中間層115的垂直厚度更大。
現在參考圖2，栓塞部163(或複數栓塞部163)可形成於多線層121中之開放空間內的預定位置處。以非限制性範例為例，如此之栓塞部163可藉由 鈦氧化物之原子層沉積形成。栓塞部遮罩可用於沉積。取決於針對用途所選擇的材料及該等材料的耐蝕刻性，形成栓塞部163乃選用卻可能有利。或者，第三材料線可用於多線層121中。
可執行蝕刻製程，其利用多線層121(及任何栓塞部163)作為蝕刻遮罩而蝕刻進入第二記憶層112(圖3)。相較於中間層115具有較厚的上心軸層145有助於保留心軸覆蓋部，同時能夠蝕刻穿過中間層115。
第一蝕刻遮罩151係形成於多線層121上。圖4及5說明例示性結果。執行第一蝕刻製程，其利用第一蝕刻遮罩151及多線層121之一或更多材料作為第一組合蝕刻遮罩而蝕刻進入第一記憶層111(圖6)。在一範例中，第一蝕刻遮罩151可包含用於圖案化通孔的槽開口。
然後，可移除第一蝕刻遮罩151(圖7)。或者，栓塞部164可形成於由第一蝕刻製程所產生的開口中(圖8)。例如，如此之栓塞部164可為鋯氧化物。
在圖9中，心軸131係從多線層121移除。在圖10中，執行蝕刻製程，其利用多線層121之剩下的材料作為蝕刻遮罩而蝕刻第二記憶層112。
第二蝕刻遮罩152係形成於多線層121上(圖11)。執行第二蝕刻製程，其利用第二蝕刻遮罩152及多線層121之一或更多材料作為第二組合蝕刻遮罩而蝕刻進入第一記憶層111(圖12)。注意到，多線層材料的一或更多者可受到蝕刻，或者，(尤其當相較於三或更多材料線具有兩材料線加上一間隔時)多線層121可已具有開口，且由此無需蝕刻多線層121的一或更多線。一或更多線可在形成任何蝕刻遮罩之前的先前步驟中受到蝕刻，或者在形成給定蝕刻遮罩之後受到蝕刻。
第一蝕刻遮罩151、第二蝕刻遮罩152、及多線層121可全部加以移除(圖13及14)。取決於期望的製程流程，第一蝕刻遮罩151可在先前的步驟中加以移除。現在，基板100具有記憶於第一記憶層111及第二記憶層112中的圖 案。執行蝕刻製程，其將藉由第一記憶層111所定義的第一記憶層圖案轉移至目標層107中(圖15)。接下來，執行蝕刻製程，其將藉由第一記憶層111所定義的第二記憶層圖案轉移至目標層107中(圖16及17)。注意到，在目標層107具有一種材料的情形中，當第二記憶層圖案被轉移至目標層107中時，利用第一記憶層圖案已加以蝕刻的特徵部或開口將被蝕刻地更深。
據此，通孔及凹槽兩者皆可被蝕刻至目標層107中。圖18為移除記憶層、且將通孔171及凹槽172圖案化至目標層107中的情形。另一優點為在槽開口垂直橫越多線層121的線之情況下，通孔開口可利用槽開口進行圖案化，且可藉由伴隨多線層121及雙記憶層的蝕刻選擇性而被縮窄成方形或圓形開口。如此之技術可改善良率，並且降低邊緣位置誤差。注意到，可使用利用多線層121下方之雙記憶層的諸多製程流程。例如，記憶層的任何者可首先或第二個進行圖案化。記憶層可在諸多階段利用多線層121及/或諸多蝕刻遮罩而圖案化。結果為利用自對準記憶兩圖案，且該兩圖案可用以針對金屬化而準確地圖案化凹槽及通孔。
在前述說明內容中，已提出如處理系統之特定幾何結構、及其中所用諸多元件及製程之說明的特定細節。然而，吾人應理解，上本文中之技術可在背離該等特定細節的其他實施例中實施，且如此之細節係用於解釋且非限制的目的。本文中所揭露之實施例已參照隨附圖式加以描述。類似地，針對解釋的目的，已提出特定的數目、材料、及配置，以提供透徹的理解。然而，實施例可在沒有如此之特定細節的情形中實施。具有實質上相同功能性結構的元件係以相似參考符號表示，且由此可省略任何重複的描述。
各種不同的技術已描述為複數的分離操作，以幫助理解各種不同的實施例。描述的順序不應被視為暗示該等操作必須順序相依。實際上，該等 操作不必以所呈現之順序執行。所描述之操作可按照不同於所述實施例的順序執行。在附加的實施例中，可執行諸多額外的操作、且/或可省略所述操作。
依據本發明，本文中所使用之「基板」或「目標基板」一般是指受處理的物體。基板可包含元件(特別是半導體或其他電子元件)的任何材料部分或結構，且舉例而言，可為基礎基板結構，如半導體晶圓、倍縮遮罩、或基礎基板結構上或覆蓋該基礎基板結構的覆層(如薄膜)。因此，基板不受限於任何特定的基礎結構、下方層或上方層、圖案化或非圖案化，反而基板被認為包含任何的如此之覆層或基礎結構、以及覆層及/或基礎結構的任何組合。描述內容可參照特定類型的基板，但其僅為說明性的目的。
熟習該領域技術者亦將理解，針對以上所解釋之技術的操作可作出諸多不同變化，而仍達成本發明之同樣的目標。如此之變化意在涵蓋於本揭露內容的範疇中。因此，本發明之實施例的前述內容不意圖為限制性。反而，對於本發明之實施例的任何限制係呈現於以下申請專利範圍中。
100‧‧‧基板
107‧‧‧目標層
111‧‧‧第一記憶層
112‧‧‧第二記憶層
115‧‧‧中間層

Claims (15)

  1. 一種基板圖案化方法，該方法包含：在一基板的一目標層上形成一第一記憶層；在該第一記憶層上形成一第二記憶層；在該第二記憶層上方形成一多線層，該多線層包含具有一交替線圖案的一區域，該交替線圖案具有二或更多不同材料，其中每一線具有一水平厚度、一垂直高度，且於該基板之範圍延伸，其中該交替線圖案之每一線形成該多線層之一頂部表面的一部分，且垂直延伸至該多線層的一底部表面，其中該二或更多不同材料其中至少兩者藉由具有相對於彼此不同的耐蝕刻性而在化學上彼此不同；在該多線層上形成一第一蝕刻遮罩並執行一第一蝕刻製程，該第一蝕刻製程利用該第一蝕刻遮罩與該多線層的一或更多材料作為一第一組合蝕刻遮罩而蝕刻進入該第一記憶層；在執行該第一蝕刻製程之後，從該多線層移除一特定材料，並將藉由該多線層所定義的一圖案轉移至該第一記憶層中；以及在將藉由該多線層所定義的該圖案轉移至該第一記憶層中之後，在該多線層上形成一第二蝕刻遮罩並執行一第二蝕刻製程，該第二蝕刻製程利用該第二蝕刻遮罩與該多線層的一或更多材料作為一第二組合蝕刻遮罩而蝕刻進入該第一記憶層。
  2. 如申請專利範圍第1項之基板圖案化方法，更包含：移除該第一蝕刻遮罩、該第二蝕刻遮罩、及該多線層；將藉由該第一記憶層所定義的一第一記憶層圖案轉移至該目標層中；以及 將藉由該第一記憶層所定義的一第二記憶層圖案轉移至該目標層中。
  3. 如申請專利範圍第2項之基板圖案化方法，其中該目標層包含介電材料；其中該第一記憶層圖案定義通孔；以及其中該第二記憶層圖案定義凹槽。
  4. 如申請專利範圍第2項之基板圖案化方法，其中該多線層包含心軸及形成於該心軸之側壁上的側壁間隔件，該側壁間隔件具有一心軸側及一間隔件側，且該心軸側與一個別心軸接觸，該側壁間隔件在相鄰側壁間隔件之間隔件側之間定義開放空間。
  5. 如申請專利範圍第2項之基板圖案化方法，其中具有二或更多不同材料之該交替線圖案包含A-B-C-B-A-B-C-B之重複序列，其中材料A及材料B具有相對於彼此不同的耐蝕刻性。
  6. 如申請專利範圍第4項之基板圖案化方法，更包含介於該第二記憶層及該多線層之間的一中間層。
  7. 如申請專利範圍第6項之基板圖案化方法，其中該心軸係形成為具有一上心軸層及一下心軸層之兩材料的一複合物。
  8. 如申請專利範圍第7項之基板圖案化方法，其中該中間層及該上心軸層係由相同材料組成，且其中該上心軸層的一垂直厚度大於該中間層的一垂直厚度。
  9. 如申請專利範圍第4項之基板圖案化方法，更包含：在形成該第一蝕刻遮罩之前，在該多線層中之開放空間內的預定位置處形成栓塞部。
  10. 如申請專利範圍第9項之基板圖案化方法，更包含： 在執行該第一蝕刻製程之後、且在形成該第二蝕刻遮罩之前，在該多線層中之開放空間內的裸露位置處形成栓塞部。
  11. 如申請專利範圍第2項之基板圖案化方法，其中該第一蝕刻遮罩係在形成該第二蝕刻遮罩之前從該基板移除。
  12. 如申請專利範圍第1項之基板圖案化方法，其中執行該第一蝕刻製程包含選擇性地移除該多線層之該二或更多不同材料其中至少一者的裸露部分。
  13. 如申請專利範圍第12項之基板圖案化方法，其中該二或更多不同材料包含三或更多不同材料，其中選擇性地移除該二或更多不同材料其中至少一者包含選擇性地移除該三或更多不同材料其中二者，導致該目標層的對應部分裸露。
  14. 如申請專利範圍第1項之基板圖案化方法，其中執行該第二蝕刻製程包含選擇性地移除該多線層之該二或更多不同材料其中至少一者的裸露部分。
  15. 如申請專利範圍第1項之基板圖案化方法，更包含：在形成該第一蝕刻遮罩之前，將藉由該多線層所定義的一圖案轉移至該第一記憶層中。
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