JP5459906B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5459906B2 JP5459906B2 JP2009282655A JP2009282655A JP5459906B2 JP 5459906 B2 JP5459906 B2 JP 5459906B2 JP 2009282655 A JP2009282655 A JP 2009282655A JP 2009282655 A JP2009282655 A JP 2009282655A JP 5459906 B2 JP5459906 B2 JP 5459906B2
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- oxide semiconductor
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- semiconductor layer
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
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Description
薄膜トランジスタを用いて表示装置の画素を構成する例を以下に説明する。本実施の形態では、一例として、液晶表示装置における画素が有する薄膜トランジスタ(以下、TFTともいう)及び当該TFTに接続された画素電極として機能する電極(単に画素電極ともいう)について示し、説明する。なお本実施の形態に示す構成は、画素電極として機能する電極に接続されたトランジスタであれば、液晶表示装置に限らず適用可能である。なお画素とは、表示装置の各画素に設けられた各素子、例えば薄膜トランジスタ、画素電極として機能する電極、及び配線等の電気的な信号により表示を制御するための素子で構成される素子群、のことをいう。なお画素は、カラーフィルター及び表示素子等を含むものであっても良く、一画素によって、明るさを制御できる色要素一つ分としてもよい。よって、一例として、RGBの色要素からなるカラー表示装置の場合には、画像の最小単位は、Rの画素とGの画素とBの画素との三画素から構成されるものとなり、複数の画素によって画像を得ることができるものとなる。
上記実施の形態とは別のTFTの構成の表示装置の画素を構成する例を以下に説明する。
上記実施の形態とは別のTFTの構成の表示装置の画素を構成する例を以下に説明する。
上記実施の形態とは別のTFTの構成の表示装置の画素を構成する例を以下に説明する。
本実施の形態では、実施の形態1の図10で説明した表示装置を、発光表示装置に適用した例を示す。表示装置の有する表示素子としては、ここではエレクトロルミネッセンスを利用する発光素子を用いて示す。エレクトロルミネッセンスを利用する発光素子は、発光材料が有機化合物であるか、無機化合物であるかによって区別され、一般的に、前者は有機EL素子、後者は無機EL素子と呼ばれている。
本実施の形態では、実施の形態1の図10で説明した表示装置を電子ペーパー(デジタルペーパー、またはペーパーライクディスプレイともいわれる)として使用する例を示す。
本実施の形態においては、上記実施の形態で説明した表示装置を具備する電子機器の例について説明する。
101 TFT
102 配線
103 配線
104 配線
105 酸化物半導体層
106 酸化物半導体層
107 電極
108 酸化物半導体層
121 基板
122 ゲート絶縁膜
123 絶縁層
124 保持容量
201 画素部
202 ゲート線駆動回路
203 ソース線駆動回路
401 レジストマスク
407 導電層
102A 配線
102B 配線
1105 酸化物半導体層
1300 画素
1301 TFT
1302 配線
1303 配線
1304 配線
1305 酸化物半導体層
1306 酸化物半導体層
1307 電極
1308 酸化物半導体層
1321 基板
1322 ゲート絶縁膜
1323 絶縁層
1324 保持容量
1401 レジストマスク
1405 点線部
1407 導電層
1600 画素
1601 TFT
1602 配線
1603 配線
1604 配線
1605 酸化物半導体層
1606 酸化物半導体層
1607 電極
1608 酸化物半導体層
1609 電極
1621 基板
1622 ゲート絶縁膜
1623 絶縁層
1624 保持容量
1707 導電層
1800 画素
1801 TFT
1802 配線
1803 配線
1804 配線
1805 酸化物半導体層
1806 酸化物半導体層
1807 電極
1808 酸化物半導体層
1809 電極
1821 基板
1822 ゲート絶縁膜
1823 絶縁層
1824 保持容量
1907 導電層
2001 TFT
2002 TFT
2003 発光素子
2004 容量素子
2005 ソース配線層
2006 ゲート配線層
2007 電源線
2020 電極層
2021 隔壁
2022 電界発光層
2023 電極層
2027 発光素子
2281 TFT
2287 電極層
2288 電極層
2289 球形粒子
2294 キャビティ
2295 充填材
9630 筐体
9631 表示部
9633 スピーカ
9635 操作キー
9636 接続端子
9638 マイクロフォン
9672 記録媒体読込部
9676 シャッターボタン
9677 受像部
9680 外部接続ポート
9681 ポインティングデバイス
1302A 配線
1302B 配線
1602A 配線
1602B 配線
1802A 配線
1802B 配線
Claims (1)
- 基板よりも上方に、第1の酸化物半導体層を有し、
前記第1の酸化物半導体層よりも上方に第2の酸化物半導体層と、第3の酸化物半導層と、を有し、
前記第2の酸化物半導体層よりも上方に第1の導電層と、第3の導電層と、を有し、
前記第1の導電層よりも上方に絶縁層を有し、
前記絶縁層よりも上方に第2の導電層と、第4の導電層と、を有し、
前記第1の酸化物半導体層は、第1の酸化物半導体膜をエッチング加工する工程を経て形成されたものであり、
前記第2の酸化物半導体層と、前記第3の酸化物半導体層とは、第2の酸化物半導体膜をエッチング加工する工程を経て形成されたものであり、
前記第1の導電層と、前記第3の導電層とは、第1の導電膜をエッチング加工する工程を経て形成されたものであり、
前記第2の導電層と、前記第4の導電層とは、第2の導電膜をエッチング加工する工程を経て形成されたものであり、
前記第1の酸化物半導体膜は、インジウムとガリウムと亜鉛とを有し、
前記第2の酸化物半導体膜は、インジウムとガリウムと亜鉛とを有し、
前記第1の酸化物半導体層は、トランジスタのチャネル領域となることができる第1の部分を有し、
前記第2の酸化物半導体層は、前記第1の導電層と接する第2の部分を有し、
前記第1の導電層は、前記トランジスタのソース電極又はドレイン電極の一方となることができる第3の部分を有し、
前記絶縁層は、前記トランジスタのゲート絶縁層となることができる第4の部分を有し、
前記第2の導電層は、前記トランジスタのゲート電極となることができる第5の部分を有し、
前記第3の酸化物半導体層は、前記第3の導電層と接する第6の部分を有し、
前記第3の導電層は、容量素子の一対の電極のうちの一方となることができる第7の部分を有し、
前記第4の導電層は、絶縁層を介して前記第7の部分と重なり、前記容量素子の一対の電極のうちの他方となることができる第8の部分を有し、
前記第1の部分は、第1の抵抗率を有し、
前記第2の部分は、第2の抵抗率を有し、
前記第6の部分は、第3の抵抗率を有し、
前記第2の抵抗率及び前記第3の抵抗率は、前記第1の抵抗率よりも小さく、
前記第1の導電層は、前記基板と接しないことを特徴とする半導体装置。
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JP5841622B2 (ja) | 2016-01-13 |
JP6030182B2 (ja) | 2016-11-24 |
KR101738379B1 (ko) | 2017-05-22 |
KR20150018480A (ko) | 2015-02-23 |
KR101634606B1 (ko) | 2016-06-29 |
TW201530786A (zh) | 2015-08-01 |
JP2010170110A (ja) | 2010-08-05 |
US20100163865A1 (en) | 2010-07-01 |
JP2014116617A (ja) | 2014-06-26 |
TWI545779B (zh) | 2016-08-11 |
US20130234136A1 (en) | 2013-09-12 |
KR20160089319A (ko) | 2016-07-27 |
CN101794770B (zh) | 2014-04-30 |
TW201037839A (en) | 2010-10-16 |
CN101794770A (zh) | 2010-08-04 |
US9112043B2 (en) | 2015-08-18 |
CN103872043B (zh) | 2019-01-15 |
US20140124779A1 (en) | 2014-05-08 |
JP2015164205A (ja) | 2015-09-10 |
KR20100075756A (ko) | 2010-07-05 |
TWI493721B (zh) | 2015-07-21 |
US8441007B2 (en) | 2013-05-14 |
US8629434B2 (en) | 2014-01-14 |
CN103872043A (zh) | 2014-06-18 |
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