JP5379189B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5379189B2 JP5379189B2 JP2011141849A JP2011141849A JP5379189B2 JP 5379189 B2 JP5379189 B2 JP 5379189B2 JP 2011141849 A JP2011141849 A JP 2011141849A JP 2011141849 A JP2011141849 A JP 2011141849A JP 5379189 B2 JP5379189 B2 JP 5379189B2
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Description
のではなく、一方は他方の一部または全部の変形例、詳細、補足説明などの関係にある。
図1、図2に示す本実施の形態1の半導体装置は、図7に示すリードフレーム1を用いて組み立てられ、かつこのリードフレーム1の片方の面側に樹脂モールディングによって封止部3が形成された片面モールドの樹脂封止型の小型半導体パッケージであり、さらに、封止部3の裏面3aの周縁部に複数のリード1aの被実装面1dを露出させて配置したペリフェラル形のものでもあり、前記半導体装置の一例として、QFN5を取り上げて説明する。
とキャピラリ7との間隔(Q)を見極めて搭載可能チップサイズを設定する必要がある。
本実施の形態2は、実施の形態1で説明したQFN5とほぼ同様の構造のQFN9について説明するものである。
aの強度を確保して樹脂モールディング時のリード1aの変形を防止することができる。
ランプ時の反力によってリード1aが変形してしまうという不具合の発生を防止できる。
本実施の形態3は、QFN構造の半導体装置において、放熱性を高める構造を説明するものである。すなわち、実施の形態1で説明したQFN5は、対向して配置されたリード1a同士における封止部形成面1gの内側端部1h間の長さ(M)が被実装面1dの内側端部1h間の長さ(L)より長くなるように形成され、したがって、長さ(M)>長さ(L)であり、その結果、各リード1aの封止部形成面1gの内側端部1hによって囲まれるチップ搭載領域を拡大することができ、パッケージサイズを変えることなく搭載可能チップサイズの拡大化を図るものであるが、このような半導体装置において、本実施の形態3のQFN15は、図39や図41に示すように、チップ端部が各リード1aに近づくぐらいに大きな半導体チップ2を搭載したものである。
本実施の形態4は、QFN構造の半導体装置のさらに小型化を図る技術であり、主にGND電位などの固定電位の安定化を図った半導体装置である。ここでは、一例として、高周波で動作する回路が組み込まれた半導体チップ2を有するQFN16を取り上げて説明する。
ため、4本のタブ吊りリード1eをGND用の共通の外部端子として用いるものである。
図59は本実施の形態5のQFN19の構造を示しており、QFN19は、タブ吊りリード1eへのワイヤ4の接続は行われているが、各リード1aにおいて、図2に示すような被実装面1dの長さ(P)と封止部形成面1gの長さ(Q)の関係が、P>Qではなく、P=Qの場合である。
1a リード
1b タブ
1c チップ支持面
1d 被実装面
1e タブ吊りリード
1f ボンディングポイント
1g 封止部形成面
1h 内側端部
1i 切り欠き部
1j 切断部
1k モールドライン
1l 裏面
1m 凹部
1n 端部肉部
1p 基端部
1q ワイヤ接合部
1r 湾曲結合部
1s 突起部
1t 凹部
1u 切り欠き部
2 半導体チップ
2a パッド
2b 主面
2c 裏面
2d 高周波アンプ
3 封止部
3a 裏面
3b 側面
3c 面取り部
4 ワイヤ
5 QFN
6 半田メッキ層
7 キャピラリ
8 成形金型
8a 上型
8b 下型
8c キャビティ
9 QFN
10 レジン流動方向
11 フィルム
12 ブレード
13 切断金型
14 一括封止部
15 QFN
16 QFN
17 実装基板
17a 端子
17b 内側端部
18 ソケット
18a 本体
18b 蓋部
18c 位置決め台
18d パッケージ押さえ
18e コンタクトピン
19 QFN
Claims (8)
- チップ支持面、及び前記チップ支持面とは反対側の裏面を有するチップ搭載部と、
封止部形成面、前記封止部形成面とは反対側の被実装面、前記封止部形成面と前記被実装面との間に位置し、かつ前記チップ搭載部と向かい合う内側端面、前記封止部形成面と前記被実装面との間に位置し、かつ前記内側端面とは反対側の外側端面、前記封止部形成面と前記被実装面との間に位置し、かつ前記内側端面と前記外側端面との間に位置するリード側面を備え、さらに前記封止部形成面から前記内側端面に繋がる切り欠き部を有する複数のリードと、
第1主面、前記第1主面に形成された複数のパッド、および前記第1主面とは反対側の第2主面を有し、前記第2主面が前記チップ支持面と対向するように、前記チップ搭載部の前記チップ支持面上に搭載された半導体チップと、
前記半導体チップの前記複数のパッドと前記複数のリードとをそれぞれ電気的に接続する複数のワイヤと、
上面、前記上面とは反対側の下面、及び前記上面と前記下面との間に位置する側面を有し、前記半導体チップ、前記複数のリードおよび前記複数のワイヤを封止する封止部と、
を含み、
前記切り欠き部は、断面視において前記封止部形成面と前記被実装面との間に位置する表面を備えており、
前記切り欠き部の前記表面は、前記半導体チップの前記第2主面と対向しており、
前記複数のリードのそれぞれの前記被実装面は、前記封止部の前記下面から露出しており、
前記封止部形成面と前記切り欠き部とが交わる第1内側端部は、前記内側端面と前記被実装面とが交わる第2内側端部よりも前記外側端面側に位置しており、
前記複数のリードのそれぞれは、前記封止部形成面における前記リードの延在方向と交差する方向の幅が、前記被実装面における前記リードの延在方向と交差する方向の幅よりも広いことを特徴とする半導体装置。 - 請求項1記載の半導体装置において、前記チップ搭載部の外形寸法は、前記半導体チップの外形寸法よりも小さいことを特徴とする半導体装置。
- 請求項2記載の半導体装置において、前記チップ支持面は、断面視において、前記複数のリードのそれぞれの前記封止部形成面と同じ位置に配置されていることを特徴とする半導体装置。
- 請求項3記載の半導体装置において、前記チップ搭載部の前記裏面は、前記封止部の前記下面から露出していることを特徴とする半導体装置。
- 請求項3記載の半導体装置において、前記チップ搭載部の厚さは、前記複数のリードのそれぞれの厚さよりも薄く形成されており、前記チップ搭載部の前記裏面は、前記封止部で覆われていることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記複数のリードのそれぞれの前記リード側面は、湾曲していることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記リード側面は、前記被実装面に対して傾斜していることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記封止部は、前記複数のリードのそれぞれの前記被実装面が前記封止部の前記下面から露出するように、かつ前記複数のリードのそれぞれの前記外側端面が前記封止部の前記側面から露出するように、前記半導体チップ、前記複数のリードのそれぞれの前記一部及び前記複数のワイヤを封止していることを特徴とする半導体装置。
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JP (3) | JP4149439B2 (ja) |
KR (1) | KR100975692B1 (ja) |
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TW200416992A (en) | 2004-09-01 |
JPWO2004004005A1 (ja) | 2005-11-04 |
KR20050024447A (ko) | 2005-03-10 |
WO2004004005A1 (ja) | 2004-01-08 |
JP2008227531A (ja) | 2008-09-25 |
US7843049B2 (en) | 2010-11-30 |
KR100975692B1 (ko) | 2010-08-12 |
CN100533722C (zh) | 2009-08-26 |
CN100342533C (zh) | 2007-10-10 |
US20090200656A1 (en) | 2009-08-13 |
US20130001804A1 (en) | 2013-01-03 |
US20060017143A1 (en) | 2006-01-26 |
US7525184B2 (en) | 2009-04-28 |
JP4945508B2 (ja) | 2012-06-06 |
CN1666338A (zh) | 2005-09-07 |
US8390133B2 (en) | 2013-03-05 |
JP2011187996A (ja) | 2011-09-22 |
JP4149439B2 (ja) | 2008-09-10 |
US8222720B2 (en) | 2012-07-17 |
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US20110089548A1 (en) | 2011-04-21 |
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