TWM606836U - 導線架 - Google Patents

導線架 Download PDF

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TWM606836U
TWM606836U TW109212332U TW109212332U TWM606836U TW M606836 U TWM606836 U TW M606836U TW 109212332 U TW109212332 U TW 109212332U TW 109212332 U TW109212332 U TW 109212332U TW M606836 U TWM606836 U TW M606836U
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lead frame
grooves
extension
wafer holder
carrying
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TW109212332U
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黃嘉能
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長華科技股份有限公司
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Priority to TW109212332U priority Critical patent/TWM606836U/zh
Publication of TWM606836U publication Critical patent/TWM606836U/zh
Priority to US17/225,683 priority patent/US11495523B2/en

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    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4842—Mechanical treatment, e.g. punching, cutting, deforming, cold welding
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    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
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    • H01L23/4952—Additional leads the additional leads being a bump or a wire
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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Abstract

一種導線架，包含多條縱橫交錯的圍框，及多個由圍框界定的導線架單元，各導線架單元包括晶片座、多個溝槽，及多數引腳。晶片座具有高度低於圍框的承載部，及數個自承載部的端面成一角度彎折並朝圍框延伸的延伸部。溝槽對應於承載部及延伸部的交接處並自底面凹陷形成，且其徑寬同時跨越承載部及相鄰的延伸部。引腳間隔地自圍框朝晶片座延伸並與晶片座成一間距。本新型利用溝槽於承載部與延伸部的交接處釋放因彎折而產生的應力，避免交接處因殘留應力而形成彎角，使後續進行封裝時，能避免晶片座與封裝用的模具間產生空隙，進而導致溢膠的情形發生。

Description

導線架
本新型是有關於一種導線架，特別是指一種銲墊外露型的導線架。
參閱圖1，在封裝產業中，常見導線架封裝元件結構，例如：四腳扁平封裝(QFP)、小外型封裝(SOP)、薄小外型封裝(TSOP)等，封裝元件100的結構大致包含一導線架11、一晶片12，及一經封裝膠硬化後包覆該晶片12及該導線架11的封裝體13。該導線架11具有一供設置該晶片12的晶片座111、多數連接於該晶片座111周緣的延伸部112，及多數自該封裝體13外露並用於供該晶片12對外電連接的引腳113。其中，該封裝元件100以該封裝體13的封裝方式，而有銲墊外露型封裝(即該晶片座111的底面會外露，如圖1所示)，及一般型封裝(即該封裝體13同時會包覆該晶片座111的底面，圖未示)。
配合參閱圖1、圖2，前述該導線架11的製作方法，是將一具有與該導線架11結構相同但該晶片座111與該等引腳113的頂面位於同一平面的導線架成型品11A置入一沖壓模具中，利用該沖壓模具的沖頭42與下模41的配合，自該晶片座111位置向下沖壓，讓該晶片座111與該等延伸部112交接處彎曲，令該晶片座111與該等引腳113位於不同平面高度，之後進行固晶、打線，再透過封裝膠將該晶片12與該導線架11進行封裝，即可得到如圖1所示的銲墊外露型的封裝元件100。然而，由於經沖壓彎折後的延伸部112於彎折處容易形成大弧形彎角，導致在封膠過程中與用於形成該封裝體13的模具(圖未示)表面的密合性不佳而產生空隙，使該封裝膠在封裝過程中容易由該空隙處溢流到該晶片座111的底面，而令該晶片座111的底面露出的表面積減少，使得該封裝元件100整體的散熱效率下降，並影響該封裝元件100後續與其它元件連接的表面性能。
因此，本新型之目的，即在提供一種於封裝製程中能防止溢膠的情形發生的導線架。
於是，本新型的導線架由導電材料構成，包含多條成縱橫間隔交錯的圍框，及多個由該等圍框界定的導線架單元，每一圍框具有彼此反向的一頂面及一底面，每一導線架單元包括：一晶片座、多個溝槽，及多數引腳。
該晶片座具有一高度低於該等圍框的頂面的承載部，及數個自該承載部的端面成一角度彎折並朝向該等圍框的頂面方向延伸的延伸部。
該等溝槽對應位於該承載部及該延伸部交接處並自該承載部及該延伸部的底面凹陷形成，且每一溝槽的徑寬同時跨越該承載部及相鄰的該延伸部。
該等引腳彼此間隔地自該等圍框朝向該晶片座延伸並與該晶片座成一間距。
本新型之功效在於：利用於該承載部與該等延伸部的交接處形成該等溝槽，減小彎折處的材料厚度，並藉以釋放因彎折而產生的應力，避免交接處因殘留應力而產生弧形彎角，使後續使用本新型的導線架進行封裝時，能避免該晶片座與封裝用的模具之間產生空隙，進而導致溢膠的情形發生。
參閱圖3、圖4，圖4是圖3中IV-IV割面線的剖視圖。本新型導線架200的一實施例，該導線架200由銅系合金或鐵鎳合金等導電材料構成，包含多條成縱橫間隔交錯的圍框2，及多個由該等圍框2界定出並成陣列排列的導線架單元3。
每一圍框2具有彼此反向的一頂面，及一底面。每一導線架單元3包括一晶片座31、多個溝槽32、多數引腳33，及多數支撐條34。
該晶片座31具有一成四方形的承載部311、數個延伸部312，及數個平行部313。
該承載部311的高度低於該等圍框2的頂面，且具有一用於承載一晶片的頂面3111、一反向該頂面3111的底面3112，及至少一自該承載部311的底面3112向內凹陷形成的凹槽314。該凹槽314也可以是多條獨立設置於該承載部311的底面3112周圍的條狀凹槽，或是一環圍該承載部311底面3112周圍的環形凹槽，在本實施例中，該凹槽314以環狀為例說明。透過該凹槽314可供後續使用該導線架200經過晶片封裝形成封裝元件並與其它元件焊接時，於該承載部311的底面3112的焊料可被該凹槽314局限而不向外溢流。然而，實際實施時，也可視需求而無須形成該凹槽314。
每一延伸部312分別自該承載部311的端面成一角度彎折並朝向該等圍框2的頂面方向延伸，並具有一與該承載部311的底面3112同側的底面3121。該等平行部313分別自每一延伸部312遠離該承載部311的端面朝向該等引腳33方向延伸，並與該等引腳33平行且不相連接。要說明的是，該等延伸部312至少需位於該承載部311相對的兩端面以提供沖壓過程所需的平衡支撐，於本實施例中是以該等延伸部312分別形成於該承載部311的四個端面為例，然實際實施時，該等延伸部312也可以是只形成於該承載部311相對的兩端面。
該等溝槽32對應於該承載部311及該延伸部312交接處並自該承載部311的底面3112及該延伸部312的底面3121凹陷形成，且每一溝槽32的徑寬w同時跨越該承載部311及相鄰的該延伸部312。於一些實施例中，該等溝槽32的深度不大於該承載部311的厚度的三分之二，以避免該晶片座31的結構支撐力不足或是於彎折過程該等延伸部312斷裂的情形發生。此外，要再說明的是，該等溝槽32的目的是要於該承載部311及該延伸部312交接的彎折處形成缺口，減小彎折處的材料厚度，並藉以釋放因彎折而產生的應力，而避免於彎折處產生弧形彎角，因此，該等溝槽32能以不同的態樣呈現，例如該等溝槽32可如圖4所示為U型溝槽；或是如圖5所示，該等溝槽32也可以是自該承載部311與該其中一延伸部312的交接處的底面向內延伸漸縮形成的V型溝槽；或是，該等溝槽32也可以如圖6所示，為自該承載部311與該其中一延伸部312的交接處的底面向內等距延伸形成的方形溝槽，或是其它形狀等，並無需特別限制。
該等引腳33彼此間隔地自該等圍框2朝向該晶片座31方向延伸並與該晶片座31成一間距。
該等支撐條34分別自該承載部311的端點朝該等圍框2的頂面延伸並連接於該等圍框2，以固定該承載部311。其中，該等支撐條34與該承載部311的交接處也會成一直方角度的彎折，且該等溝槽32還對應形成於每一支撐條34及該承載部311的交接處的底面。
前述該導線架200是利用沖壓方式令該承載部311與該等延伸部312成預定角度彎折後而得。
參閱圖7，詳細的說，該沖壓過程是將一選自銅系合金或鐵鎳合金構成並具有與前述該實施例結構相同但該等晶片座31與該等圍框2的頂面位於同一平面的導線架成型品200A設置於一沖壓模具中，利用該沖壓模具的下模41及沖頭42配合，透過該沖頭42將該承載部311向下擠壓，令該等延伸部312與該承載部311的交接處自形成有該等溝槽32的位置處產生預定角度的彎折，即可得到該晶片座31。透過該等溝槽32對材料減薄並釋放彎折時產生的應力，因此，該導線架成型品200A經沖壓彎折後，於該等延伸部312與該承載部311的交接彎折處可避免形成弧形彎角。
參閱圖3與圖8，圖8是利用如圖3所述的該導線架200進行封裝、切割後得到的封裝元件300，該封裝元件300包含如前所述的該導線架單元3、一半導體晶片51、數條導線52，及一封膠體53。
該半導體晶片51設置於該承載部311的頂面3111，該等導線52分別連接該半導體晶片51與相應的該等引腳33而令彼此電連接。該封膠體53包覆該半導體晶片51與該晶片座31，且令該晶片座31的承載部311的底面3112與該等引腳33露出於封膠體53外，且部分該封膠體53填充於該等溝槽32中。
詳細的說，前述該封裝元件300是將設有該半導體晶片51及該等導線52的導線架200放置於一用於封膠的封裝模具中(圖未示)，令該承載部311的底面3112貼合於該封裝模具，透過模注的方式注入封裝膠以形成該封裝體53，之後，再進行切割，即可得到如圖8所示單顆封裝的該封裝元件300。其中，由於該導線架200的承載部311的底面3112與該封裝模具間並無空隙產生，因此，當注入封裝膠時，該封裝膠不會溢入該承載部311的底面3112，而可避免習知封裝膠溢流的問題。
綜上所述，本新型利用於該承載部311與該等延伸部312的交接處形成該等溝槽32，利用該等溝槽32減小彎折處的材料厚度並釋放沖壓彎折時所產生的應力，以避免該承載部311與該等延伸部312的交接處因應力殘留而產生大彎角，令後續進行封裝製程時，該晶片座31於該封裝模具之間不會有空隙產生，使該封裝膠不會溢入該承載部311的底面3112，減少該封裝元件300因溢膠而減少對外散熱面積(即該承載部311的底面3112露出於該封裝體53外的面積)的情形，確實能達成本新型之目的。
惟以上所述者，僅為本新型之實施例而已，當不能以此限定本新型實施之範圍，凡是依本新型申請專利範圍及專利說明書內容所作之簡單的等效變化與修飾，皆仍屬本新型專利涵蓋之範圍內。
100:封裝元件 11:導線架 11A:導線架成型品 111:晶片座 112:延伸部 113:引腳 12:晶片 13:封裝體 200:導線架 200A:導線架成型品 2:圍框 3:導線架單元 31:晶片座 311:承載部 3111:頂面 3112:底面 312:延伸部 3121:底面 313:平行部 314:凹槽 32:溝槽 33:引腳 34:支撐條 41:下模 42:沖頭 300:封裝元件 51:半導體晶片 52:導線 53:封膠體 w:徑寬
本新型之其他的特徵及功效，將於參照圖式的實施方式中清楚地呈現，其中： 圖1是一剖視示意圖，說明一習知的導線架； 圖2是一剖視示意圖，說明一習知的導線架成型品形成該習知的導線架的過程；圖3是一俯視示意圖，說明本新型導線架的一實施例；圖4是一沿圖3的IV-IV線的剖視示意圖，說明該實施例的一導線架單元，且該導線架單元的多數溝槽為U型溝槽的態樣；圖5是一剖視示意圖，說明該等溝槽為V型溝槽的態樣；圖6是一剖視示意圖，說明該等溝槽為方形溝槽的態樣；圖7是一剖視示意圖，說明一導線架成型品形成該實施例的導線架的過程；及圖8是一剖視示意圖，說明包含有該導線架的一封裝元件。
31:晶片座
311:承載部
3111:頂面
3112:底面
312:延伸部
3121:底面
313:平行部
314:凹槽
32:溝槽
w:徑寬

Claims (9)

  1. 一種導線架，由導電材料構成，包含多條成縱橫間隔交錯的圍框，及多個由該等圍框界定的導線架單元，每一圍框具有彼此反向的一頂面及一底面，每一導線架單元包括： 一晶片座，具有一高度低於該等圍框的頂面的承載部，及數個自該承載部的端面成一角度彎折並朝向該等圍框的頂面方向延伸的延伸部； 多個溝槽，對應位於該承載部及該延伸部交接處，並自該承載部及該延伸部的底面凹陷形成，且每一溝槽的徑寬同時跨越該承載部及相鄰的該延伸部；及 多數引腳，彼此間隔地自該等圍框朝向該晶片座延伸並與該晶片座成一間距。
  2. 如請求項1所述的導線架，其中，該等溝槽的深度不大於該承載部的厚度的三分之二。
  3. 如請求項1所述的導線架，其中，該等溝槽為U型溝槽。
  4. 如請求項1所述的導線架，其中，該等溝槽為V型溝槽。
  5. 如請求項1所述的導線架，其中，該等溝槽為方形溝槽。
  6. 如請求項1所述的導線架，其中，每一導線架單元的該晶片座還具有數個分別自每一延伸部遠離於該承載部的端面朝向該等引腳延伸，並與該等引腳平行且不相連接的平行部。
  7. 如請求項1所述的導線架，其中，每一導線架單元的該承載部具有一用於承載一晶片的頂面、一反向該頂面的底面，及至少一自該承載部的底面向內凹陷形成的凹槽。
  8. 如請求項1所述的導線架，其中，該等延伸部至少位於該承載部相對的兩端面。
  9. 如請求項1所述的導線架，其中，每一導線架單元還具有數條分別自該承載部的端點朝該等圍框的頂面延伸並連接於該等圍框的支撐條，該等溝槽還對應形成於每一支撐條及該承載部的交接處的底面。
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