JP5184558B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5184558B2 JP5184558B2 JP2010008015A JP2010008015A JP5184558B2 JP 5184558 B2 JP5184558 B2 JP 5184558B2 JP 2010008015 A JP2010008015 A JP 2010008015A JP 2010008015 A JP2010008015 A JP 2010008015A JP 5184558 B2 JP5184558 B2 JP 5184558B2
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- 239000004065 semiconductor Substances 0.000 title claims description 86
- 238000007789 sealing Methods 0.000 claims description 139
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- 238000007747 plating Methods 0.000 claims description 4
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
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- 239000011347 resin Substances 0.000 description 76
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- 230000007547 defect Effects 0.000 description 3
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- 229910001111 Fine metal Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
図1は本発明の実施の形態の半導体装置の構造の一例を示す平面図、図2は図1に示す半導体装置の構造の一例を示す裏面図、図3は図1に示す半導体装置の角部の構造を示す拡大部分斜視図、図4は図1に示す半導体装置の構造を封止体を透過して示す平面図、図5は図4に示すA−A線に沿って切断した断面の構造を示す断面図、図6は図4に示すB−B線に沿って切断した断面の構造を示す断面図、図7は図4に示すA−A線に沿って切断した断面の構造の変形例を示す断面図、図8は図7に示す構造を封止体を透過して示す拡大部分平面図、図9は図1に示す半導体装置の角部の裏面のピン配置の一例を示す拡大部分裏面図、図10は本発明の実施の形態の変形例の半導体装置の構造を示す裏面図、図11は図1に示す半導体装置の製造方法の一例を示す組み立てフロー図、図12は図11に示す半導体装置の製造方法のモールド工程における板厚ゲート使用時の樹脂注入方法の一例を示す部分断面図、図13は図11に示す半導体装置の製造方法のモールド工程における通常ゲート使用時の樹脂注入方法の一例を示す部分断面図、図14は図12に示す板厚ゲート使用時のゲートとリードの位置関係の一例を示す拡大部分平面図、図15は図13に示す通常ゲート使用時のゲートとリードの位置関係の一例を示す拡大部分平面図、図16は図15に示すフレームの角部の構造を示す部分拡大平面図、図17は図11に示す半導体装置の製造方法のリード切断から個片化までの各工程における加工状態の一例を示す部分拡大断面図および部分拡大側面図、図18は図1に示す半導体装置の角部の裏面のピン配置の一例を示す拡大部分裏面図、図19は図13に示す通常ゲート使用時における半導体装置の角部の構造を示す拡大部分斜視図である。
1a リード
1b タブ(チップ搭載部)
1c チップ支持面
1d 裏面
1e 吊りリード
1f 裏面
1g 被接続面(一部)
1h 切断面
1i 肉厚部
1j 突出部
1k 間隙
1m 切断しろ
1n テーパ(面取り)
2 半導体チップ
2a パッド(電極)
2b 主面
2c 裏面
3 封止体
3a 裏面
3b レジンバリ
4 ワイヤ(金属細線)
5 QFN(半導体装置)
6 ダイボンド材
7 レジン注入経路
8 フィルムシート(封止用シート)
9 樹脂成形金型
9a 上型
9b 下型
9c キャビティ
9d 金型面
9e ゲート部
9f ランナ
10 切断金型
10a 受け部
10b 押さえ部
10c 平坦部
10d 切断パンチ
11 レーザ
Claims (13)
- 複数の電極パッドが配置された表面を有する半導体チップと、
前記半導体チップが搭載された表面と、前記表面とは反対側の裏面と、を有するチップ搭載部と、
前記チップ搭載部と一体で形成された吊りリードと、
前記チップ搭載部の周囲に配置された複数のリードと、
前記半導体チップの前記複数の電極パッドと前記複数のリードとをそれぞれ接続する複数のワイヤと、
上面、前記上面とは反対側の下面、およびその厚さ方向において、前記上面と前記下面との間に配置された複数の側面を備え、前記半導体チップ、前記吊りリードの一部、および前記複数のリードのそれぞれの一部を封止する封止体と、を有し、
前記複数のリードのそれぞれの裏面は、前記封止体の前記下面から露出し、
前記吊りリードは、前記封止体の前記上面側から見たときに前記封止体の前記複数の側面のうちの一部の側面から突出する端部を有し、
前記吊りリードの前記端部は、前記封止体から露出する上面と、前記封止体に覆われた下面と、を有し、
前記吊りリードの前記端部は、前記複数のリードのそれぞれの厚さよりも薄く形成されている半導体装置。 - 請求項1に記載の半導体装置において、
前記チップ搭載部の前記裏面には、前記封止体の前記下面から露出する部分を有する。 - 請求項1に記載の半導体装置において、
前記チップ搭載部の前記裏面には突出部が設けられており、前記突出部の一部が前記封止体の前記下面から露出している。 - 請求項1に記載の半導体装置において、
前記チップ搭載部の前記裏面の一部は前記封止体により覆われている。 - 請求項1に記載の半導体装置において、
前記チップ搭載部の面積は、前記半導体チップの面積よりも大きい。 - 請求項1に記載の半導体装置において、
前記封止体は、面取りされた角部を有し、前記吊りリードの前記端部は、前記封止体の前記面取りされた前記角部から突出している。 - 請求項1に記載の半導体装置において、
前記複数のリードのそれぞれの表面の一部は、前記封止体から露出している。 - 請求項1に記載の半導体装置において、
前記複数のリードのそれぞれの表面の一部は、前記封止体の前記上面側から見たときに前記封止体の前記複数の側面のうち、前記吊りリードが突出した側面とは異なる側面から露出している。 - 請求項1に記載の半導体装置において、
前記複数のリードのそれぞれの前記裏面は、前記封止体の前記下面から突出している。 - 請求項1に記載の半導体装置において、
前記複数のリードのそれぞれの前記裏面には半田めっきが形成されている。 - 請求項1に記載の半導体装置において、
前記複数のリードのそれぞれの表面側には金属バリが形成されている。 - 請求項1に記載の半導体装置において、
前記複数のワイヤのそれぞれは、金ワイヤである。 - 請求項1に記載の半導体装置において、
前記封止体は、熱硬化性のエポキシ樹脂により構成されている。
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JP2010008015A JP5184558B2 (ja) | 2010-01-18 | 2010-01-18 | 半導体装置 |
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JP2010008015A JP5184558B2 (ja) | 2010-01-18 | 2010-01-18 | 半導体装置 |
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JP2009226011A Division JP4535513B2 (ja) | 2009-09-30 | 2009-09-30 | 半導体装置 |
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JP2012257864A Division JP5512784B2 (ja) | 2012-11-26 | 2012-11-26 | 半導体装置の製造方法 |
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JP5953703B2 (ja) * | 2011-10-31 | 2016-07-20 | ソニー株式会社 | リードフレームおよび半導体装置 |
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JP2002026190A (ja) * | 2000-07-03 | 2002-01-25 | Dainippon Printing Co Ltd | 樹脂封止型半導体装置 |
JP4523138B2 (ja) * | 2000-10-06 | 2010-08-11 | ローム株式会社 | 半導体装置およびそれに用いるリードフレーム |
JP2003158234A (ja) * | 2001-11-21 | 2003-05-30 | Hitachi Ltd | 半導体装置及びその製造方法 |
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