TWI290764B - Semiconductor device and the manufacturing method of the same - Google Patents

Semiconductor device and the manufacturing method of the same Download PDF

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Publication number
TWI290764B
TWI290764B TW092116267A TW92116267A TWI290764B TW I290764 B TWI290764 B TW I290764B TW 092116267 A TW092116267 A TW 092116267A TW 92116267 A TW92116267 A TW 92116267A TW I290764 B TWI290764 B TW I290764B
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Taiwan
Prior art keywords
wire
package
semiconductor wafer
wires
semiconductor device
Prior art date
Application number
TW092116267A
Other languages
Chinese (zh)
Other versions
TW200416992A (en
Inventor
Yoshihiko Shimanuki
Yoshihiro Suzuki
Koji Tsuchiya
Original Assignee
Hitachi Ltd
Renesas Nthn Jp Semiconductor
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Application filed by Hitachi Ltd, Renesas Nthn Jp Semiconductor filed Critical Hitachi Ltd
Publication of TW200416992A publication Critical patent/TW200416992A/en
Application granted granted Critical
Publication of TWI290764B publication Critical patent/TWI290764B/en

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    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

The present invention provides a semiconductor device, which is composed of a support tab 1b carrying the semiconductor chip 2, the package 3 formed by resin packaging with the semiconductor chip 2, the mounting surface 1d exposed from the edge of the back surface 3a of the package 3, a plurality of leads 1a configured on the package forming surface 1g on the opposite side, and the pad 2a and the wiring 4 of lead 1a connecting with the semiconductor chip 2; wherein the length M between the inner terminals 1h on the package-forming surface 1g for the leads 1a arranged oppositely within the plurality of leads 1a is formed longer than the length L between the inner terminals 1h of the mounting surface 1d. Thus, the present invention can expand the chip carrying area surrounded by the inner terminals 1h of the package-forming surface 1g for each lead 1a, and expand the carrying chip dimensions.

Description

1290764 玫、發明說明： 【發明所屬之技術領域】 本發明係關於半導體製造技術，特別係關於可有效適用 於可搭載之晶片尺寸之擴大化之技術。 【先前技術】 作為謀求小型化之半導體裝置，已經開發出比所謂qfn (Quad Flat Non-leaded package :扁平式四邊無接腳型封裝 體）之半導體晶片略大程度之小型半導體封裝體，構成外部 端子之多數導線露出配置於樹脂模塑所形成之封裝部背面 之周緣邵’此種構造之半導體封裝體稱為周邊型。 在QFN中’各導線露出封裝邵背面，各導線與封裝用樹 脂之接合面積非常小，因此，為了提高各導線與封裝部之 接合強度，各種措施紛紛出現。 另外，有關QFN之構造，例如，曾記載於株式會社press J ⑽ rnal 1998年 7 月 27日發行、「月刊Semic〇nduct〇r w〇dd 增刊號’ 99半導體組裝·檢查技術」、53〜S7頁。 在QFN中，如圖14之比較例所示，各導線丨a露出封裝部3 之背面3 a而具有作為外邵端子之機能之被安裝面丨d之延伸 方向長度P與位於其相反側而被樹脂封裝部覆蓋之封裝部 形成面lg之長度Q相比，具有Q-P之關係。 此係由於在各導線1 a之封裝部形成面丨§形成有用於防止 導線切斷時之應力施加至配線接合部，且增強對各；辟之 水平方向之抗拉強度之多數凹部lm，因此，封裝部形成面 lg之長度Q變長，其結果呈現Q-P之關係。 85943 1290764 示之導線架i組裝，且在此導線架丨之單方之面侧以樹脂模 塑法形成封裝部3之單面模塑之樹脂封裝型之小型半導體 封裝體。另外，亦係一種使多數導線“之被安裝面比露出 配置於封裝部3之背面3a之周緣部之周邊型半導體裝置。茲 列舉QFM5作為前述半導體裝置之一例加以說明。 级 口此，QFN5i各導線la兼具埋入封裝部3之内導線與露 出封裝部3之背面3a之周緣部之外導線兩者之機能。 又，圖2所示之QFN5係將晶片搭載部之支持片化以半蝕 刻法等削掉其背面U而形成導線la之一半程度之厚度，因 此、，=裝用樹脂也能進入支持片lb背面丨丨施行樹脂^塑。 也就是說，QFN5雖採用支持片lb被埋入封裝部3之支持片 埋^構造，但也可採用使支持片。之背面u露出封裝部3 之背面3a之支持片露出型構造。 另外，QFN5雖採用支持片lb之大小小於半㈣晶片^之 大小之小支持片構造，但QFN5並不限於採用Ή持片構造 ，支持片lb之大也可與半導體晶片2之大小同等在其之上。 就圖1、圖2所示之qFN5之構成加以說明時，係由具有支 持半導體晶片2之晶片支持面le，且在此晶片支持心搭載 丰導體晶片2之支持片1b、將半導體晶片2樹脂封裝而形成 封衣4 3支持支持片lb之支持片ib懸吊導線le、具有露 出封农4 3足背面3a之周緣部之被安裝面id與配置於其相 反側且接觸於封裝部3侧面％之封裝部形成面k之多數導 、泉la、及連接半導體晶片2之作為表面電極之墊。與對 此之導線1a之多數配線4所構成，將多數導線la中才目對向\己 85943 1290764 置之導線la彼此之封裝部形成面lg之内侧端部lh間之長度 Μ形成長於被安裝面Id之内侧端部lh間之長度L。 即，如圖2所示，各導線la在各相對向之導線la間形成長 度从> 長度L。 又，在各導線la中，封裝部形成面lg之長度Q<被安裝面 Id之長度P。 藉此，可擴大各導線1 a之封裝部形成面1 g之内側端部1 h 所包圍形成之晶片搭載區域，謀求可搭載之晶片尺寸之擴 大化，其結果，不必改變封裝體尺寸，即謀求可搭載之晶 片尺寸之擴大化。 因此，可搭載更大之半導體晶片2。 在此，利用圖2所示之本實施形態1之QFN5與圖14所示之 比較例之QFN型半導體裝置，比較各可搭載之晶片尺寸之 最大值時，首先，在圖14所示之比較例之Q f N型半導體裝 置中，假設相對向配置之導線1 a彼此之被安裝面1 d之内侧 端邵1 h間之長度L為3 mm時，封裝部形成面1 g之内侧端部 1 li間之長度Μ為2 · 9 mm，考慮晶片接合之搭載精度時，距 離半導體晶片2之緣需要〇, 1 mm之容限，可搭載之晶片尺寸 之最大值 N為長度 M—0.2 mm=2.7 mm(即 2.7 mm X 2 7 mm)。 相對地，本實施形態1之圖2所示之QFN5之情形，假設封 裝體尺寸相同，將相對向配置之導線1 a彼此之被安裝面j d 之内侧端部lh間之長度L同樣設定為3 mm時，封裝部形成 面1 g之内侧端部1 h間之長度Μ為3.2 mm，其結果，可摔:載 之晶片尺寸之最大值N為3.0 mm(即3.0 mm X 3.0 mm)。 85943 -10 - 1290764 線厚度方向呈現倒台形形狀。 因此，提高導線la對封裝體垂直方向之抗拉強度。 又，'^口 圖 2 戶f ~7~"- _ V不’+導體晶片2係利用接合材料（例如銀膏 寺:定於支持片lb之晶片支持面〗c上。 、卜在排列配置於QFN5之封裝部3之背面3a之周緣部 知子之導線la之被安裝面ld，形成有厚pm程度之 坪料電鍍層6。 又，支持片lb、支持片懸吊導線le及各導線“係利用例 如鋼等薄板材科所形成，其厚度為0.15〜0.2 _之程度。 另外，連接半導體晶片2之墊2a與對應於此之導線la之配 線4例如係使用金線等。 又，封裝部3係利用模塑法之樹脂封裝所形成，其時所使 用义封裝用樹脂例如為熱硬化性之環氧樹脂等。 其次，說明有關本實施形態rQFN5(半導體裝置）之製造 方法。 首先’準備圖7所示之導線架i而該導線架i係包含可支持 半導體晶片2之支持片lb、去转Φ姓gik、丄 行斤it)爻待支持片16<支持片懸吊導線 le、與配置於支持片lb之周圍之多數導線u，且將相對向 配置之導線la彼此之封裝部形成面lg之内側端部化間之長 度形成長於被安裝面1 d之内側端部i h間之長产。 即’如圖2所示，準備各導線la分別呈現封又裝部形成面1§ 之長度Q〈被安裝面Id之長度P之導線架1。 又，在導線架1如圖7所示，形成查,丨八士 u 成^刀支持片lb及其周圍 之導線la之切斷部。又，圖7所示點線部 禾口!為梃塑後之模塑緯 85943 -12 - 1290764 lk 〇 一另外，導線架丨係可由i塊導線架丨製造多數個qfn5之詩 :狀〈細長之多連式構造，另外’可在i塊導線架^上以矩 陣排列方式製造QFN5,因此，在1塊導線架！上，可利用矩 陣排列方式形成多數個對應於1個QFN5之封裝區域。 又’在導線架1係利用例如銅（Cu)等所形成之薄板材料， 其=度例如為0.15〜〇.2議之程度，但前述材料及前述厚 度等均不受此等所限定。 其後，準備在主面2b形成有半導體積體電触 μ. 〇 ^ u 口〜卞寸自豆曰曰 斤2 半導體晶片2配置 f双寸、'果ia又各封裝邵形成面 内側端部lh所圍成之區域内之支持面lb上。 其後，施行接合半導體晶片2之背面。與支持片比之晶片 支持面ic之晶片接合（又稱晶片焊接或晶片安裝）。" 即，將半導體晶片2搭載於導線架丨之支持片。之晶 持面1 c。 其時，使主面π朝上，經由晶片接合材料（例如銀膏 將半導體晶片2固定於導線架1之支持片lb。 接著，如圖2所示，利用配線4連接半導體晶片]之墊u逝 對應於此之圖4所示之導線1&之封裝部形成面1§之接合點 1 f附近。 … 其後，利用樹脂模塑（在此使用傳遞模塑）法將半導體晶 2及多數配線4樹脂封裝而在導線架丨之封壯 4曰曰 〜τ及哔形成面lg 形成封裝部3(施行單面膜塑）。 其時’係利用使多數導線la之被安裝面啦出排列於封 85943 13 - 1290764 裝部3之背面3a之周緣部之方式施行樹脂模塑。 在此，利用成型模具8(參照圖35)之模腔〜與QFN5以〗比ι 相對應之單片模塑型之前述成型模具8施行樹脂模塑。 藉此，以矩陣配置方式將多數封裝部3形成於導線架〗上。 其後，施行由導線架1切斷分離從封裝部3突出之各導線 la及支持片懸吊導線le之導線切斷（單片化）。 在此，係沿著導線架1之切斷部。切斷各導線la，取得圖 2所示之QFN5。 其/人’說明本實施形態1之變形例之QFN5。 圖8、圖9係表示變形例tQFN5，又，圖1〇〜圖12係表示 變形例之QFN5之各導線ia<形狀。 即，圖8、圖9所示之QFN5雖構造與圖2所示之qfn5大致 相同，但不同之點在於各導線丨&之封裝部形成面〗$之形狀 在各導線la之封裝邵形成面lg之内侧端部lh形成有圖12 所示之缺口部Η。 也就是說’在各導線丨a之封裝部形成面丨g之内侧角部設 有具有由封裝邵形成面1 g下陷之階差部之缺口部1 i。 利用设置此缺口部丨i，可將相對向配置之導線丨a彼此之 封裝部形成面lg之内侧端部lh間之長度Μ形成長於被安裝 面Id之内側端邵^間之長度L，而與與圖2所示之qFN5同樣 地’各導線1a呈現封裝部形成面lg之長度Q<被安裝面Id 之長度P。 又’在圖9所示之變形例之QFN5中，在各導線la中，將 配線4連接於由封裝部形成面“下陷之缺口部^。 85943 -14 - 1290764 因此，如圖13所示，在配線接合時，有必要認清半導體 晶片2之端部與毛細管7之間隔Q而以可使焊接工具之毛細 T7進入料la之缺口 #1ι之方式設定可搭載之晶片尺寸。 二例如，使封裝體尺寸與如圖2所示之QFN5相同，且認清 則述間隔Q(例如設定Q=〇 〇5 mm程度）而算出可搭载之晶片. 尺寸。首S ’如圖9所示’假設相對向配置之導線u彼此之 被安裝面1(1之内側端部lh間之長“同樣為3随時，封裝* 邵形成面1§之内側端部_之長度_ 3 84 _，考慮晶片 接合之搭載精度與配線接合之可接合性時，距離半導體晶 片2之緣需要〇.32 mm之容限，可搭載之晶片尺寸之最大^ 為長度M-〇.64 mm=3 2咖（即3 2咖以2叫。 此時’因在導線la之封裝部形成面1§之内側端部h形成 有缺口料，故與圖2所示之⑽5相比時，也可搭載更大之 半導體晶片2。 又’由於圖9所示之變形例之QFN5之其他構造及組裝方 法以及其他作用效果均與圖2所示之卿5相同，故省略重# 複之說明。 (實施形態2) 本實施形態2係說明有關與實施形態」所說明之卿5大· 致相同構造之QFN9。 錢 圖15係在採用將圖16所示之支持片lb形成小於半導體晶 片2〈王面2b(小支持片構造，且將封裝部3之/部分配置 於支持片ib之背面u側之支持片埋入型構造之qfN9中，表 示此QFN9组裝中樹脂模塑時之樹脂(封裝用樹脂)之流動狀 85943 -15 - Ϊ290764 感。即，晶片尺寸增大時，在半導體晶片2背面2c侧，封壯 用樹脂較難以進人支持片lb之侧面與導線㈣之區域，= 本實施形態2之QFN9如圖16所示，由於利用半蝕刻等對^ 持片lb之背面U施行薄化加工，在樹脂模塑時，也可使封 裳用樹脂進入支持片1 b之背面11侧。 ^ 因此，在支持片lb之背面m則，封裝用樹脂可沿著圖15 所示之樹脂流動方worn結果’可使封裝用樹脂進 入晶片背面之支持片lb之侧面與導線“間之區域，防止在 前述區域產生空隙。 又，作為薄化支持片ib之背面Η之加工方法，也可採用 壓印加工。又，在圖15及圖16所示之qFN9中，因未施以支 持片拱起加工，故支持片：^之晶片搭載侧之面之晶片支持 面lc與各導線la之封裝部形成面1§被配置於相同高度。、 其次，如圖17所示之變形例之QFN9係採用施以支持片拱 起加工之支持片埋人型構造，支持片11}之晶片支持面㈣ 配置於由導線1 a之封裝部形成面丨g向晶片主面侧之方向遠 離心位置。此時，與圖15所示之QFN9同樣地，在支持片讣 之背面11侧，封裝用樹脂可沿著圖15所示之樹脂流動方向 ίο流入，故可使封裝用樹脂進入晶片背面之支持片ib之側 面與導線1 a間之區域，防止在前述區域產生空隙。 因此，在搭載晶片端部接近導線la之大尺寸之半導體晶 片2之QFN9中，施行薄化支持片比或支持片拱起加工可有 效降低在晶片背面之支持片丨13侧面所形成之空隙。 其次，說明有關本實施形態2之qFN9之導線形狀。 85943 -16 - 1290764 成基端邵lp而使封裝部形成面之見度、交乍 藉此可提高導線1 a在其延伸方向之抗拉強度’防止導線 la由封裝部3脫落。 又，在配線接合部lq中，封裝部形成面1g之寬度形成比 其相反側之被安裝面1 d寬，配線接合部1 q之導線1 a之寬方 向之剖面形狀如圖21所示，係呈現上底之長度比下底更長 之逆向之略呈台形形狀。 藉此可提高導線1 a對封裝體厚度方向之抗拉強度。 又，本實施形態2之QFN9之導線la在其導線圖案之加工 中，採用蝕刻加工法，在蝕刻加工之際，由於係由導線1 a 之表背面兩侧塗敷蝕刻液，故可由表背兩面侧削蝕導線1 a。 因此，在圖21及圖22所示之各導線之剖面形狀中，在各 導線1 a之厚度方向之中央附近形成彎曲結合部丨r，可利用 此、弯曲結合部1 r謀求導線1 a之強度之提高與抗拉強度之提 高。 又’導線圖案之加工並非限定於蝕刻加工，也可採用衝 壓加工。 其次，說明本實施形態2之圖23〜圖34所示之各種變形例 之導線形狀。 圖23〜圖25所示之導線la在外形上與圖18〜圖2〇所示之 導線la相同，如圖25所示，在導線ia之延伸、 士土 、 万向之封裝部 形成面lg與被安裝面Id中，由各模塑線丨丨 任、 晶片側端部之 長度呈現長度R<長度Ρ，另外，在配線接八 按。。卩lq之封裝部 形成面lg並未形成如圖19所示之凹部im， #装部形成面1 g 85943 -19 - 1290764 列万式形成多數個對應於1個(^]?]^9之封裝區域。 其後，施行步驟S2所示之晶片接合。 在此係準備在主面2b形成有半導體積體電路之半導體 曰曰片2，將半導體晶片2配置於多數導線la之各封装部形成 面lg之内側端邵lh所圍成之區域内之支持片汕上。 ，、後她行接合半導體晶片2之背面仏與支持片lb之晶片 支持面lc之晶片接合（又稱晶片焊接或晶片安裝” 即，將半導體晶片2搭載於導線架丨之支持片讣之晶片支 持面1 c 〇 其時，使王面2b朝上，經由晶片接合材料（例如銀膏等） 、接合薄膜（接著膠帶等）將半導體晶片2固定於導線架丨之支 持片lb。 接著，施行步騾S3所示之配線接合。 在此，係利用金線等之導電性之配線4以配線接合連接半 導體曰曰片2之墊2a與對應於此之圖19所示之導線la之凹部 1 m内侧區域之封裝邵形成面丨g之接合點丨f附近。 其時，首先，施行連接半導體晶片2之塾2a與配線4之第^ 接合，其後，施行連接配線4與導線la之配線接合部lq之封 裝部形成面1 g之凹邵1 m内侧之接合點1 〇付近之第2接合。 在岫述第2接合中，如圖36所示，將配線4壓斷而連接於 導線1 a ’故需要有比第1接合之區域更寬之面積之區域，但 在本κ知形悲2之導線1 a之情形，由於在導線1 a之封裝部形 成面1 g僅形成1個凹部1 m，故容易確保第2接合之區域，容 易施行第2接合。 85943 -22- 1290764 配置之導線la彼此之封裝部形成面lg之内側端部lh間之長 度Μ形成長於被安裝面ld之内侧端部1}1間之長度^，故長度 Μ >長度L ’其結果，可擴大各導線1 a之封裝部形成面1 g之 内侧端部lh所圍成之晶片搭載區域，不必改變封裝體尺寸 ’即可謀求可搭載之晶片尺寸之擴大化，但在此種半導體 裝置中，本實施形態3tQFN15如圖39或圖41所示，搭載著 晶片端部接近於各導線la之程度之大的半導體晶片2。 此時’隨著半導體晶片2之增大，其放熱性也有提高之必 要’因此’採用使支持片lb由封裝部3之背面3a露出，並增 大至與半導體晶片2大致相同大小之構造。 圖39、圖40所示之QFN15係採用略大於半導體晶片2之支 持片lb，使此支持片11}由封裝部3之背面3a露出，其結果， 可提南Q F N1 5之放熱性。 又’圖41、圖42所示之QFN1 5係採用略小於半導體晶片2 之支持片lb之情形，利用使此支持片11}由封裝部3之背面3a 露出，可以提高QFN15之放熱性。 又’如圖43之局部放大声面圖所示，在半導體晶片2懸吊 在支持片lb外侧之構造之qFN1 5之情形，半導體晶片2由支 持片lb之端邵突出之長度（懸吊長度：R)最妤在導線la之被 士裝面1 d之導線延伸方向之長度s以下。即，最好Rgs。 因此，可抑制半導體晶片2由支持片ib之端部突出之長度 ，其結果，可在晶片端邵與導線1 a之内侧端部1 h間形成間 隙T。因此，在樹脂模塑時，也可使封裝用樹脂進入半導體 晶片2之背面2c側之支持片比之侧面，藉以防止在支持片lb 85943 -27- 1290764 之侧面產生空隙。 (實施形態4) 本實施形態4係利用謀求QFN構造之半導體裝置之更小 型化之技術，提供主要可謀求GND電位等固定電位之穩定 化之半導體裝置。茲列舉具有裝設可藉高頻率啟動之電路 之半導f豆晶片2之QFN16作為一例加以說明。 即，實施形態1所說明之圖2所示之QFN5，將相對向配置 之導線1 a彼此之封裝邵形成面丨g之内侧端部丨h間之長度M 形成長於被安裝面Id之内侧端部lh間之長度[，其結果，可 擴大各導線1 a之封裝部形成面丨g之内侧端部丨h所圍成之晶 片搭載區域，謀求可搭載之晶片尺寸之擴大化而不必改變 封裝體尺寸大小。但在此種半導體裝置中，本實施形態4之 QFN16係在不增加分配至導線丨a之GND端子等共通端子而 使用支持片懸吊導線le之一部分作為共通端子用之外部端 子，以謀求GND電位等固定電位之穩定化。 因此，利用使用支持片懸吊導線丨e之一部分作為gND用 之外部端子，也可使以往分配至導線latGND用導線成為 空的導線，藉此可減少導線數，謀求半導體裝置之小型化。 圖44、圖45所示之QFN16係與圖2所示之QFN5同樣地， 將相對向配置之導線丨a彼此之封裝部形成面丨g之内侧端部 1 h間之長度Μ形成長於被安裝面1 d之内侧端部1 h間之長度 L ’其結果，可擴大各導線la之封裝部形成面lg之内側端部 lh所圍成之晶片搭載區域，並在與支持片懸吊導線（懸吊導 線）le之被安裝面ln之相反側之面之上面lq之前述被安裝 85943 -28 - 1290764 面In相對向之區域，連接一端連接於半導體晶片2之墊。之 導電性配線4之他端。 即，利用配線4連接半導體晶片2之gND用之墊2a與支持 片懸吊導線le，由於4條支持片懸吊導線“分別連接於支持 片lb，故可使用4條支持片懸吊導線le作為gnD用之外部端 子。 其時，配線4連接於支持片懸吊導線^之處為支持片懸吊 導線le之露出部1ρ與前述被安裝面ιη相對向之上面。 即，如圖45所示，在支持片懸吊導線^之板厚方向中未 施行偏心處理之處（例如未施行板厚之變更或彎曲加工等 之處）連接配線4。圖45所示之QFN16係將支持片ib及支持 片懸吊導線1 e之一部分施行半|虫刻處理，而在支持片释吊 導線le之板厚不變之露出部ip連接配線4。 又，對支持片懸吊導線1 e之配線接合動作為了提高配線 接合時之穩定性’最好接合在支持片懸吊導線1 e儘量靠近 外側之處。此係為使配線接合時之熱塊確實密接於露出部 lp之故，藉此，可使配線接合時之熱及超音波由支持片懸 吊導線le之露出部lp確實傳達而使支持片懸吊導線le之配 線接合動作得以穩定。 另外’也可應付半導體晶片2之大型化之需要，因此，配 線接合動作最好接合在支持片懸吊導線1 e儘量靠近外側之 處。 又，在QFN16之支持片懸吊導線le之露出部lp之上面lq ，於其配線4之連接處之外侧，形成有狹缝之凹部1 r。此凹 85943 -29- 1290764 4 !· r係在圖4 6及圖4 7所示樹脂模塑後之構造中切斷導線之 際’利用拉扯而切斷支持片懸吊導線le時，用於緩和施加 至支持片懸吊導線le之配線4之連接處之應力。 即’利用拉扯支持片懸吊導線1 e而切斷之動作係利用對 圖47所示之支持片懸吊導線1 6之缺口部丨11施加旋轉應力而 拉扯而切斷之動作，其時，使切斷時之導線厚度方向之應 力集中於凹部1 r，以防止切斷應力施加至配線4之連接處， 藉此可防止支持片懸吊導線1 e切斷時之配線剝落之發生。 另外’可藉凹部1 r延長支持片懸吊導線1 e上之戌漏流徑 ’降低沿著支持片懸吊導線1 e入侵之水份。 又’在支持片懸吊導線le之露出部lp之配線4之連接處外 侧之兩側面設有突起部i s。此突起部丨s與凹部lr同樣地係在 利用拉扯而切斷支持片懸吊導線le時，用於緩和施加至支 持片懸吊導線1 e之配線4之連接處之應力，但也用於緩和切 斷支持片懸吊導線1 e時之導線水平方向之應力。即，切斷 支持片懸吊導線le時，此突起部18可承受導線水平方向之 切斷應力’防止切斷應力施加至配線4之連接處。 另外，也可藉此突起部ls延長支持片懸吊導線le上之戌 漏/見控’降低沿著支持片懸吊導線丨e入侵之水份。 又，如圖50及圖51之變形例之qFN16所示，在支持片懸 吊導線le之露出部1]3之上面lq之配線4之連接處内側，也可 形成另一個凹邯11。此形成於配線4之連接處内側之凹部h 係在QFN16安裝於安裝基板17(參照圖53)之狀態下之可靠 性試驗（溫度循環試驗）時，用於吸收其熱應力，可防止可 85943 -30 - 1290764 性試驗時，熱應力施加至配線4之連接處。 又，本實施形態4之QFN16在使用支持片懸吊導線le作為 GND用之外部端子之際，為了不減少導線丨a之數，在封裝 邵3之背面3a之4個角部之倒角部3c配置支持片懸吊導線le 之鉻出邰lp之被安裝面。 即，在原來之QFN構造之半導體裝置中，支持片懸吊導 線le係被配置於封裝部3之角部，利用此方式在封裝部3之 角部配置支持片懸吊導線1 e之露出部丨p之被安裝面1 n，以 此被安裝面In作為GND用之外部端子時，可不必減少導線 la<數。換言之，使用支持片懸吊導線le作為gnd用之外 部端子時’也可使以往分配至導線丨&之Gnd用導線成為空 的導線，可減少導線數，謀求半導體裝置之小型化。 藉此，可減少QFN16之安裝面積。 又，如圖48及圖49之變形例<qFN16係採用施行使支持 片lb之位置高於導線“之支持片拱起加工之構造，藉此可 形成利用封裝部3封裝支持片lb之支持片埋入型構造。又， 如圖44及圖45之QFN 16係施行半|虫刻加工，以形成較薄之 支持片lb之背面，此情形也可形成利用封裝部3封裝支持片 lb之支持片埋入型構造。 如此，採用支持片埋入型構造時，支持片lb並未露出封 裝部3之背面3a，故在圖53所示之安裝基板17中，也可將配 線繞接至對應於QFN安裝時之支持片。之下方之區域，提 高在安裝基板1 7之配線繞接之自由度。 足 其次，利用圖52及圖53，說明QFN安裝時之外部端子（導 85943 -31 - 1290764 線1 a及支持片懸吊導線le)與安裝基板17之端子17a之配置 關係。 首先’如圖5 2所示，支持片懸吊導線1 e之露出部1 p之導 線延伸方向之被安裝面In之長度U最好比支持片懸吊導線 le之露出邵lp之厚度為長。以一例表示時，露出部Ip之板 一 厚（導線架1之板厚）為 0.2 mm時，U=0.5 5 mm。但露出部 lp 之厚度及長度U並非限定於此等數值。 如此’延長支持片懸吊導線le之露出部lp之長度U時，可 鲁 增加與安裝基板17之端子17a之連接面積，故可提高QFN16 之放熱性。 但，在支持片懸吊導線le之露出部lp之被安裝面In之内 侧區域，與鄰接之導線1 a之最短距離部係被封裝部3所封裝 。即’考慮放熱性時，露出部1 p之被安裝面1 η固然以長長 地向内侧延伸較為理想，但如圖52所示，由於配置有鄰接 於支持片懸吊導線1 e之兩侧之導線1 a，故必須注意焊料洩 漏之問題。 _ 因此，事先利用被封裝部3封裝支持片懸吊導線1 e之被安 裝面1 η之内侧區域中與鄰接之導線1 a之最短距離部時，即 ， 可防止安裝時之焊料洩漏至安裝基板17。 μ 另外，與鄰接於支持片懸吊導線le之導線la連接之安裝 基板17之端子17a如圖53所示，其内侧端部最好配置於 與導線1 a之被安裝面1 d之内侧端部1 h同一面或其外侧。 即，將QFN16安裝於安裝基板17之際，利用將安裝基板 17之端子17a之内侧端部1 7b配置於與對應於此之導線1 &之 85943 -32 - 1290764 被安裝面Id之内侧端部ih同一面或其遠離之外侧時，可防 止安裝基板17之端子17a接近至接觸於支持片懸吊導線^ 之露出部lp之程度，可防止安裝時之焊料洩漏至安裝基板 17 〇 其次，說明本實施形態4之QFN16之電的特性之檢查情形。 圖54及圖55係表示有關QFN16之電的特性之檢查方法， 在檢查之際，如圖56及圖57所示，將QFN16配置於插座18 之本體18a之定位台18c，關上蓋部18b，利用封裝體壓板I” 壓住QFN16而將QFN16裝定於插座18。 藉此，如圖55所示，可使接觸端腳I8e與支持片懸吊導線 le之露出部lp之被安裝面In相接觸，以施行電的特性之檢 查。 其時’如圖5 8所示’在由獨立之GND用之導線1 a，經由 墊2a及高頻放大器2d，將GND電位供應至高頻之a電路之狀 態，加上由共通端子之支持片懸吊導線le之露出部lp經由 螯2a及南頻放大器2d’將GND電位供應至高頻之a電路，以 施行測試。 如此，充分供應GND電位，以謀求GND電位之穩定化， 並利用確保A電路之高頻特性之條件施行測試，可改善半導 體晶片2之高頻特性。即，可利用更接近於實際使用作為製 品之狀態，對高頻之A電路之特性施行測試。 又’將QFN16裝定於插座18之際，由於訊號用之接觸端 腳1 8e也接觸於各訊號用之導線1 a，故可依需要經由特定之 導線1 a輸入電訊號，以施行所希望之電的特性之檢查。 85943 -33 - 1290764 (實施形態5) 圖59係表示本實施形態5之QFN19之構造，QFN19雖將配 線4連接至支持片懸吊導線丨e，但在各導線丨a中，圖2所示 <被安裝面Id之長度p與封裝部形成面1§之長度q之關係 並非P> Q，而係P二q之情形。 即’具有被安裝面14與封裝部形成面lg之長度相等之構 造。 在此種構造之QFNl9t，也可利用將配線4連接至支持片 懸吊導線le之技術及在支持片懸吊導線&設置凹部ir、it 及尖起p卩Is之技術，獲得與實施形態4之相同之效果。 以上，已就本發明人所創見之發明，依據實施形態予以 具體說明’但本發明並不僅限定於前述實施形態、，在不脫 雄其要曰之範圍内，當然可作種種適當之變更。 例如，在前述實施形態1中，係說明利用以矩陣排列形成 有夕數個如圖7所π之封裝體區_ (切斷部“圍成之區域）之 ㈣架1組裝㈣5之情形，但就半導體裝置（QFN5)之組裝 而言，也可利用前逑封裝體區域多數個排成丨行所形成之詩 籤狀之多連式導線架丨予以組裝。 又，在實施形態4所說明之支持片懸吊導線u設置凹心 、哭起部Is ’以緩和施加至配線4之連接處之應力之技 術方面，並㈣定於QFN構造之半導體裝置，只要屬 導線型之半導f4裝置，也可適料導線u向相對向之 延伸之半導體裝置。 向 產業上之可利用性 85943 -34- 1290764 如以上所述，本發明之半導體裝置適合於使用作為各導 線之一部分露出配置於封裝部之背面之端部之非導線型之 半導體裝置，尤其適合於導線向4方向延伸之qfn。 【圖式簡單說明】 圖1係透過封裝部顯示本發明之實施形態丨之半導體裝置 (QFN)之構造之導線架構造之一例之平面圖，圖2係圖i所示 之QFN構造之剖面圖，圖3係表示圖丨所示之qfn之組裝所 使用4導線架之導線構造之放大局部底面圖，.圖4係圖3所 π導線（放大局部平面圖，圖5係圖3所示導線之放大局部 剖面圖，圖6係圖4所示導線之沿Α-Α線之剖面圖，圖7係表 示圖1所示之QFN之組裝所使用之導線架之導線構造之一 例之局部平面圖，圖8係透過封裝部顯示本發明之實施形態 1之又形例之半導體裝置（QFN)之構造之導線架構造之平面 圖圖9係®8所tf之QFN構造之剖面圖，圖1〇係表示圖8所 示之QFN之組裝所使用之導線架之導線構造之放大局部底 面圖，圖11係圖_示導線之放大局部平面圖，圖12係圖 11所示寸、、泉之放大局邯剖面圖，圖丨3係表示圖8所示之qfN 之組裝中配線接合時之半導體晶片與毛細管之間隔之一例 之局邛ί、!ΐ面圖，圖14係表示對本發明之實施形態1之之 比較例之QFN之構造之剖φ圖，圖} 5係表示本發明之實施 形態2之QFN之封裝用樹脂之流動狀態之一例之平面圖，圖 16係圖15所示之qFN構造之剖面圖，圖⑺系本發明之實施 形態2之變形例之半導體裝置（QFN)之構造之剖面圖，圖18 係表7F圖1 5所不之QFN之組裝所使用之導線架之導線構造 85943 -35 - 1290764 之放大局部底面圖，圖19你同1 Q -、苦a、 口係圖18所不導線之放大局部平面 圖，圖20係圖18所示導線之放大局部剖面圖，圖21係圖19 所示導線之沿j-j線之剖面圖，圖22係圖19所示導線之^ B-B線之剖面圖’圖23、圖26、圖29及圖如表示本發明之 實施形態2之變形例之導線構造之放大局部底面圖，圖μ、 圖27圖30及圖33係各導線之放大局部平面圖，圖25、圖 28、圖31及圖34係各導線之放大局部剖面圖，圖35係圖15 所示之QFN(單片模塑型）之組裝步驟之—例之製程流程圖 ，圖36係表示圖35所示之組裝中配線接合時之構造之一例 (放大局部剖面圖，圖37係表示本發明之實施形態2之變形 例（-次模塑型）之組裝步驟之製程流程圖，圖38係表示圖” 所示之组裝中樹脂模塑時之構造之一例之局部剖面圖與放 大局斗d面圖，圖3 9係透過封裝部顯示本發明之實施形態3 IQFN之構造之一例之平面圖，圖4〇係圖39所示之構 造心剖面圖，圖41係透過封裝部顯示本發明之實施形態3之 變形例之QFN之構造之平面圖，圖42係圖41所示之QFN構 造之剖面圖’圖43係圖42所示之c部構造之放大局部剖面圖 圖44係透過封裝邵顯示本發明之實施形態4之QFN之構造 之例之平面圖，圖45係沿著圖44所示之D-D線切斷之構造 之面圖，圖46係透過封裝部類示圖44所示之qFN組裝中 树月曰模塑後之構造之一例之局部平面圖，圖W係沿著圖# 所示之E-E線切斷之構造之局部剖面圖，圖48係透過封裝部 顯示本發明之實施形態4之變形例之QFN構造之平面圖，圖 49係沿著圖48所示之F-F線切斷之構造之剖面圖，圖50係透 85943 -36- 1290764 過封裝部顯示本發明之實施形態4之變形例之QFN構造之 平面圖，圖51係沿著圖50所示之G-G線切斷之構造之剖面圖 ，圖52係對本發明之實施形態4之QFN之安裝基板之安裝構 造之各導線之被安裝面與基板端子之關係之一例之放大局 邵平面圖，圖53係表示與圖52所示之安裝構造之導線之基 板端子之連接狀態之放大局部平面圖，圖54係透過封裝部 頋777本發明之實施形態4之QFN組裝後之電的特性檢查時 之狀態之一例之平面圖，圖55係沿著圖54所示之h_h線切斷 之構k之剖面圖，圖56係透本發明之實施形態4之qFN組裝 後4電的特性檢查時之插座裝定狀態之一例之剖面圖，圖 57係表示圖56所示之部構造之放大局部剖面圖，圖58係表 示圖56所示之電的特性檢查時之咖電位之供應狀態之一 2之局部平面圖，圖59係透過封裝部顯示本發明之實施形 悲5之QFN構造之一例之平面圖。 【圖式代表符號說明】 1 導線架 la 導線 lb 支持片 1 c 晶片支持面 Id 被安裝面 1 e 懸吊導線 If 接合點 lg 封裝部形成面 1 h 内侧端部 85943 -37- 1290764 li 缺口部 Ij 切斷部 11 背面 1 m 凹部 lk 模塑線 In 端部厚部 lp 基端部 lq 配線接合部 lr 彎曲結合部 Is 突起部 It 凹部 2 半導體晶片 2a 墊 2b 主面 2c 背面 2d 高頻放大器 3 封裝部 3a 背面 3b 侧面 3c 倒角部 4 配線 6 焊料電鍍層 7 毛細管 8 成型模具 -38 85943BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly to a technique that can be effectively applied to the enlargement of a mountable wafer size. [Prior Art] As a semiconductor device for miniaturization, a small semiconductor package which is slightly larger than a semiconductor wafer of a so-called qfn (Quad Flat Non-leaded package) has been developed, and an external device is formed. A plurality of wires of the terminal are exposed to the periphery of the back surface of the package portion formed by resin molding. The semiconductor package having such a structure is referred to as a peripheral type. In the QFN, each of the wires exposes the back surface of the package, and the bonding area between each of the wires and the resin for packaging is extremely small. Therefore, various measures have appeared in order to improve the bonding strength between the wires and the package. In addition, the structure of the QFN, for example, was published on July 27, 1998 by Press J (10) rnal, "Semic〇nduct〇rw〇dd Supplement No. '99 Semiconductor Assembly and Inspection Technology", 53~S7 . In the QFN, as shown in the comparative example of FIG. 14, each of the wires 丨a is exposed on the back surface 3a of the package portion 3, and has a length P in the extending direction of the mounted surface 丨d which is a function of the outer-shoring terminal and is located on the opposite side thereof. The length Q of the encapsulation portion forming surface lg covered by the resin encapsulation portion has a QP relationship. This is because the surface of the package portion of each of the wires 1a is formed with a plurality of recesses lm for preventing stress applied to the wire bonding portions from being applied to the wire bonding portions, and enhancing the tensile strength in each of the horizontal directions. The length Q of the encapsulation portion forming surface lg becomes long, and the result exhibits a QP relationship. 85943 1290764 The lead frame i is assembled, and a single-sided molded resin-package type small semiconductor package in which the package portion 3 is formed by resin molding is formed on the one side of the lead frame. In addition, a peripheral type semiconductor device in which a plurality of wires are mounted on a peripheral portion of the back surface 3a of the package portion 3 is disclosed. As an example of the semiconductor device, QFM5 is described as an example of the semiconductor device. The wire la has both the function of embedding the inner lead wire in the package portion 3 and the lead wire outside the peripheral portion of the back surface 3a of the package portion 3. Further, the QFN5 shown in Fig. 2 is formed by dicing the support of the wafer mounting portion in half. The etching method or the like cuts off the back surface U to form a thickness of one half of the wire la. Therefore, the resin for mounting can also enter the back surface of the support sheet 1b to perform resin molding. That is, the QFN5 is supported by the support sheet lb. Although the support sheet embedded structure of the package portion 3 is embedded, the support sheet may be exposed such that the back surface u of the support sheet 3 is exposed to the back surface 3a of the package portion 3. Further, the size of the support sheet lb of the QFN 5 is less than half (four). The support structure of the wafer is small, but the QFN 5 is not limited to the structure of the support piece, and the size of the support piece lb can be equal to the size of the semiconductor wafer 2. The qFN5 shown in Fig. 1 and Fig. 2 Description of the composition In the case of the support sheet 1b having the wafer support surface supporting the semiconductor wafer 2, and supporting the conductor wafer 2 on the wafer support, the semiconductor wafer 2 is resin-packed to form a support sheet for the support tab 3b. The ib suspension wire le has a mounting surface id that exposes a peripheral portion of the back surface 3a of the sealing member, and a plurality of guides, a spring, and a sealing portion that is disposed on the opposite side of the sealing portion 3 and that is in contact with the side surface of the sealing portion 3 And a pad as a surface electrode for connecting the semiconductor wafer 2. The majority of the wires 4 of the wire 1a are formed, and the plurality of wires la are aligned with each other to form a surface of the package portion of the wires la 85943 1290764 The length Μ between the inner end portions lh is longer than the length L between the inner end portions lh of the mounted surface Id. That is, as shown in Fig. 2, each of the wires la forms a length from each of the opposite wires la > length L Further, in each of the wires la, the length of the package forming surface lg is Q <The length P of the surface to be mounted Id. Thereby, the wafer mounting region surrounded by the inner end portion 1 h of the package portion forming surface 1 g of each of the wires 1 a can be enlarged, and the size of the mountable wafer can be enlarged, and as a result, it is not necessary to change the package size. The size of the wafer that can be mounted is expanded. Therefore, a larger semiconductor wafer 2 can be mounted. Here, when the maximum value of each of the mountable wafer sizes is compared with the QFN5 of the first embodiment shown in FIG. 2 and the QFN type semiconductor device of the comparative example shown in FIG. 14, first, the comparison is shown in FIG. In the Q f N type semiconductor device of the example, it is assumed that the length L between the inner ends of the mounted surfaces 1 d of the oppositely disposed wires 1 a is 1 mm, and the inner end of the package portion 1 g is formed. The length 1 between 1 li is 2 · 9 mm. When considering the mounting accuracy of wafer bonding, the distance from the edge of the semiconductor wafer 2 is required to be 〇, the tolerance of 1 mm, and the maximum value of the size of the wafer that can be mounted is N - 0.2 mm. = 2.7 mm (ie 2.7 mm X 2 7 mm). On the other hand, in the case of the QFN 5 shown in FIG. 2 of the first embodiment, it is assumed that the package body has the same size, and the length L between the inner end portions lh of the mounted surfaces jd of the oppositely disposed wires 1 a is set to 3 as well. In the case of mm, the length Μ between the inner end portions 1 h of the package forming surface 1 g is 3.2 mm, and as a result, the maximum value N of the wafer size to be loaded is 3.0 mm (that is, 3.0 mm X 3.0 mm). 85943 -10 - 1290764 The line thickness direction is inverted. Therefore, the tensile strength of the wire la to the vertical direction of the package is increased. Moreover, the '^ port diagram 2 household f ~ 7 ~ " - _ V not ' + conductor wafer 2 is made of a bonding material (for example, silver paste temple: fixed on the wafer support surface of the support sheet lb c.) The surface to be mounted ld of the lead wire la of the peripheral portion of the back surface 3a of the encapsulation portion 3 of the QFN 5 is formed with a plating layer 6 of a thickness of pm. Further, the supporting piece lb, the supporting piece suspending wire le, and each wire are formed. It is formed by a thin plate member such as steel, and has a thickness of 0.15 to 0.2 Å. Further, the pad 2a that connects the semiconductor wafer 2 and the wiring 4 that connects the wires 1a are, for example, gold wires or the like. The encapsulating portion 3 is formed by a resin encapsulation of a molding method, and the encapsulating resin used in the present invention is, for example, a thermosetting epoxy resin or the like. Next, a method of manufacturing the rQFN 5 (semiconductor device) according to the present embodiment will be described. 'Prepare the lead frame i shown in FIG. 7 and the lead frame i includes a support piece lb that can support the semiconductor wafer 2, go to the Φ surname gik, and 丄行斤it) <Supporting the sheet suspending wire le and the plurality of wires u disposed around the support sheet 1b, and forming the length between the inner end portions of the package portion forming surface lg of the oppositely disposed wires la to be longer than the mounted surface Long-term production between the inner end ih of 1 d. That is, as shown in Fig. 2, each of the wires la is prepared to have a lead frame 1 having a length Q of the mounting portion forming surface 1 § and a length P of the mounting surface Id. Further, as shown in Fig. 7, the lead frame 1 is formed as a cut portion of the wire lb and the wire la around it. Moreover, the dotted line portion and the bottom line shown in Fig. 7 are the molding latitude 85943 -12 - 1290764 lk after the boring molding. In addition, the lead frame 可由 can be made from the i-piece lead frame 多数 many qfn5 poems: The multi-connected structure, in addition, 'QFN5 can be manufactured in a matrix arrangement on the i-piece lead frame ^, therefore, in one lead frame! In the above, a plurality of package regions corresponding to one QFN 5 can be formed by a matrix arrangement. Further, the lead frame 1 is made of, for example, copper (Cu) or the like, and the degree of the degree is, for example, 0.15 to 〇2. However, the above materials and the above-described thickness are not limited thereto. Thereafter, a semiconductor integrated body electrical contact μ is formed on the main surface 2b. 〇^u Port~卞寸自豆曰曰斤 2 The semiconductor wafer 2 is arranged in a double inch, and the fruit ia and the inner side of each package are formed. The support surface lb in the area enclosed by lh. Thereafter, the back surface of the semiconductor wafer 2 is bonded. Wafer bonding (also known as wafer soldering or wafer mounting) to a support wafer than a support wafer. " That is, the semiconductor wafer 2 is mounted on a support piece of the lead frame. Crystal holding surface 1 c. At this time, the main surface π faces upward, and the semiconductor wafer 2 is fixed to the support sheet 1b of the lead frame 1 via a wafer bonding material (for example, as shown in FIG. 2, the semiconductor wafer is connected by the wiring 4). The encapsulation portion of the wire 1 & shown in Fig. 4 is formed in the vicinity of the joint 1 f of the surface 1 §. Thereafter, the semiconductor crystal 2 and the majority are used by resin molding (here, transfer molding) The wiring 4 is resin-packed, and the package portion 3 is formed on the lead frame 封 曰曰 τ τ τ 哔 哔 形成 ( ( ( ( ( ( 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成Resin molding is performed in such a manner that the peripheral portion of the back surface 3a of the mounting portion 3 is sealed 85094 13 - 1290764. Here, the cavity of the molding die 8 (refer to FIG. 35) is molded by a single piece corresponding to QFN5. The molding die 8 of the type is subjected to resin molding. Thereby, a plurality of package portions 3 are formed on the lead frame in a matrix arrangement. Thereafter, the wires protruding from the package portion 3 are cut and separated by the lead frame 1 And the wire of the supporting piece suspension wire is cut (single piece). This is along the cut portion of the lead frame 1. The respective wires la are cut to obtain the QFN 5 shown in Fig. 2. The person/person's description of the QFN 5 according to the modification of the first embodiment is shown in Fig. 8 and Fig. 9 Example tQFN5, and FIG. 1A to FIG. 12 show the wires ia of the QFN5 of the modification. <shape. That is, the structure of the QFN 5 shown in FIGS. 8 and 9 is substantially the same as that of qfn5 shown in FIG. 2, but the difference is that the shape of the surface of the package portion of each of the wires amp & The inner end portion lh of the surface lg is formed with a notch portion 图 shown in Fig. 12. In other words, the notch portion 1 i having the step portion recessed by the package forming surface 1 g is provided at the inner corner portion of the package portion forming surface 丨g of each of the wires 丨a. By providing the notch portion 丨i, the length Μ between the inner end portions lh of the package portion forming surface lg of the oppositely disposed wires 丨a can be formed longer than the length L between the inner ends of the mounted surface Id, and Similarly to the qFN5 shown in FIG. 2, each of the wires 1a exhibits a length Q of the package forming surface lg. <The length P of the surface to be mounted Id. Further, in the QFN 5 according to the modification shown in Fig. 9, in the respective wires la, the wiring 4 is connected to the notch portion which is depressed by the surface on which the package portion is formed. 85943 - 14 - 1290764 Therefore, as shown in Fig. 13, At the time of wiring bonding, it is necessary to recognize the interval Q between the end portion of the semiconductor wafer 2 and the capillary 7, and to set the size of the wafer that can be mounted so that the capillary T7 of the bonding tool can enter the gap #1 of the material la. The size of the package is the same as that of QFN5 shown in Fig. 2, and the interval Q (for example, setting Q = 〇〇 5 mm) is used to calculate the size of the mountable wafer. The size of the first S' is shown in Figure 9. The length of the oppositely disposed wires u to be mounted on each other 1 (the length between the inner end portions l1 of 1) is also 3 at any time, the length of the inner end portion of the package * the surface 10 of the formation _ 3 _ _, considering wafer bonding When the mounting accuracy and the bondability of the wiring are bonded, a distance of 〇32 mm is required from the edge of the semiconductor wafer 2, and the maximum size of the wafer that can be mounted is the length M-〇.64 mm=3 2 coffee (ie, 3) 2 The coffee is called 2. At this time, 'the inner end portion h of the forming portion 1 of the lead portion of the wire la is formed. Therefore, when compared with (10) 5 shown in FIG. 2, a larger semiconductor wafer 2 can be mounted. Further, other structures and assembling methods of the QFN 5 according to the modification shown in FIG. 9 and other effects are the same as those in FIG. Since the description 5 is the same, the explanation is omitted. (Embodiment 2) In the second embodiment, QFN9 having the same structure as that described in the embodiment of the present invention is described. The support piece 1b shown in FIG. 16 is formed to be smaller than the semiconductor wafer 2 (the king face 2b (small support piece structure, and the portion 3 of the package portion 3 is disposed on the back side u of the support piece ib) of the support piece embedded type qfN9 In the QFN9 assembly, the resin (packaging resin) in the resin molding process has a flow pattern of 85,943 -15 - Ϊ 290,764. That is, when the wafer size is increased, the resin is sealed on the back surface 2c side of the semiconductor wafer 2 It is difficult to enter the area of the side of the support sheet lb and the wire (4), and the QFN9 of the second embodiment is thinned by the half-etching or the like on the back surface U of the holding piece lb, during resin molding. It is also possible to allow the resin for sealing to enter the side of the back surface 11 of the support sheet 1 b. ^ Therefore, on the back surface m of the support sheet lb, the encapsulating resin can be along the resin flow side shown in Fig. 15 to cause the encapsulating resin to enter the area between the side of the support sheet lb on the back side of the wafer and the conductor. It is possible to prevent voids from being formed in the above-mentioned regions. Further, as a method of processing the back surface of the thinned support piece ib, an imprint process can be used. Further, in the qFN9 shown in Figs. 15 and 16, the support piece is not provided. Since the processing is performed, the wafer supporting surface 1c of the wafer mounting side of the support sheet is placed at the same height as the package forming surface 1 of each of the wires 1a. Next, the QFN9 according to the modification shown in FIG. 17 adopts a support piece buried structure in which the support piece is arched, and the wafer support surface (4) of the support piece 11} is disposed on the surface formed by the package portion of the wire 1a.丨g is away from the center of the heart in the direction of the main surface side of the wafer. At this time, similarly to the QFN9 shown in Fig. 15, on the back surface 11 side of the support sheet, the encapsulating resin can flow in the resin flow direction shown in Fig. 15, so that the encapsulating resin can be supported on the back side of the wafer. The area between the side of the sheet ib and the wire 1 a prevents the occurrence of voids in the aforementioned area. Therefore, in the QFN9 in which the semiconductor wafer 2 having the wafer end portion close to the large size of the wiring la is mounted, the thinned support sheet ratio or the support sheet arching process can effectively reduce the gap formed on the side of the support sheet 13 on the wafer back surface. Next, the shape of the wire of the qFN 9 according to the second embodiment will be described. 85943 -16 - 1290764 is formed at the base end of the lp to make the surface of the package portion visible and intersect, thereby increasing the tensile strength of the wire 1 a in the extending direction thereof to prevent the wire la from coming off the package portion 3. Further, in the wire bonding portion 1q, the width of the package portion forming surface 1g is wider than the surface to be mounted 1d on the opposite side, and the cross-sectional shape of the wire 1a of the wire bonding portion 1b is as shown in Fig. 21, It has a slightly trapezoidal shape in which the length of the upper base is longer than the lower base. Thereby, the tensile strength of the wire 1 a in the thickness direction of the package can be improved. Further, the wire la of the QFN 9 of the second embodiment is subjected to an etching process in the processing of the wire pattern, and the etching liquid is applied to both sides of the front and back surfaces of the wire 1 a during the etching process, so that the front and back can be used. The two sides are etched the wire 1 a. Therefore, in the cross-sectional shape of each of the wires shown in Figs. 21 and 22, the curved joint portion 丨r is formed in the vicinity of the center in the thickness direction of each of the wires 1a, and the bent joint portion 1 r can be used to obtain the wire 1a. Increased strength and increased tensile strength. Further, the processing of the wire pattern is not limited to the etching process, and the stamping process can also be employed. Next, the shape of the wire of each modification shown in Figs. 23 to 34 of the second embodiment will be described. The wire la shown in FIG. 23 to FIG. 25 is identical in appearance to the wire la shown in FIGS. 18 to 2B, and as shown in FIG. 25, the surface of the package portion is formed by the extension of the wire ia, the orientation of the conductor, and the universal direction. In the surface to be mounted Id, the length of the end portion of the wafer side and the length of the end portion of the wafer are represented by the length R. <Length Ρ, in addition, the wiring is connected to eight. . The encapsulation portion forming surface lg of the 卩lq does not form the concave portion im as shown in FIG. 19, and the mounting portion forming surface 1 g 85943 -19 - 1290764 is formed by a plurality of columns corresponding to one (^]?]^9 Then, the wafer bonding shown in step S2 is performed. Here, the semiconductor wafer 2 having the semiconductor integrated circuit formed on the main surface 2b is prepared, and the semiconductor wafer 2 is placed in each package portion of the plurality of wires 1a. The inner side of the surface lg is supported on the support sheet, and then the wafer is bonded to the back surface of the semiconductor wafer 2 and the wafer support surface lc of the support sheet lb (also referred to as wafer soldering or wafer bonding). That is, the semiconductor wafer 2 is mounted on the wafer supporting surface 1 c of the support sheet of the lead frame, and the king face 2b is faced upward, via a wafer bonding material (for example, silver paste or the like), and a bonding film (following the tape) The semiconductor wafer 2 is fixed to the support sheet 1b of the lead frame. Next, the wiring bonding shown in the step S3 is performed. Here, the semiconductor wafer is connected by wire bonding using the conductive wiring 4 such as a gold wire. 2 pad 2a and FIG. 19 corresponding thereto In the vicinity of the junction point 丨f of the package forming surface 丨g of the inner portion of the recess 1 m of the conductor la, at the same time, first, the second connection of the 塾 2a and the wiring 4 connecting the semiconductor wafer 2 is performed, and thereafter, the connection is performed. The wiring 4 and the bonding portion forming surface 1 g of the wiring portion 1 of the wire 1a are joined to each other at the bonding point 1 on the inner side of the recess 1 m. In the second bonding, as shown in FIG. 36, the wiring is wired as shown in FIG. 4 is broken and connected to the wire 1 a ', so it is necessary to have a region wider than the area of the first bonding, but in the case of the wire 1 a of the κ 悲 悲 2, due to the formation of the portion of the wire 1 a Since only one recessed portion 1 m is formed in the surface 1 g, it is easy to secure the second bonded region, and the second bonding can be easily performed. 85943 -22- 1290764 The length between the inner end portions lh of the packaged portion forming surface lg of the arranged wires la The crucible is formed to have a length longer than the inner end portion 1} of the mounting surface ld, so the length Μ > the length L ', as a result, the inner end portion lh of the encapsulating portion forming surface 1 g of each of the wires 1 a can be enlarged. In the wafer mounting area, the size of the package can be mounted without changing the package size. In the semiconductor device of the present embodiment, as shown in FIG. 39 or FIG. 41, the semiconductor wafer 2 having a wafer end portion close to each of the wires la is mounted as shown in FIG. 39 or FIG. 41. When the amount of 2 is increased, the heat dissipation property is also increased. Therefore, the support sheet 1b is exposed from the back surface 3a of the package portion 3 and is increased to a structure substantially the same size as the semiconductor wafer 2. Fig. 39 and Fig. 40 are shown. The QFN 15 is slightly larger than the support piece 1b of the semiconductor wafer 2, and the support piece 11} is exposed from the back surface 3a of the package portion 3. As a result, the heat dissipation property of the south QF N1 5 can be improved. Further, in the case where the QFN1 5 shown in Figs. 41 and 42 is slightly smaller than the support sheet 1b of the semiconductor wafer 2, the heat dissipation of the QFN 15 can be improved by exposing the support sheet 11} from the back surface 3a of the package portion 3. In the case of the qFN1 5 of the structure in which the semiconductor wafer 2 is suspended outside the support sheet 1b, as shown in the partial enlarged surface view of FIG. 43, the length of the semiconductor wafer 2 protruded from the end of the support sheet 1b (suspension length) :R) Finally, the length s of the wire extending direction of the conductor 1a is less than or equal to the length s. That is, it is better to Rgs. Therefore, the length of the semiconductor wafer 2 protruding from the end portion of the supporting piece ib can be suppressed, and as a result, a gap T can be formed between the wafer end and the inner end portion 1h of the wire 1a. Therefore, at the time of resin molding, the encapsulating resin can also enter the side of the support sheet side of the back surface 2c side of the semiconductor wafer 2, thereby preventing voids from being formed on the side faces of the support sheets lb 85943 -27 - 1290764. (Embodiment 4) In the fourth embodiment, a semiconductor device which is mainly capable of stabilizing a fixed potential such as a GND potential is provided by a technique for miniaturizing a semiconductor device having a QFN structure. A QFN 16 having a semiconductor wafer 2 for mounting a circuit that can be activated by a high frequency will be described as an example. That is, in the QFN 5 shown in Fig. 2 described in the first embodiment, the length M between the inner end portions 丨h of the package forming surface 丨g of the oppositely disposed wires 1a is formed longer than the inner end of the mounted surface Id. The length of the portion lh [the result is that the wafer mounting region surrounded by the inner end portion 丨h of the package forming surface 丨g of each of the wires 1a can be enlarged, and the size of the mountable wafer can be enlarged without changing the package. Body size. However, in the semiconductor device of the fourth embodiment, the QFN 16 of the fourth embodiment is used as a common terminal for the common terminal without using a common terminal such as a GND terminal to be connected to the lead 丨a, and is used as an external terminal for the common terminal. Stabilization of a fixed potential such as a potential. Therefore, by using one of the support sheets suspending the wires 丨e as the external terminals for the gND, the wires which are conventionally distributed to the wires for the wires latGND can be made empty, whereby the number of wires can be reduced, and the size of the semiconductor device can be reduced. In the same manner as the QFN 5 shown in FIG. 2, the QFN 16 shown in FIG. 44 and FIG. 45 has a length Μ between the inner end portions 1 h of the encapsulating portion forming faces 丨g of the oppositely disposed wires 丨 a, and is formed longer than the mounting. As a result, the length L' between the inner end portions 1h of the surface 1d can be enlarged, and the wafer mounting region surrounded by the inner end portion lh of the package forming surface lg of each of the wires la can be enlarged, and the wire can be suspended with the support sheet ( The above-mentioned lq of the surface of the opposite side of the mounting surface ln of the suspension wire) is mounted on the opposite surface of the surface of the surface of the 85943-28- 1290764, and the connection end is connected to the pad of the semiconductor wafer 2. The other end of the conductive wiring 4. That is, the pad 2a for the gND of the semiconductor wafer 2 and the supporting wire suspension wire le are connected by the wiring 4, since the four supporting piece suspension wires are respectively connected to the supporting piece lb, four supporting pieces can be used to suspend the wire. As the external terminal for gnD, the wiring 4 is connected to the supporting piece suspending wire ^ where the exposed portion 1ρ of the supporting piece suspension wire le is opposed to the above-mentioned surface to be mounted. That is, as shown in Fig. 45 It is shown that the wiring 4 is connected in a place where the eccentricity is not applied in the thickness direction of the supporting piece suspension wire (for example, where the thickness of the plate is not changed or bent, etc.). The QFN16 system shown in Fig. 45 will support the piece ib. And a part of the supporting piece suspension wire 1 e is subjected to semi-insect processing, and the wiring portion 4 is connected to the exposed portion ip of the supporting piece releasing wire le. Further, the wiring of the supporting piece suspension wire 1 e In order to improve the stability at the time of wire bonding, the bonding operation is preferably joined to the support piece suspension wire 1 e as close as possible to the outside. This is to ensure that the heat block when the wire is bonded is in close contact with the exposed portion lp, thereby The heat and ultrasonic waves that can be used to join the wires The exposed portion lp of the supporting piece suspension wire le is surely transmitted to stabilize the wiring bonding operation of the supporting piece suspension wire le. In addition, the need for the enlargement of the semiconductor wafer 2 can be coped with, and therefore, the wire bonding operation is preferably bonded to The support piece suspension wire 1 e is as close as possible to the outer side. Further, on the outer side lq of the exposed portion lp of the support piece suspension wire le of the QFN 16 , a recessed portion 1 r is formed on the outer side of the connection portion of the wiring 4 This concave 85943 -29- 1290764 4 !·r is used when the wire is cut in the structure after resin molding shown in Fig. 46 and Fig. 47, when the support piece suspension wire le is cut by pulling, The stress applied to the joint of the wiring 4 supporting the sheet suspension wire le is alleviated. That is, the operation of cutting the wire 1 e by pulling the support piece is performed by using the support piece suspension wire shown in FIG. The notch portion 11 is subjected to a rotation stress and is pulled and cut. In this case, the stress in the thickness direction of the wire at the time of cutting is concentrated on the concave portion 1 r to prevent the cutting stress from being applied to the joint of the wiring 4. Prevents the support piece suspension wire 1 e from being cut The occurrence of wiring peeling occurs. In addition, the recessed flow path of the support piece suspension wire 1 e can be extended by the recess 1 r to reduce the water intrusion along the support piece suspension wire 1 e. A projection portion is provided on both sides of the outer side of the joint of the wiring 4 of the exposed portion lp of the wire le. This projection portion 丨s is similar to the recess portion lr for easing the support piece suspension wire le by pulling. The stress applied to the joint of the wiring 4 supporting the sheet suspending wire 1 e, but also used to alleviate the stress in the horizontal direction of the wire when the supporting piece suspends the wire 1 e. That is, the supporting piece is suspended. At this time, the projection 18 can withstand the cutting stress in the horizontal direction of the wire to prevent the cutting stress from being applied to the joint of the wiring 4. Alternatively, the projections ls may be used to extend the leakage/seeking on the support sheet suspension wire le to reduce the moisture intrusion along the support sheet suspension wire 丨e. Further, as shown by qFN16 in the modification of Figs. 50 and 51, another recess 11 may be formed inside the junction of the wiring 4 on the upper surface lq of the exposed portion 1] 3 of the support sheet suspension lead le. The recess h formed on the inner side of the junction of the wiring 4 is used to absorb the thermal stress when the QFN 16 is mounted on the mounting substrate 17 (see FIG. 53) in a reliability test (temperature cycle test), thereby preventing the 85943 In the -30 - 1290764 test, thermal stress is applied to the joint of the wiring 4. Further, in the QFN 16 of the fourth embodiment, when the support piece suspension wire le is used as the external terminal for GND, the chamfered portion of the four corners of the back surface 3a of the package Shao 3 is not reduced in order to reduce the number of the wires 丨a. The 3c configuration supports the mounting surface of the chrome exit lp of the sheet suspension wire le. That is, in the semiconductor device of the original QFN structure, the support sheet suspension wires are disposed at the corners of the package portion 3, and in this manner, the exposed portions of the support sheet suspension wires 1e are disposed at the corners of the package portion 3. When the mounting surface 1 n of the 丨p is used as the external terminal for the GND by the mounting surface In, it is not necessary to reduce the wire la <Number. In other words, when the support piece suspension wire le is used as the external terminal for gnd, the Gnd wire which has been conventionally distributed to the wire 丨 & can be made empty, and the number of wires can be reduced, and the size of the semiconductor device can be reduced. Thereby, the installation area of the QFN 16 can be reduced. Further, as shown in the modified examples of FIGS. 48 and 49 <qFN16 is a structure in which the support sheet lb is placed at a position higher than that of the support sheet of the lead wire, whereby the support sheet-embedded structure in which the support sheet lb is packaged by the package portion 3 can be formed. And the QFN 16 of FIG. 45 performs half-cut processing to form the back surface of the thin support sheet lb. In this case, a support sheet embedded type structure in which the support sheet lb is packaged by the package portion 3 can be formed. In the chip-embedded structure, the support sheet 1b does not expose the back surface 3a of the package portion 3. Therefore, in the mounting substrate 17 shown in FIG. 53, the wiring can be wound to the support sheet corresponding to the QFN mounting. In the area, the degree of freedom in wiring winding on the mounting substrate 17 is improved. Secondly, the external terminals of the QFN mounting are used as shown in Fig. 52 and Fig. 53 (guide 85943 -31 - 1290764 line 1 a and the supporting piece suspension wire) Le) arrangement relationship with the terminal 17a of the mounting substrate 17. First, as shown in Fig. 52, the length U of the mounted surface In in the direction in which the wire of the exposed portion 1p of the sheet suspension wire 1e is extended is preferably supported. The thickness of the exposed suspension wire le is long. In the case of the example, when the thickness of the exposed portion Ip is 0.2 mm (the thickness of the lead frame 1) is 0.2 mm, U = 0.5 5 mm. However, the thickness and length U of the exposed portion lp are not limited to these values. When the length U of the exposed portion lp of the suspension wire le is increased, the connection area with the terminal 17a of the mounting substrate 17 can be increased, so that the heat dissipation property of the QFN 16 can be improved. However, in the exposed portion lp of the supporting piece suspension wire le The innermost region of the surface to be mounted In and the shortest distance from the adjacent wire 1 a are encapsulated by the package portion 3. That is, when the heat dissipation property is considered, the mounted surface 1 η of the exposed portion 1 p is long to the inside. The extension is ideal, but as shown in Fig. 52, since the wires 1a adjacent to the both sides of the supporting piece suspension wires 1e are disposed, it is necessary to pay attention to the problem of solder leakage. _ Therefore, the package is supported by the packaged portion 3 in advance. When the shortest distance between the inner side of the surface 1 η of the mounting wire 1 η and the adjacent wire 1 a is short, that is, the solder at the time of mounting can be prevented from leaking to the mounting substrate 17. μ Further, adjacent to the supporting piece Installation of the wire la connection of the suspension wire le As shown in Fig. 53, the terminal 17a of the plate 17 is preferably disposed on the same side or outside of the inner end portion 1h of the surface 1d of the lead wire 1a. That is, the QFN 16 is mounted on the mounting substrate 17. The inner end portion 17b of the terminal 17a of the mounting substrate 17 is disposed on the same side or away from the inner end portion ih of the mounting surface Id of the wire 1 & 85943 -32 - 1290764 In this case, the terminal 17a of the mounting substrate 17 can be prevented from coming close to the exposed portion lp of the supporting piece suspension wire ^, and the solder during mounting can be prevented from leaking to the mounting substrate 17. Next, the electric power of the QFN 16 of the fourth embodiment will be described. Check the characteristics of the feature. Figs. 54 and 55 show a method of inspecting the characteristics of the electric power of the QFN 16. When the inspection is performed, as shown in Figs. 56 and 57, the QFN 16 is placed on the positioning table 18c of the main body 18a of the socket 18, and the lid portion 18b is closed. The QFN 16 is mounted on the socket 18 by pressing the QFN 16 with the package presser plate I". Thereby, as shown in Fig. 55, the contact end leg I8e can be connected to the mounted surface In of the exposed portion lp of the support piece suspension lead le Contact, to check the characteristics of the electric power. At this time, as shown in Fig. 5, 'on the wire 1 a used by the independent GND, the GND potential is supplied to the high frequency a circuit via the pad 2a and the high frequency amplifier 2d. In the state, the exposed portion lp of the supporting piece suspension wire le of the common terminal is supplied to the high frequency a circuit via the cheek 2a and the south frequency amplifier 2d' to perform the test. Thus, the GND potential is sufficiently supplied. In order to stabilize the GND potential and perform the test by the conditions for ensuring the high-frequency characteristics of the A circuit, the high-frequency characteristics of the semiconductor wafer 2 can be improved. That is, the state closer to the actual use can be utilized as the state of the product, and the high frequency can be utilized. Test the characteristics of the A circuit. Also 'QF When the N16 is mounted on the socket 18, since the contact pin 1 8e for the signal is also in contact with the wire 1 a for each signal, the electric signal can be input through the specific wire 1 a as needed to perform the desired electric power. 85943 -33 - 1290764 (Embodiment 5) FIG. 59 shows the structure of the QFN 19 of the fifth embodiment, and the QFN 19 connects the wiring 4 to the supporting piece suspension wire 丨e, but in each wire 丨a, Figure 2 shows <The relationship between the length p of the mounted surface Id and the length q of the package forming surface 1 § is not P> Q, but is the case of P2. That is, it has a configuration in which the length of the surface to be mounted 14 is equal to the length of the surface lg of the package portion. In the QFNl9t of such a configuration, the technique of connecting the wiring 4 to the supporting piece suspension wire le and the technique of providing the concave wire ir, it and the sharpening p卩Is in the supporting piece suspension wire can also be obtained and implemented. 4 the same effect. As described above, the present invention has been described in detail with reference to the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the scope of the invention. For example, in the first embodiment, the case where the (four) frame 1 assembly (four) 5 of the package area _ (the area enclosed by the cut portion) of the π group as shown in FIG. 7 is formed by matrix arrangement is described. In the assembly of the semiconductor device (QFN5), it is also possible to assemble a multi-connected lead frame formed by a plurality of pouches arranged in a row in the front package area. The support piece suspending wire u is provided with a concave core, a weeping portion Is 'to ease the technical aspect of the stress applied to the joint of the wiring 4, and (4) a semiconductor device set for the QFN structure, as long as it is a wire type semi-conductive f4 device, It is also possible to accommodate a semiconductor device in which the wire u is extended to the opposite direction. Industrial Applicability 85943 - 34 - 1290764 As described above, the semiconductor device of the present invention is suitable for use as a part of each of the wires and exposed to the package portion The non-conducting type semiconductor device at the end of the back surface is particularly suitable for the qfn in which the wires extend in the four directions. [Brief Description of the Drawings] FIG. 1 is a semiconductor device showing an embodiment of the present invention through a package portion. (QFN) is a plan view of an example of a lead frame structure, FIG. 2 is a cross-sectional view of the QFN structure shown in FIG. 1, and FIG. 3 is an enlarged view showing the wire structure of the 4-conductor used in the assembly of qfn shown in FIG. Figure 4 is a π-ray of Figure 3 (enlarged partial plan view, Figure 5 is an enlarged partial cross-sectional view of the wire shown in Figure 3, Figure 6 is a cross-sectional view of the wire along the Α-Α line shown in Figure 4, Fig. 7 is a partial plan view showing an example of a lead structure of a lead frame used for assembling the QFN shown in Fig. 1, and Fig. 8 is a view showing a semiconductor device (QFN) according to a still further embodiment of the first embodiment of the present invention. FIG. 9 is a cross-sectional view showing the QFN structure of the tf of the QFN, and FIG. 1 is an enlarged partial bottom view showing the wire structure of the lead frame used for assembling the QFN shown in FIG. Figure _ shows an enlarged partial plan view of the wire, Figure 12 is an enlarged cross-sectional view of the inch and spring shown in Figure 11, and Figure 3 shows the semiconductor wafer and capillary when the wire is bonded in the assembly of qfN shown in Figure 8. One of the intervals is 邛ί, !ΐ图, Figure 14 shows FIG. 5 is a plan view showing an example of a flow state of a QFN encapsulating resin according to a second embodiment of the present invention, and FIG. 16 is a view showing a flow chart of a structure of a QFN according to a second embodiment of the present invention. FIG. FIG. 7 is a cross-sectional view showing the structure of a semiconductor device (QFN) according to a modification of the second embodiment of the present invention, and FIG. 18 is a wire used for assembling the QFN in the case of FIG. Amplified partial bottom view of the wire structure 85943-35-1290764 of the frame, Figure 19 is an enlarged partial plan view of the wire of the same Q-, bitter a, and port diagram 18, and Figure 20 is an enlarged partial section of the wire shown in Figure 18. Figure 21 is a cross-sectional view of the wire taken along line jj of Figure 19, and Figure 22 is a cross-sectional view of the wire BB of Figure 19, Figure 23, Figure 26, Figure 29 and Figure show the implementation of the present invention. Fig. 25, Fig. 27, Fig. 30 and Fig. 33 are enlarged partial plan views of the wires, and Fig. 25, Fig. 28, Fig. 31 and Fig. 34 are enlarged partial sections of the wires. Figure 35 is an assembly procedure of the QFN (single-piece molding type) shown in Figure 15 - FIG. 36 is a view showing an example of a structure at the time of wiring joining in the assembly shown in FIG. 35 (an enlarged partial cross-sectional view, and FIG. 37 is a view showing an assembly of a modified example (-sub-molding type) according to the second embodiment of the present invention. FIG. 38 is a partial cross-sectional view showing an example of a structure during resin molding in the assembly shown in the drawing, and an enlarged view of the structure of the embodiment, and FIG. 39 shows the implementation of the present invention through the package portion. FIG. 4 is a plan view showing a structure of a structure of the IQFN, FIG. 4 is a cross-sectional view of the structure shown in FIG. 39, and FIG. 41 is a plan view showing a structure of a QFN according to a modification of the third embodiment of the present invention through a package portion, and FIG. FIG. 43 is a cross-sectional view showing a structure of a c-part structure shown in FIG. 42. FIG. 44 is a plan view showing an example of a structure of a QFN according to a fourth embodiment of the present invention. 45 is a plan view of the structure cut along the DD line shown in FIG. 44, and FIG. 46 is a partial plan view showing an example of the structure after the molding of the tree in the qFN assembly shown in FIG. 44 through the package portion, FIG. The structure of the structure cut along the EE line shown in Figure # FIG. 48 is a plan view showing a QFN structure according to a modification of the fourth embodiment of the present invention through a package portion, and FIG. 49 is a cross-sectional view showing a structure cut along the FF line shown in FIG. 48, and FIG. -36- 1290764 The over-encapsulated portion shows a plan view of a QFN structure according to a modification of the fourth embodiment of the present invention, and FIG. 51 is a cross-sectional view taken along the line GG shown in FIG. 50, and FIG. 52 is an embodiment of the present invention. In the mounting structure of the mounting substrate of the QFN of the form 4, the relationship between the mounted surface of each of the wires and the substrate terminal is an enlarged plan view, and FIG. 53 shows the connection state with the substrate terminal of the lead of the mounting structure shown in FIG. FIG. 54 is a plan view showing an example of a state in which the electric characteristics of the QFN according to the fourth embodiment of the present invention are inspected by the sealing portion 777, and FIG. 55 is cut along the h_h line shown in FIG. FIG. 56 is a cross-sectional view showing an example of a socket mounting state in the case of characteristic inspection of the electric power after the qFN assembly according to the fourth embodiment of the present invention, and FIG. 57 is a view showing the configuration of the portion shown in FIG. 56. Zoom in on a partial section view The 58 series shows a partial plan view of one of the supply states of the coffee potential at the time of the characteristic inspection of the electric power shown in Fig. 56, and Fig. 59 is a plan view showing an example of the QFN structure of the fifth embodiment of the present invention transmitted through the package portion. [Description of symbolic representation] 1 lead frame la wire lb support piece 1 c wafer support surface Id mounted surface 1 e suspension wire If joint lg package portion forming surface 1 h inner end portion 85943 -37- 1290764 li notch Ij cutting portion 11 back surface 1 m concave portion lk molding line In end portion thick portion lp base end portion lq wiring joint portion lr bending joint portion Is projection portion recess portion 2 semiconductor wafer 2a pad 2b main surface 2c back surface 2d high frequency amplifier 3 Package part 3a back side 3b side 3c chamfered part 4 wiring 6 solder plating layer 7 capillary tube 8 molding die -38 85943

Claims (1)

I29(PMl626immf 中又申請專利範圍替換本;月） 拾、申請專利細： h 一種半導體裝置，其#徵在於包含： 搭載半導體晶片之支持片； 封裝前述半導體晶片之封裝部； 部之背面的周緣 前述封裝部覆蓋 多數導線，其係包含露出於前述封裝 部之被安裝面與配置於其相反侧且以 之封裝部形成面者；及 夕數配線，其係連接前述半導體晶片之表面電極 應於此之前述導線者； 、 互相相對向配置之前述導線彼此之前述封裝部形成 面之内側端部間之長度係長於前述被线面之内側端 部間之長度’且在前述封裝部形成面之内側端部形成缺 口部者。 2· 一種半導體裝置，其特徵在於包含： 搭載半導體晶片之支持片； 封裝前述半導體晶片之封裝部； 多數導線，其係包含露出於前述封裝部之背面的周緣 邵之被安裝面與配置於其相反側且以前述封裝部覆蓋 之封裝部形成面者；及 多數配線，其係連接前述半導體晶片之表面電極與對 應於此之前述導線者； 互相相對向配置之前述導線彼此之前述封裝部形成 面之内侧端邵間之長度係長於前述被安裝面之内側端 部間之長度，且前述封裝部形成面之至少一部分之寬度 85943-960518.doc Ϊ290764 係寬於前述被安裝面之寬度者。 種半導體裝置，其特徵在於包含·· 搭載半導體晶片之支持片； 封裝前述半導體晶片之封裝部； 多數導線，其係包含露出於前述封裝 Jr ^ 〇. 同面的周緣 4又被安裝面與配置於其相反侧且以 豕 之封裝部形成面者；及 、邵覆蓋 多數配線，其係連接前述半導體晶 應於此之前述導線者； 〈表面電極與對 互相相對向配置之前述導線彼此之前述封 面《内側端部間之長度係長於前述被安裝面 7 却A、E A 文l面又内側端 二二：’ί在前述封裝部形成面之内側端部形成缺 &quot;另外，則述封裝部形成面之至少一 #八、+ 4· 寬於前述被安裝面之寬度者。 ^寬度係 種半導體裝置，其特徵在於包含： 搭載半導體晶片之支持片； 封裝前述半導體晶片之封裝部； 多數導線’其係包含露出於前、 部之被安裝面與配置於其相反側=背面的周緣 之封裳部形成面者；及 ㈣封裝部覆蓋 夕數導甩性配線，其係連接前述曲 極與對應於此之前述導線者； 導-晶片之表面電 各则述導線係形成互相相對向配』 之前述封裝部形成面之内側端部間之：如述導輪 長度長於前述被 85943-960518.doc Ϊ290764 ，面之内侧端部間之長度，且分 被安裝面之前述封裝部形成面者。 x度寬於前述 5_ :申請專利範圍第4項之半導體裝置，… 包含配置於晶片側之配岣&amp;A、 、則述導線係 侧面之内侧、外侧之基H與跨及前迷封震部之 二：形成面之寬度比前述基端部之前述封：：前述封 &lt;寬度更寬者。 形成面 6. 如申請專利範園第4项之半導體裝置， 〈前逑封裝部形成面形成凹部者。〃中在㈣導線 7. 如申請專利範圍第6 形成於前述封裝部形成面之配;^人#其中前述凹部係 8. 如申請專利範固第4项之半導體 《外侧者。 之前述封裝部形成面，相f+v^ 置，/、中在前述導線 直自、^ 對於與前述導線之延伸古内成 直角万向，㈣伸万向成 者。 別述封裝邵形成面寬度之凹部 9. —種半導體裝置，其特徵在於包含： 搭裁半導體晶片之支持片；° 封裳前述半導體晶片之封裝部； 多數導線，並在 、 部者；纟係—邵分露出於前述封裝部之背面之端 懸吊導線’其係與前 逑封装部之北待片連結，且包含露出於前 夕 &lt; Θ面 &lt; 被安裝面者；及 ^數導電㈣線，其料 極與對應於此之前迷導線者，·何_片&lt;表面電 85943-960518.doc 1290764 在人則述懸吊導線之前述被安裝面之相反側之面之 :述被女裝面相對向之區域，連接-端連接於前述半導 體晶片之表面電極之導電性配線之他端者。 •如申明專利範圍第9項之半導體裝置，其中在前述懸吊 導、’泉之則述被安裝面之相反側之面形成凹部者。 u·如申請專利範圍第1G項之半導體裝置，其中前述懸吊導 、泉之如述凹邵係形成於前述被安裝面之相反侧的面之 前述配線連接之處之外侧者。 •如申叩專利範園第11項之半導體裝置，其中前述懸吊導 泉之如述四邵係形成於前述被安裝面之相反側的面之 前述配線連接之處之内侧者。 3·如申4專利範圍第9項之半導體裝置，其中在前述懸吊 導、、泉之則述配線連接之處之外側之兩侧面設有突起部 者。 種半導體裝置，其特徵在於包含： 搭載半導體晶片之支持片； 封裝前述半導體晶片之封裝部； 夕數導線，其係一部分露出於前述封裝部之背面的周 緣部者； 懸吊導線，其係與前述支持片連結，且包含露出於前 述封裝邵之背面之倒角部之被安裝面者；及 多數導電性配線，其係連接前述半導體晶片之表面電 極與對應於此之前述導線者； 在與前述懸吊導線之前述被安裝面之相反側之面之 ^943-960518.doc -4- 端連接於前述半導 導電性配線之他端 則述被安裝面相對向之區域，連接一 體晶# &gt; I I Λ 万又表面電極中GND用電極的 者。 15 16 17. 18. 其中前述支持卩 如申請專利範園第14項之半導體裝置 係被前述封裝部所封裝者。 一種半導时置，其純在於包含： 搭载半導體晶片之支持片； 封裝前述半導體晶片之封裝部； 、多數導線，其係包含露出於前述封裝部之背面之 邵之被安裝面者； ’ ^吊導線’其係與前述支持片連結，且包含露出於前 述封裝邵之背面之被安裝面者；及 夕數導電性配線，其係連接前述半導體晶片之表面電 極與對應於此之前述導線者； 义在與㈣懸吊導線之前述被安裝面之相反側之面之 :述被安裝面相對向之區域，連接—端連接於前述半導 體晶片之表面電極之導電性配線之他端； 月，J述懸吊導線之延伸方向之前述被安裝面之長度係 長於前述被安裝面之前述懸吊導線之厚度者。 如申請專利範圍第16積之半導體裝置，其中在前述懸吊 導線之前述被安裝面之内側區域，與鄰接之前述導線之 最短距離邵係被前述封裝部所封裝者。 如申請第叫之半導體裝置，其中在前述半導 體裝置安裝於安裝基板之際，與鄰接於前述半導體裝置 85943-960518.doc j29〇764 子#二吊導線之前述導線連接之前述安裳基板之端 内n側端部配置於與前述導線之前述 } &amp;側端部同-面或其外側者。 ι面 19. 一種半導體裝置，其特徵在於包含： 搭裁半導體晶片之支持片； 封裝前述半導體晶片之封裝部； 之背面的周緣 述封裝部覆蓋 、夕數導線，其係包含露出於前述封裝部 15之被安裝面與配置於其相反側且以前 之封裝邵形成面者； ，I29 (replacement of patent scope in PMl626immf; month) Picking up, applying for patent fineness: h A semiconductor device, comprising: a support sheet on which a semiconductor wafer is mounted; a package portion encapsulating the semiconductor wafer; a periphery of a back portion of the portion The package portion covers a plurality of wires including a surface to be mounted exposed on the opposite surface of the package portion and a surface on which the package portion is formed, and a surface wiring for connecting the surface electrode of the semiconductor wafer to And the length of the inner end portion of the surface of the package forming portion of the lead wires disposed opposite to each other is longer than the length between the inner end portions of the lined surface and is formed on the surface of the package portion The inner end portion is formed with a notch portion. 2. A semiconductor device comprising: a support sheet on which a semiconductor wafer is mounted; a package portion in which the semiconductor wafer is packaged; and a plurality of wires including a mounting surface exposed on a periphery of the back surface of the package portion and disposed on the semiconductor chip a surface of the package portion covered by the encapsulating portion on the opposite side; and a plurality of wires connecting the surface electrode of the semiconductor wafer and the wire corresponding thereto; and forming the package portion of the wires disposed opposite to each other The length between the inner ends of the faces is longer than the length between the inner ends of the mounted faces, and the width of at least a portion of the face forming face 85594-960518.doc Ϊ 290764 is wider than the width of the face to be mounted. A semiconductor device comprising: a support sheet on which a semiconductor wafer is mounted; a package portion on which the semiconductor wafer is packaged; and a plurality of wires including a peripheral edge 4 exposed on the same surface of the package Jr ^ 〇. And forming a surface on the opposite side of the encapsulation portion of the crucible; and, covering a plurality of wirings, which are connected to the wire on which the semiconductor crystal is to be placed; <the surface electrode and the aforementioned wires disposed opposite to each other The cover "the length between the inner end portions is longer than the above-mentioned mounting surface 7 but A, EA, and the inner side end 22: ' ί is formed at the inner end portion of the encapsulating portion forming surface." At least one of the forming faces, #8, +4· is wider than the width of the aforementioned mounting surface. A width-type semiconductor device comprising: a support sheet on which a semiconductor wafer is mounted; a package portion on which the semiconductor wafer is packaged; and a plurality of wires including a surface to be mounted exposed on the front side and a side opposite to the side And (4) the encapsulating portion covers the imaginary guiding wiring, which is connected to the curved pole and the wire corresponding thereto; the surface of the conductive wafer is formed by each other Between the inner end portions of the surface of the encapsulating portion of the opposing portion: the length of the guide wheel is longer than the length between the inner end portions of the surface of 85943-960518.doc Ϊ 290764, and the package portion of the mounting surface is divided Form the face. The x-degree is wider than the above-mentioned 5_: the semiconductor device of the fourth aspect of the patent application, ... including the 配置 &A arranged on the wafer side, the base H on the inner side and the outer side of the side of the lead wire, and the span and the front seal Part 2: The width of the forming surface is wider than the aforementioned sealing of the base end portion: the sealing portion is wider. Forming the surface 6. As in the case of the semiconductor device of the fourth application of the patent garden, "the front side of the encapsulation portion is formed into a concave portion. In the middle of the (four) wire 7. If the scope of application of the sixth paragraph is formed in the formation surface of the above-mentioned package part; ^ person # which is the aforementioned recessed part 8. As claimed in the patent of the fourth item of the semiconductor "outside." The encapsulating portion forming surface, the phase f + v ^, /, in the wire straight, ^ to the extension of the wire to the right angle of the universal direction, (four) extension of the universal. A semiconductor device is provided, which comprises: a semiconductor device, comprising: a support piece for dicing a semiconductor wafer; a package portion of the semiconductor wafer; a plurality of wires, and a portion; - Shao is exposed at the rear of the package portion at the end of the suspension wire 'which is connected to the north toe of the front 逑 encapsulation portion, and includes exposed on the eve of the Θ Θ 被 被 被 被 被 被 被 被 被 被 被 被 被 被 被 被 及 及 及 及 及 及 及 及 及 及The line, the material of the material and the corresponding wire before the wire, · He_ piece &lt; surface electricity 85943-960518.doc 1290764 on the opposite side of the aforementioned mounting surface of the suspension wire: the female The opposite side of the mounting surface is connected to the other end of the conductive wiring of the surface electrode of the semiconductor wafer. The semiconductor device according to claim 9, wherein the recessed portion is formed on a surface opposite to the mounting surface of the suspension. The semiconductor device according to the first aspect of the invention, wherein the suspension guide and the spring are formed on the outer side of the wiring connection of the surface on the opposite side of the surface to be mounted. The semiconductor device according to claim 11, wherein the suspension guide is formed on the inner side of the wiring connection of the surface on the opposite side of the mounting surface. 3. The semiconductor device according to claim 9, wherein the projections are provided on both sides of the outer side of the suspension connection and the spring connection. A semiconductor device comprising: a support sheet on which a semiconductor wafer is mounted; a package portion in which the semiconductor wafer is packaged; and a plurality of outer circumference wires that are partially exposed on a peripheral portion of a back surface of the package portion; and a suspension wire The support sheet is connected to the surface of the chamfered portion exposed on the back surface of the package, and a plurality of conductive wirings are connected to the surface electrode of the semiconductor wafer and the wire corresponding thereto; The end of the opposite side of the mounting surface of the suspension wire is connected to the other end of the semiconductive conductive wire, and the opposite side of the mounting surface is connected to the integrated surface. &gt; II Λ 10,000 and the electrode of the GND electrode in the surface electrode. 15 16 17. 18. The aforementioned support, such as the semiconductor device of claim 14 of the patent application, is encapsulated by the aforementioned package. A semi-conductive time, which is purely comprising: a support sheet on which a semiconductor wafer is mounted; a package portion encapsulating the semiconductor wafer; and a plurality of wires including a surface to be mounted exposed on the back surface of the package portion; ' ^ a hanging wire that is connected to the support piece and includes a surface to be mounted exposed on a back surface of the package; and a conductive conductive wire that connects the surface electrode of the semiconductor wafer and the wire corresponding thereto And the opposite side of the above-mentioned mounted surface of the suspension wire: the region opposite to the mounting surface, the connection end is connected to the other end of the conductive wiring of the surface electrode of the semiconductor wafer; J The length of the above-mentioned mounted surface in the extending direction of the suspension wire is longer than the thickness of the aforementioned suspension wire on the surface to be mounted. The semiconductor device of claim 16 wherein the shortest distance from the adjacent one of the wires in the inner side of the mounting surface of the suspension wire is encapsulated by the package portion. The application of the semiconductor device of the first aspect, wherein the semiconductor device is mounted on the mounting substrate, and the end of the Antenna substrate connected to the wire adjacent to the semiconductor device 85943-960518.doc j29〇764## The inner n-side end portion is disposed on the same side as the above-mentioned side of the wire and the outer side thereof. A semiconductor device, comprising: a support sheet for dicing a semiconductor wafer; a package portion for encapsulating the semiconductor wafer; a peripheral portion of the back surface of the back surface of the package, and a plurality of ridge wires, wherein the package includes the package portion The surface to be mounted of 15 is disposed on the opposite side of the surface and the former package is formed by Shao; ι吊導線，其係與前述支持片連 诚私册、 丑包含露出於前 封裝邵之背面之被安裝面者，·及 夕數導電性配線，其係連接前述半 極:對應於此之前述導線者； 一片…電 :述導線係形成相對向配置之前述導線彼此之前述 邵形成面之内側端部間之長度長於前述導線彼此 &lt;則述被安裝面之内側端部間之長度；The ith suspension wire is connected to the support piece, and the ugly surface is exposed on the back surface of the front package Shao, and the iridium conductive wiring is connected to the half pole: corresponding to the foregoing a wire; a piece of electricity: the length of the wire between the inner end portions of the oppositely-formed wires forming the oppositely disposed wires is longer than the length of the wire between the inner ends of the wire to be mounted; 、在與則述懸吊導線之前述被安裝面相對向之區域，連 接一端連接於前述半導體晶片之表面電極之導電性配 線之他端者。 20.種半導體裝置之製造方法，其特徵在於包含： 準備步驟，其係準備導線架，而該導線架係包含多數 兀件區域，其係包含搭載半導體晶片之支持片；多數導 、’泉’其係配置於前述支持片之周圍，益包含被安裝面及 其相反側之封裝部形成面者；懸吊導線，其係支持前述 85943-960518.doc -6 - 1290764 支持片者；The other end of the conductive wiring connected to the surface electrode of the semiconductor wafer is connected to a region facing the mounting surface of the suspension wire. 20. A method of fabricating a semiconductor device, comprising: a preparation step of preparing a lead frame, wherein the lead frame comprises a plurality of element regions including a support piece on which a semiconductor wafer is mounted; a plurality of guides, 'spring' It is disposed around the support sheet, and includes a surface formed by the mounting surface and the opposite side of the mounting surface; the suspension wire supports the aforementioned 85943-960518.doc -6 - 1290764 support film; 如述封裝邵形成面寬度之凹部者；Such as the recess of the width of the package forming surface; 區域内後， ，其係將前述半導體晶片配置於前述多數導 &lt;前述封裝部形成面之内侧端部所圍成之 將削述半導體晶片搭載於前述支持片者，· 連接步驟，其係利用導電性配線連接前述半導體晶片 之表面電極與對應於此之前述導線之前述封裝部形成 面之前述凹部之内側處者； 形成步驟，其係以將薄膜配置於樹脂成型模具之模具 面上而以樹脂成型模具之1個膜腔覆蓋前述多數元件區 域 &lt; 狀慼施行合模，利用前述合模，使前述導線之前述 被安裝面鑽入前述薄膜，以施行樹脂成型，使前述多數 導線之被安裝面露出並排列於背面之周緣部而形成一 次封裝部者；及 分離步驟’其係利用切割切斷各導線與前述一次封裳 部而由導線架分離者。 21· —種半導體裝置之製造方法，其特徵在於包含： 準備步驟，其係準備導線架，而該導線架係包含··搭 載半導體晶片之支持片；多數導線，其係配置於前述支 持片之周圍’並包含被安裝面及其相反侧之封裝部形成 面者；懸吊導線，其係支持前述支持片者；且將相對向 85943-960518.doc 1290764 彼此之封裝部形成面之内侧端部間之 各；嗖Ί万1迷被安裝面之内側端部間之長度，並在 緩和切斷時之應力之應力緩和機構者； 才口載步驟，並 ) 、、、則U半導體晶片配置於前述多數導 洳 '則述封裝邵形成面之内側端部所圍成之區域 1’、將前述半導體晶片搭㈣前述支持片者； 、連接步驟’其係利用導電性配線連接前述半導體晶片 表面私極與對應於此之前述導線之前述應力緩和機 構《内側區域之前述封裝部形成面者； /成步驟’其係以樹脂封裝前述半導體晶片及前述配 線’使前述多數導線之被安裝面露出並排列於背面之周 緣邵而形成封裝部者；及 /刀離步驟，其係於以切斷模具夾持各前述導線之前述 底力、、爰和機構之外側處之狀態下，利用衝壓切斷各導線 而由導線架分離者。 22·如申叫專利範圍第2 i項之半導體裝置之製造方法，其中 則述應力緩和機構係狹縫狀之凹部，在前述導線之前述 封裝邵形成面形成前述狹缝狀之凹部者。 23·如申凊專利範圍第21項之半導體裝置之製造方法，其中 則述應力緩和機構係凹部，在前述導線之兩侧面形成前 述凹部者。 24· —種半導體裝置之製造方法，其特徵在於製造半導體裝 置，其係包含： 搭載半導體晶片之支持片； 封裝前述半導體晶片之封裝部； 85943-960518.doc 1290764 多數導線，其係一部分露出前述封裝部之背面之端部 者； 懸吊導線，其係與前述支持片連結，且一部分露出前 述封裝部之背面者； 多數導電性配線，其係連接前述半導體晶片之表面電 極與對應於此之前述導線者；及 導電性配線，其係連接前述半導體晶片之GND用之表 面電極與前述懸吊導線者； 且在經由前述多數導線中GND用之導線及前述懸吊 導線，將GND電位供應至前述半導體晶片之所希望之電 路之狀態下’測試前述半導體裝置者。 85943-960518.docAfter the region, the semiconductor wafer is disposed on the inner end portion of the package forming surface, and the semiconductor wafer is mounted on the support sheet, and the connection step is used. a conductive wiring connecting the surface electrode of the semiconductor wafer and the inner side of the concave portion of the surface of the package portion corresponding to the wire; the forming step of disposing the film on the mold surface of the resin molding die One of the film cavities of the resin molding die covers the plurality of element regions, and the mold is clamped, and the surface of the lead wire is drilled into the film by the mold clamping to perform resin molding to cause the plurality of wires to be The mounting surface is exposed and arranged on the peripheral portion of the back surface to form a primary package portion; and the separating step is performed by cutting the respective wires and the primary sealing portion to be separated by the lead frame. A method of manufacturing a semiconductor device, comprising: a preparation step of preparing a lead frame, wherein the lead frame includes a support piece on which a semiconductor wafer is mounted; and a plurality of wires disposed on the support sheet The surrounding portion includes the surface of the packaged surface and the opposite side of the packaged portion; the suspension wire supports the support piece; and the opposite end faces of the package portion of 85943-960518.doc 1290764 are formed. Each of the two; the length of the inner side of the mounting surface of the , 1 , , , , 缓 缓 缓 缓 缓 缓 缓 缓 缓 缓 缓 缓 缓 缓 缓 缓 缓 缓 缓 U U U U U U U U U U U U U U U U U U The plurality of guides ′′ describe a region 1′ surrounded by the inner end portion of the package forming surface, and the semiconductor wafer is lapped (4) to the support sheet; and the connecting step “connects the surface of the semiconductor wafer with conductive wiring” And the above-mentioned stress relieving mechanism of the aforementioned wire corresponding to the above-mentioned wire, "the above-mentioned package portion forming surface of the inner region; / step" is to encapsulate the aforementioned semiconductor with a resin The wafer and the wiring “are formed by exposing the mounted surface of the plurality of wires and arranging the periphery of the back surface to form a package portion; and a knife-cutting step of clamping the bottom force of each of the wires by the cutting die, In the state of the outer side of the cymbal and the mechanism, the wires are separated by punching and separated by the lead frame. The method of manufacturing a semiconductor device according to the second aspect of the invention, wherein the stress relaxation mechanism is a slit-shaped recess, and the slit-shaped recess is formed on the package forming surface of the wire. The method of manufacturing a semiconductor device according to claim 21, wherein the stress relaxation mechanism is a concave portion, and the concave portion is formed on both side faces of the wire. A method of manufacturing a semiconductor device, comprising: manufacturing a semiconductor device, comprising: a support sheet on which a semiconductor wafer is mounted; and a package portion encapsulating the semiconductor wafer; 85943-960518.doc 1290764 a plurality of wires, a part of which is exposed a terminal of the back surface of the package portion; a suspension wire connected to the support piece and partially exposing a back surface of the package portion; and a plurality of conductive wires connecting the surface electrode of the semiconductor wafer and corresponding thereto And the conductive wiring is connected to the surface electrode for the GND of the semiconductor wafer and the suspension wire; and the GND potential is supplied to the GND wire and the suspension wire through the plurality of wires The semiconductor device is tested in the state of the desired circuit of the semiconductor wafer. 85943-960518.doc
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