JP5173654B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP5173654B2
JP5173654B2 JP2008197943A JP2008197943A JP5173654B2 JP 5173654 B2 JP5173654 B2 JP 5173654B2 JP 2008197943 A JP2008197943 A JP 2008197943A JP 2008197943 A JP2008197943 A JP 2008197943A JP 5173654 B2 JP5173654 B2 JP 5173654B2
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island
semiconductor device
outer edge
semiconductor chip
mold resin
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JP2009060093A (en
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朋之 吉野
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Seiko Instruments Inc
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Seiko Instruments Inc
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

本発明は、樹脂封止された半導体装置に関する。より詳細には、モールド樹脂から半導体チップを搭載するアイランドを露出させた構造の半導体パッケージを有する半導体装置に関する。   The present invention relates to a resin-sealed semiconductor device. More specifically, the present invention relates to a semiconductor device having a semiconductor package having a structure in which an island for mounting a semiconductor chip is exposed from a mold resin.

半導体パッケージに高放熱性を付与する場合には、半導体チップを搭載したアイランド部をモールド樹脂から露出させる方法や他の部材からなる放熱板を半導体チップに貼り付けてモールド樹脂から露出させる方法が一般的に採られる。しかしながら、アイランド部の一部をモールド樹脂に埋め込むだけの構造では、膨張係数などの違いにより、アイランド部がモールド樹脂から抜け落ちることがある。特許文献1には、アイランド部がモールド樹脂から抜けにくくするためにアイランド外周部に潰し加工を施す発明が開示されている。図5に従来の技術による半導体装置の断面図を示す。アイランド2の表面には半導体チップ5が搭載され、アイランド2の外側には離間してリード端子3があり、リード端子と半導体チップはワイヤー6で電気的に接続されている。アイランド2、半導体チップ5、ワイヤー6、リード端子3はモールド樹脂4で覆われるが、アイランド2の下面やリード端子の側面および下面は露出する構造となっている。ここで、アイランド2は上層部と下層部からなり、きのこのように上層部の面積を下層部の面積よりも大きくすることで、上層部がモールド樹脂に食い込み、モールド樹脂が上層部の下に回りこむことによって抜けにくくなっている。
特開平3−11754号公報
When imparting high heat dissipation to a semiconductor package, there are generally a method of exposing an island portion on which a semiconductor chip is mounted from a mold resin, and a method of attaching a heat dissipation plate made of another member to a semiconductor chip and exposing it from the mold resin. Adopted. However, in a structure in which a part of the island part is embedded in the mold resin, the island part may fall out of the mold resin due to a difference in expansion coefficient or the like. Patent Document 1 discloses an invention in which the island portion is crushed to make it difficult for the island portion to come off from the mold resin. FIG. 5 is a sectional view of a conventional semiconductor device. A semiconductor chip 5 is mounted on the surface of the island 2, and lead terminals 3 are spaced apart from the island 2, and the lead terminals and the semiconductor chip are electrically connected by wires 6. The island 2, the semiconductor chip 5, the wire 6, and the lead terminal 3 are covered with the mold resin 4, but the bottom surface of the island 2 and the side and bottom surfaces of the lead terminal are exposed. Here, the island 2 is composed of an upper layer portion and a lower layer portion. By making the area of the upper layer portion larger than the area of the lower layer portion like a mushroom, the upper layer portion bites into the mold resin, and the mold resin is below the upper layer portion. It becomes hard to come off by turning around.
JP-A-3-11754

上記のように、アイランドの外周部分に潰し加工を施し、その断面形状をT字型に形成することで樹脂から抜けにくくしたとしても、半導体装置の薄型化が進み、パッケージの薄型化が進むと、アイランド2がモールド樹脂4から抜け落ちるという不具合が発生する。図5のアイランド潰し加工部8にはモールド樹脂が入り込むが、半導体装置が薄くなると、アイランド潰し加工部8のモールド樹脂が肉薄となる。通常、モールド樹脂加工工程を終えると、バリを取る工程に移るが、高圧水を吹き付けてバリを除去するのが一般的である。高圧水の吹き付けにより薄バリのみならず、これに準ずる肉薄の樹脂も半導体装置から剥離してしまうという問題がある。これは、肉薄の樹脂とアイランドとの密着力が低いためである。アイランド潰し加工部8のモールド樹脂が剥離すると、アイランド2が半導体装置から抜け落ちることとなる。   As mentioned above, even if the outer peripheral part of the island is crushed and its cross-sectional shape is made T-shaped to make it difficult to remove from the resin, the semiconductor device is becoming thinner and the package is becoming thinner. The problem that the island 2 falls off from the mold resin 4 occurs. The mold resin enters the island crushing portion 8 of FIG. 5, but when the semiconductor device becomes thinner, the mold resin of the island crushing portion 8 becomes thinner. Normally, when the mold resin processing step is completed, the process proceeds to a step for removing burrs. Generally, high pressure water is sprayed to remove burrs. There is a problem that not only a thin burr but also a thin resin corresponding to this is peeled off from the semiconductor device by spraying high-pressure water. This is because the adhesion between the thin resin and the island is low. When the mold resin in the island crushing processed portion 8 is peeled off, the island 2 comes off from the semiconductor device.

本発明は、このような従来の構造が有していた問題を解決しようとするものであり、バリ取り工程を経ても、アイランド2が半導体装置にしっかり保持されることを目的とする。   An object of the present invention is to solve the problem of such a conventional structure, and an object of the present invention is to hold the island 2 firmly in the semiconductor device even after the deburring process.

半導体チップを搭載するアイランドの外周部に潰し加工を施して外縁部を設け、断面形状がT字型になるようにすると同時に、その潰し加工を施した部分にアイランドの表面と裏面が貫通する様に複数の切り込み加工を行い、モールド樹脂がアイランドの潰し加工を施した部分を覆う様に挟むことで密着性を高める。   The outer periphery of the island on which the semiconductor chip is mounted is crushed to provide an outer edge so that the cross-sectional shape is T-shaped. At the same time, the front and back of the island penetrate through the crushed portion. A plurality of cuts are made, and the adhesiveness is improved by sandwiching the mold resin so as to cover the portion where the island is crushed.

本発明を実施することで半導体チップを搭載したアイランド部とモールド樹脂の密着性を高めることが出来る。モールド樹脂はアイランド外縁部に形成した凹凸部に入り込むためアイランドを抱え込む構造になり、アイランドがモールド樹脂から抜けにくくなる。   By implementing the present invention, it is possible to improve the adhesion between the island portion on which the semiconductor chip is mounted and the mold resin. Since the mold resin enters the concavo-convex portion formed on the outer edge portion of the island, the structure is configured to hold the island, and the island is difficult to come off from the mold resin.

以下、図面を参照して本発明の実施例を詳細に説明する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

図1は本発明の半導体装置の実施例を示す断面図である。概ねT字型の断面を有するアイランド2の上部の表面には半導体チップ5が銀ペースト等の導電性接着剤を介して搭載され、アイランド2の外側には離間してリード端子3が配置されている。リード端子3には潰し加工がされており、その上層部には外縁部が形成されている。リード端子と半導体チップ表面に設けられたパッド電極とはワイヤー6で電気的に接続されている。アイランド2、半導体チップ5、ワイヤー6、リード端子3は絶縁性を有するモールド樹脂4で覆われるが、アイランド2の下面やリード端子の側面および下面はモールド樹脂4から外部に露出する構造となっている。図示してはいないが、アイランドやリード端子の露出面はメッキされており、このメッキされた部分を介して基板等に実装される。ここで、アイランド2の外周部は潰し加工が施されており外縁部を有する上層部と外縁部の無い下層部からなる。上層部の外縁部にはアイランド凹凸部1が設けられている。なお、半導体チップ5の外縁は通常アイランド外縁部の内側にあるが、アイランド外縁部にかかっていても構わない。   FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor device of the present invention. A semiconductor chip 5 is mounted on the upper surface of the island 2 having a substantially T-shaped cross section via a conductive adhesive such as silver paste, and lead terminals 3 are arranged outside the island 2 so as to be spaced apart. Yes. The lead terminal 3 is crushed, and an outer edge portion is formed on the upper layer portion thereof. The lead terminal and the pad electrode provided on the semiconductor chip surface are electrically connected by a wire 6. The island 2, the semiconductor chip 5, the wire 6, and the lead terminal 3 are covered with an insulating mold resin 4, but the lower surface of the island 2 and the side and lower surfaces of the lead terminal are exposed to the outside from the mold resin 4. Yes. Although not shown, the exposed surfaces of the islands and lead terminals are plated, and are mounted on a substrate or the like through the plated portions. Here, the outer peripheral portion of the island 2 is crushed and is composed of an upper layer portion having an outer edge portion and a lower layer portion having no outer edge portion. An island uneven portion 1 is provided on the outer edge portion of the upper layer portion. The outer edge of the semiconductor chip 5 is usually inside the outer edge of the island, but may be on the outer edge of the island.

図2は、アイランド部2の断面図であり、図3はアイランド部2を上方から見た平面図である。アイランド部2の上層部の外縁部にはアイランド凹凸部1が設けられている。アイランド凹凸部1には外周部から切り込まれた表面から裏面まで貫通する溝が複数設けられアイランド部2の上層部の外縁部を凹凸形状にしている。モールド樹脂は、この凹凸部に入り込むため、樹脂とアイランドとの接着面積が大きくなり、バリ取り工程での剥離耐性が強くなる。   2 is a cross-sectional view of the island portion 2, and FIG. 3 is a plan view of the island portion 2 as viewed from above. An island uneven portion 1 is provided on the outer edge portion of the upper layer portion of the island portion 2. The island uneven portion 1 is provided with a plurality of grooves penetrating from the front surface to the back surface cut from the outer peripheral portion, and the outer edge portion of the upper layer portion of the island portion 2 has an uneven shape. Since the mold resin enters the concavo-convex portion, the bonding area between the resin and the island is increased, and the peeling resistance in the deburring process is increased.

図4はアイランド外縁の凹凸部を拡大した断面図である。凹凸部の側面にテーパー加工が施されおり、アイランド外縁部をモールド樹脂が挟み込む形態になっている。このような形態とすることで接着面積を増すことになり、両者をより強固に密着させることが出来るようになる。   FIG. 4 is an enlarged cross-sectional view of the uneven portion on the outer edge of the island. A taper process is applied to the side surface of the concavo-convex portion so that the mold resin sandwiches the island outer edge portion. By setting it as such a form, an adhesion area will be increased and it will become possible to stick both more firmly.

これまで、アイランドの外縁部に凹凸形状を有することでアイランドとモールド樹脂の密着性を向上させることが可能であることを説明したが、図1に示されるリード端子3にも外縁部があり、この部分に切り込みを入れて凹凸形状とすることでリード端子の抜け落ちを防止することが可能となる。   So far, it has been explained that it is possible to improve the adhesion between the island and the mold resin by having an uneven shape on the outer edge of the island, but the lead terminal 3 shown in FIG. 1 also has an outer edge, It is possible to prevent the lead terminal from falling off by making a cut-out in this portion to form an uneven shape.

アイランド外縁部の凹凸の形成方法は、薬品によるエッチングで形成することも可能である。この場合、アイランドは等方的にエッチングされるため、凹凸部がテーパーとなりやすい。この際、エッチングは片面からのエッチングでも良いし、両面からのエッチングでも良い。両面エッチングの場合は図4に示すようなテーパー形状ではなく、表裏面両方からのテーパー形状が形成される。   The method for forming irregularities on the outer edge of the island can also be formed by etching with chemicals. In this case, since the island is isotropically etched, the uneven portion tends to be tapered. At this time, etching may be performed from one side or from both sides. In the case of double-sided etching, a taper shape from both the front and back surfaces is formed instead of the taper shape as shown in FIG.

また、プレス加工によってアイランド周辺部を打ち抜くことで凹凸を形成することも可能である。この場合もアイランドの表面と裏面の間にテーパーを付けることが可能である。   It is also possible to form irregularities by punching the periphery of the island by pressing. In this case also, it is possible to taper between the front surface and the back surface of the island.

図6には、図4で示したアイランド外縁の凹凸部の側面テーパー加工の方向を逆にしたものである。この様に逆方向にテーパー加工してもモールド樹脂との引っかかりが強くなり、樹脂からアイランドが抜けにくくなる。   In FIG. 6, the direction of the side taper processing of the uneven portion of the island outer edge shown in FIG. 4 is reversed. Thus, even if taper processing is performed in the reverse direction, the mold resin is strongly caught, and the island is difficult to escape from the resin.

図7は、アイランドを分割する溝であるアイランド分割溝9を縦横に設けたものである。この溝にモールド樹脂が流れ込み、チップ下にも樹脂が入り込みアイランドが抜けにくくなっている。 In FIG. 7, island dividing grooves 9 which are grooves for dividing an island are provided vertically and horizontally. Mold resin flows into this groove, and the resin also enters under the chip, making it difficult for the island to come off.

アイランド分割溝にもテーパー加工をすることでより強度をさらに向上させることが可能である。   It is possible to further improve the strength by tapering the island dividing grooves.

以上のようなアイランドの形態とすることで、モールド樹脂からアイランドが抜け落ちることのない半導体装置を構成することが可能となる。   With the island configuration as described above, it is possible to configure a semiconductor device in which the island does not fall out of the mold resin.

本発明による半導体装置の断面図Sectional view of a semiconductor device according to the present invention. 本発明による半導体装置のアイランド部の断面図Sectional view of island part of semiconductor device according to the present invention 本発明による半導体装置のアイランド部の平面図The top view of the island part of the semiconductor device by this invention 本発明による半導体装置のアイランド部の拡大断面図The expanded sectional view of the island part of the semiconductor device by this invention 従来の半導体装置の断面図。Sectional drawing of the conventional semiconductor device. 本発明による半導体装置のアイランド部の断面図Sectional view of island part of semiconductor device according to the present invention 本発明による半導体装置のアイランド部の平面図The top view of the island part of the semiconductor device by this invention

符号の説明Explanation of symbols

1 アイランド凹凸部
2 アイランド部
3 リード端子
4 モールド樹脂
5 半導体チップ
6 ワイヤー
7 拡大されたアイランド凹凸部
8 アイランド潰し加工部
9 アイランド分割溝
DESCRIPTION OF SYMBOLS 1 Island uneven part 2 Island part 3 Lead terminal 4 Mold resin 5 Semiconductor chip 6 Wire 7 Expanded island uneven part 8 Island crushing part 9 Island division groove

Claims (5)

絶縁性樹脂からなる封止体と、
前記封止体の実装面に裏面を露出しており、前記裏面と反対側の表面に導電性接着剤を介して半導体チップを搭載するアイランドと、
前記封止体の実装面に裏面を露出し、外縁部を有するリード端子と、
前記半導体チップと前記リード端子を電気的に接続するワイヤーとからなる半導体装置であって、
記アイランドの表面側の外縁にはアイランドよりも厚みが薄く、複数の切れ込みがあるアイランド凹凸部を有し、前記アイランド凹凸部の側面は、その先端に垂直な方向の断面が上側のチップ搭載面側の幅より下側の面の幅が広く形成された台形形状である、テーパーを有することを特徴とする半導体装置。
A sealing body made of an insulating resin;
The back surface is exposed on the mounting surface of the sealing body, and an island on which a semiconductor chip is mounted via a conductive adhesive on the surface opposite to the back surface,
A lead terminal exposing a back surface on the mounting surface of the sealing body and having an outer edge;
A semiconductor device comprising a wire for electrically connecting the semiconductor chip and the lead terminal,
Thinner thickness than the island in the outer surface side of the front Symbol island has an island uneven portion more slits there Ru, side of the island uneven portion, the vertical direction of the cross section at the distal end upper side of the tip A semiconductor device having a taper which is a trapezoidal shape in which a width of a lower surface is wider than a width of a mounting surface .
前記アイランドは、前記チップ搭載面から前記アイランドの内部にかけて設けられたアイランド分割溝をさらに有することを特徴とする請求項1記載の半導体装置。 The island semiconductor device according to claim 1, wherein Rukoto further having a islands divided grooves provided from the chip mounting surface to the interior of the island. 前記アイランド凹凸部よりも内側に半導体チップの外縁があることを特徴とする請求項1記載の半導体装置。 The semiconductor device according to claim 1, wherein an outer edge of the semiconductor chip is inside the island uneven portion . 前記アイランド凹凸部内に半導体チップの外縁があることを特徴とする請求項1記載の半導体装置。 The semiconductor device according to claim 1, wherein an outer edge of the semiconductor chip is in the island uneven portion . 前記リード端子の外縁部には切れ込みがあって、凹凸形状であることを特徴とする請求項1乃至4のいずれか一項記載の半導体装置。   5. The semiconductor device according to claim 1, wherein an outer edge portion of the lead terminal is notched and has an uneven shape.
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JP5797126B2 (en) * 2012-02-06 2015-10-21 三菱電機株式会社 Semiconductor device
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JP7365871B2 (en) 2019-11-26 2023-10-20 エイブリック株式会社 Semiconductor device and its manufacturing method
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Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56104458A (en) * 1980-01-23 1981-08-20 Hitachi Ltd Semiconductor device
JPH0447966Y2 (en) * 1986-10-28 1992-11-12
JPS63157451A (en) * 1986-12-22 1988-06-30 Oki Electric Ind Co Ltd Lead frame for semiconductor device
JPH0422162A (en) * 1990-05-17 1992-01-27 Hitachi Ltd Lead frame and semiconductor integrated circuit device using it
JPH06268143A (en) * 1993-03-15 1994-09-22 Seiko Epson Corp Lead frame and semiconductor device
JP2570611B2 (en) * 1993-12-10 1997-01-08 日本電気株式会社 Resin-sealed semiconductor device
US6448633B1 (en) * 1998-11-20 2002-09-10 Amkor Technology, Inc. Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant
JP2001077278A (en) * 1999-10-15 2001-03-23 Amkor Technology Korea Inc Semiconductor package, lead frame thereof, manufacture of semiconductor package and mold thereof
JP4149439B2 (en) * 2002-07-01 2008-09-10 株式会社ルネサステクノロジ Semiconductor device
JP2004228167A (en) * 2003-01-20 2004-08-12 Sanyo Electric Co Ltd Lead frame and semiconductor device using it
JP2004349397A (en) * 2003-05-21 2004-12-09 Sharp Corp Semiconductor device and lead frame used therefor
JP4055158B2 (en) * 2003-05-28 2008-03-05 ヤマハ株式会社 Lead frame and semiconductor device provided with lead frame
JP2006318996A (en) * 2005-05-10 2006-11-24 Matsushita Electric Ind Co Ltd Lead frame and resin sealed semiconductor device
JP4252563B2 (en) * 2005-07-05 2009-04-08 株式会社ルネサステクノロジ Semiconductor device

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