JP4357519B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4357519B2 JP4357519B2 JP2006286467A JP2006286467A JP4357519B2 JP 4357519 B2 JP4357519 B2 JP 4357519B2 JP 2006286467 A JP2006286467 A JP 2006286467A JP 2006286467 A JP2006286467 A JP 2006286467A JP 4357519 B2 JP4357519 B2 JP 4357519B2
- Authority
- JP
- Japan
- Prior art keywords
- lead
- tab
- suspension
- suspension lead
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
図1、図2および図3は本実施の形態のQFNの構造の一例を示す図、図4および図5はリードフレームの図、図6はQFNの組み立て手順を示す製造プロセスフロー図である。
とを金線などのワイヤ4によって接続するワイヤボンディングを行う(ステップS3)。
1a リード
1b タブ
1c チップ支持面
1d 裏面
1e 吊りリード
1f 凸部
1g 被接続面
1h 幅広部
2 半導体チップ
2a パッド(表面電極)
2b 主面
2c 裏面
3 封止部
3a 裏面(半導体装置実装側の面)
4 ワイヤ
5 QFN(半導体装置)
6 半田メッキ
7 ボール端子パッケージ(半導体装置)
7a 半田ボール
8 モールドライン
Claims (3)
- 半導体チップを支持可能なタブと、
前記タブと一体に形成された複数の吊りリードと、
前記タブの周囲に配置された複数のリードと、
複数の表面電極を有し、前記タブ上に搭載された半導体チップと、
前記半導体チップの前記複数の表面電極と前記複数のリードとを接続する複数のワイヤと、
前記半導体チップ、前記複数のワイヤ、前記タブ、前記複数のリード、前記複数の吊りリードを封止する樹脂体とを有し、
前記複数の吊りリードの各々は、前記樹脂体の端部において前記樹脂体の裏面からその一部が露出する露出部分を有し、
前記露出部分は、前記樹脂体の端部側に位置する第1部分と、前記第1部分より前記タブ側で、かつ前記第1部分よりその幅を広く形成された第2部分を有し、
前記複数の吊りリードの各々は、前記露出部分の反対側の面に、前記露出部分の幅よりも大きい凸部を有し、前記凸部は前記樹脂体内に位置していることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、前記複数の吊りリードの各々は、前記タブと前記露出部分との間に、前記露出部分よりもその厚さが薄い部分を有し、前記第2部分は、前記露出部分と前記薄い部分との間に位置していることを特徴とする半導体装置。
- 請求項2記載の半導体装置において、前記複数の吊りリードの各々の前記薄い部分と前記タブの厚さは同一であることを特徴とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006286467A JP4357519B2 (ja) | 2006-10-20 | 2006-10-20 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006286467A JP4357519B2 (ja) | 2006-10-20 | 2006-10-20 | 半導体装置 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2000313973A Division JP3891772B2 (ja) | 2000-10-13 | 2000-10-13 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007013220A JP2007013220A (ja) | 2007-01-18 |
JP4357519B2 true JP4357519B2 (ja) | 2009-11-04 |
Family
ID=37751194
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006286467A Expired - Fee Related JP4357519B2 (ja) | 2006-10-20 | 2006-10-20 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4357519B2 (ja) |
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2006
- 2006-10-20 JP JP2006286467A patent/JP4357519B2/ja not_active Expired - Fee Related
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Publication number | Publication date |
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JP2007013220A (ja) | 2007-01-18 |
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