JP5091209B2 - 表示装置 - Google Patents
表示装置 Download PDFInfo
- Publication number
- JP5091209B2 JP5091209B2 JP2009209031A JP2009209031A JP5091209B2 JP 5091209 B2 JP5091209 B2 JP 5091209B2 JP 2009209031 A JP2009209031 A JP 2009209031A JP 2009209031 A JP2009209031 A JP 2009209031A JP 5091209 B2 JP5091209 B2 JP 5091209B2
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- JP
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- Prior art keywords
- oxide semiconductor
- layer
- semiconductor layer
- gate electrode
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- G—PHYSICS
- G02—OPTICS
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Description
本形態は、画素部とその周辺に非線形素子を含む保護回路が形成された表示装置の一態様を図面を参照して説明する。
本形態は、実施の形態1において図4(A)に示した画素部とその周辺に非線形素子を含む保護回路が形成された表示装置の作製工程の一様態を図8及び図9を参照して説明する。図8及び図9は図4(A)中のQ1−Q2切断線に対応した断面図を表している。
本形態は、画素部とその周辺に非線形素子を含む保護回路が形成された表示装置の実施の形態2とは異なる一様態を、図27を参照して説明する。
本実施の形態では、本発明の一態様を適用した表示装置として、保護回路と画素部に配置するTFTを同一基板上に有する電子ペーパーの例を示す。
本実施の形態では、本発明の一態様の半導体装置の一例である表示装置において、同一基板上に少なくとも保護回路と、駆動回路の一部と、画素部に配置する薄膜トランジスタを作製する例について図11乃至図16を用いて以下に説明する。
本発明の一態様の非線形素子と共に薄膜トランジスタを作製し、該薄膜トランジスタを画素部、さらには駆動回路に用いて表示機能を有する半導体装置(表示装置ともいう)を作製することができる。また、本発明の一態様の非線形素子と薄膜トランジスタを駆動回路の一部または全体に用い、画素部と同じ基板上に一体形成し、システムオンパネルを形成することができる。
本発明の一態様の非線形素子と共に薄膜トランジスタを作製し、該薄膜トランジスタを画素部、さらには駆動回路に用いて表示機能を有する半導体装置(表示装置ともいう)を作製することができる。
本発明の一態様の表示装置は、電子ペーパーとして適用することができる。電子ペーパーは、情報を表示するものであればあらゆる分野の電子機器に用いることが可能である。例えば、電子ペーパーを用いて、電子書籍(電子ブック)、ポスター、電車などの乗り物の車内広告、クレジットカード等の各種カードにおける表示等に適用することができる。電子機器の一例を図22、図23に示す。
本発明の一態様に係る半導体装置は、さまざまな電子機器(遊技機も含む)に適用することができる。電子機器としては、例えば、テレビジョン装置(テレビ、またはテレビジョン受信機ともいう)、コンピュータ用などのモニタ、デジタルカメラなどのカメラ、デジタルビデオカメラ、デジタルフォトフレーム、携帯電話機(携帯電話、携帯電話装置ともいう)、携帯型ゲーム機、携帯情報端末、音響再生装置、パチンコ機などの大型ゲーム機などが挙げられる。
11 走査線入力端子
12 信号線入力端子
13 走査線
14 信号線
16 ゲート電極
17 画素部
18 画素
19 画素トランジスタ
20 保持容量部
21 画素電極
22 容量線
23 共通端子
24 保護回路
25 保護回路
26 保護回路
27 容量バス線
28 共通配線
29 共通配線
30 非線形素子
30a 非線形素子
30b 非線形素子
31 非線形素子
31a 非線形素子
31b 非線形素子
38 配線層
39 配線層
100 基板
101 ゲート電極
102 ゲート絶縁層
103 酸化物半導体層
104a 酸化物半導体層
104b 酸化物半導体層
105a 導電層
105b 導電層
107 保護絶縁膜
108 走査線
110 配線層
111 酸化物半導体層
125 コンタクトホール
128 コンタクトホール
131 レジストマスク
132 導電膜
170a 非線形素子
170b 非線形素子
270a 非線形素子
581 薄膜トランジスタ
585 絶縁層
587 電極層
588 電極層
589 球形粒子
590a 黒色領域
590b 白色領域
594 キャビティ
595 充填材
730a 非線形素子
730b 非線形素子
730c 非線形素子
740a 非線形素子
740b 非線形素子
740c 非線形素子
740d 非線形素子
1000 携帯電話機
1001 筐体
1002 表示部
1003 操作ボタン
1004 外部接続ポート
1005 スピーカ
1006 マイク
2600 TFT基板
2601 対向基板
2602 シール材
2603 画素部
2604 表示素子
2605 着色層
2606 偏光板
2607 偏光板
2608 配線回路部
2609 フレキシブル配線基板
2610 冷陰極管
2611 反射板
2612 回路基板
2613 拡散板
2631 ポスター
2632 車内広告
2700 電子書籍
2701 筐体
2703 筐体
2705 表示部
2707 表示部
2711 軸部
2721 電源
2723 操作キー
2725 スピーカ
4001 基板
4002 画素部
4003 信号線駆動回路
4004 走査線駆動回路
4005 シール材
4006 基板
4008 液晶層
4010 薄膜トランジスタ
4011 薄膜トランジスタ
4013 液晶素子
4015 接続端子電極
4016 端子電極
4018 FPC
4019 異方性導電膜
4020 絶縁層
4021 絶縁層
4030 画素電極層
4031 対向電極層
4032 絶縁層
4501 基板
4502 画素部
4503a 信号線駆動回路
4504a 走査線駆動回路
4505 シール材
4506 基板
4507 充填材
4509 薄膜トランジスタ
4510 薄膜トランジスタ
4511 発光素子
4512 電界発光層
4513 電極層
4515 接続端子電極
4516 端子電極
4517 電極層
4518a FPC
4519 異方性導電膜
4520 隔壁
5300 基板
5301 画素部
5302 走査線駆動回路
5303 信号線駆動回路
5400 基板
5401 画素部
5402 走査線駆動回路
5403 信号線駆動回路
5404 走査線駆動回路
5501 配線
5502 配線
5503 配線
5504 配線
5505 配線
5506 配線
5543 ノード
5544 ノード
5571 薄膜トランジスタ
5572 薄膜トランジスタ
5573 薄膜トランジスタ
5574 薄膜トランジスタ
5575 薄膜トランジスタ
5576 薄膜トランジスタ
5577 薄膜トランジスタ
5578 薄膜トランジスタ
5601 ドライバIC
5602 スイッチ群
5603a 薄膜トランジスタ
5603b 薄膜トランジスタ
5603c 薄膜トランジスタ
5611 配線
5612 配線
5613 配線
5621 配線
5701 フリップフロップ
5703a タイミング
5703b タイミング
5703c タイミング
5711 配線
5712 配線
5713 配線
5714 配線
5715 配線
5716 配線
5717 配線
5721 信号
5803a タイミング
5803b タイミング
5803c タイミング
5821 信号
6400 画素
6401 スイッチング用トランジスタ
6402 駆動用トランジスタ
6403 容量素子
6404 発光素子
6405 信号線
6406 走査線
6407 電源線
6408 共通電極
7001 TFT
7002 発光素子
7003 陰極
7004 発光層
7005 陽極
7011 駆動用TFT
7012 発光素子
7013 陰極
7014 発光層
7015 陽極
7016 遮蔽膜
7017 導電膜
7021 駆動用TFT
7022 発光素子
7023 陰極
7024 発光層
7025 陽極
7027 導電膜
9600 テレビジョン装置
9601 筐体
9603 表示部
9605 スタンド
9607 表示部
9609 操作キー
9610 リモコン操作機
9700 デジタルフォトフレーム
9701 筐体
9703 表示部
9881 筐体
9882 表示部
9883 表示部
9884 スピーカ部
9885 入力手段(操作キー)
9886 記録媒体挿入部
9887 接続端子
9888 センサ
9889 マイクロフォン
9890 LEDランプ
9891 筐体
9893 連結部
9900 スロットマシン
9901 筐体
9903 表示部
Claims (8)
- 基板上に、互いに交差して設けられた複数の走査線および複数の信号線と、
前記基板上に設けられ、マトリクス状に配列した複数の画素電極を有する画素部と、
前記基板の周辺部に設けられた信号入力端子と、
前記画素部と前記信号入力端子の間に設けられた保護回路と、
を有し、
前記画素部は薄膜トランジスタを有し、
前記薄膜トランジスタは、
チャネル形成領域を有する第1酸化物半導体層と、
前記複数の走査線の一つと接続する第1のゲート電極と、
前記複数の信号線の一つおよび前記第1酸化物半導体層と接続する第1配線層と、
前記複数の画素電極の一つおよび前記第1酸化物半導体層と接続する第2配線層と、
を有し、
前記保護回路は、第1の非線形素子と第2の非線形素子を有し、
前記第1の非線形素子は、
前記複数の走査線の一つまたは前記複数の信号線の一つと接続する第2のゲート電極と、
前記第2のゲート電極を被覆する第1のゲート絶縁層と、
前記第1のゲート絶縁層上に設けられ、前記第2のゲート電極と重畳する第2酸化物半導体層と、
前記第2酸化物半導体層上に設けられ、端部が前記第2のゲート電極と重畳し、かつ、第1導電層と第3酸化物半導体層の積層を有する第3配線層と、
前記第2酸化物半導体層上に設けられ、端部が前記第2のゲート電極と重畳し、かつ、第2導電層と第4酸化物半導体層の積層を有する第4配線層と、
を有し、
前記第3配線層は前記複数の走査線の一つまたは前記複数の信号線の一つと接続し、
前記第4配線層は共通配線と接続し、
前記第2の非線形素子は、
前記共通配線と接続する第3のゲート電極と、
前記第3のゲート電極を被覆する第2のゲート絶縁層と、
前記第2のゲート絶縁層上に設けられ、前記第3のゲート電極と重畳する第5酸化物半導体層と、
前記第5酸化物半導体層上に設けられ、端部が前記第3のゲート電極と重畳し、かつ、第3導電層と第6酸化物半導体層の積層を有する第5配線層と、
前記第5酸化物半導体層上に設けられ、端部が前記第3のゲート電極と重畳し、かつ、第4導電層と第7酸化物半導体層の積層を有する第6配線層と、
を有し、
前記第5配線層は前記複数の走査線の一つまたは前記複数の信号線の一つと接続し、
前記第6配線層は前記共通配線と接続することを特徴とする表示装置。 - 基板上に、互いに交差して設けられた複数の走査線および複数の信号線と、
前記基板上に設けられ、マトリクス状に配列した複数の画素電極を有する画素部と、
前記基板の周辺部に設けられた信号入力端子と、
前記画素部と前記信号入力端子の間に設けられた保護回路と、
を有し、
前記画素部は薄膜トランジスタを有し、
前記薄膜トランジスタは、
チャネル形成領域を有する第1酸化物半導体層と、
前記複数の走査線の一つと接続する第1のゲート電極と、
前記複数の信号線の一つおよび前記第1酸化物半導体層と接続する第1配線層と、
前記複数の画素電極の一つおよび前記第1酸化物半導体層と接続する第2配線層と、
を有し、
前記保護回路は、第1の非線形素子と第2の非線形素子と第3の非線形素子を有し、
前記第1の非線形素子は、
第2のゲート電極と、
前記第2のゲート電極を被覆する第1のゲート絶縁層と、
前記第1のゲート絶縁層上に設けられ、前記第2のゲート電極と重畳する第2酸化物半導体層と、
前記第2酸化物半導体層上に設けられ、端部が前記第2のゲート電極と重畳し、かつ、第1導電層と第3酸化物半導体層の積層を有する第3配線層と、
前記第2酸化物半導体層上に設けられ、端部が前記第2のゲート電極と重畳し、かつ、第2導電層と第4酸化物半導体層の積層を有する第4配線層と、
を有し、
前記第3配線層は前記複数の走査線の一つまたは前記複数の信号線の一つと接続し、
前記第4配線層は共通配線と接続し、
前記第2の非線形素子は、
前記複数の走査線の一つまたは前記複数の信号線の一つと接続する第3のゲート電極と、
前記第3のゲート電極を被覆する第2のゲート絶縁層と、
前記第2のゲート絶縁層上に設けられ、前記第3のゲート電極と重畳する第5酸化物半導体層と、
前記第5酸化物半導体層上に設けられ、端部が前記第3のゲート電極と重畳し、かつ、第3導電層と第6酸化物半導体層の積層を有する第5配線層と、
前記第5酸化物半導体層上に設けられ、端部が前記第3のゲート電極と重畳し、かつ、第4導電層と第7酸化物半導体層の積層を有する第6配線層と、
を有し、
前記第5配線層は前記複数の走査線の一つまたは前記複数の信号線の一つと接続し、
前記第6配線層は前記第2のゲート電極と接続し、
前記第3の非線形素子は、
前記共通配線と接続する第4のゲート電極と、
前記第4のゲート電極を被覆する第3のゲート絶縁層と、
前記第3のゲート絶縁層上に設けられ、前記第4のゲート電極と重畳する第8酸化物半導体層と、
前記第8酸化物半導体層上に設けられ、端部が前記第4のゲート電極と重畳し、かつ、第5導電層と第9酸化物半導体層の積層を有する第7配線層と、
前記第8酸化物半導体層上に設けられ、端部が前記第4のゲート電極と重畳し、かつ、第6導電層と第10酸化物半導体層の積層を有する第8配線層と、
を有し、
前記第7配線層は前記共通配線と接続し、
前記第8配線層は前記第2のゲート電極と接続することを特徴とする表示装置。 - 基板上に、互いに交差して設けられた複数の走査線および複数の信号線と、
前記基板上に設けられ、マトリクス状に配列した複数の画素電極を有する画素部と、
前記基板の周辺部に設けられた信号入力端子と、
前記画素部と前記信号入力端子の間に設けられた保護回路と、
を有し、
前記画素部は薄膜トランジスタを有し、
前記薄膜トランジスタは、
チャネル形成領域を有する第1酸化物半導体層と、
前記複数の走査線の一つと接続する第1のゲート電極と、
前記複数の信号線の一つおよび前記第1酸化物半導体層と接続する第1配線層と、
前記複数の画素電極の一つおよび前記第1酸化物半導体層と接続する第2配線層と、
を有し、
前記保護回路は、第1の非線形素子と第2の非線形素子と第3の非線形素子と第4の非線形素子を有し、
前記第1の非線形素子は、
前記複数の走査線の一つまたは前記複数の信号線の一つと接続する第2のゲート電極と、
前記第2のゲート電極を被覆する第1のゲート絶縁層と、
前記第1のゲート絶縁層上に設けられ、前記第2のゲート電極と重畳する第2酸化物半導体層と、
前記第2酸化物半導体層上に設けられ、端部が前記第2のゲート電極と重畳し、かつ、第1導電層と第3酸化物半導体層の積層を有する第3配線層と、
前記第2酸化物半導体層上に設けられ、端部が前記第2のゲート電極と重畳し、かつ、第2導電層と第4酸化物半導体層の積層を有する第4配線層と、
を有し、
前記第3配線層は前記複数の走査線の一つまたは前記複数の信号線の一つと接続し、
前記第4配線層は共通配線と接続し、
前記第2の非線形素子は、
前記共通配線と接続する第3のゲート電極と、
前記第3のゲート電極を被覆する第2のゲート絶縁層と、
前記第2のゲート絶縁層上に設けられ、前記第3のゲート電極と重畳する第5酸化物半導体層と、
前記第5酸化物半導体層上に設けられ、端部が前記第3のゲート電極と重畳し、かつ、第3導電層と第6酸化物半導体層の積層を有する第5配線層と、
前記第5酸化物半導体層上に設けられ、端部が前記第3のゲート電極と重畳し、かつ、第4導電層と第7酸化物半導体層の積層を有する第6配線層と、
を有し、
前記第5配線層は前記複数の走査線の一つまたは前記複数の信号線の一つと接続し、
前記第6配線層は前記共通配線と接続し、
前記第3の非線形素子は、
前記複数の走査線の一つまたは前記複数の信号線の一つと接続する第4のゲート電極と、
前記第4のゲート電極を被覆する第3のゲート絶縁層と、
前記第3のゲート絶縁層上に設けられ、前記第4のゲート電極と重畳する第8酸化物半導体層と、
前記第8酸化物半導体層上に設けられ、端部が前記第4のゲート電極と重畳し、かつ、第5導電層と第9酸化物半導体層の積層を有する第7配線層と、
前記第8酸化物半導体層上に設けられ、端部が前記第4のゲート電極と重畳し、かつ、第6導電層と第10酸化物半導体層の積層を有する第8配線層と、
を有し、
前記第7配線層は前記複数の走査線の一つまたは前記複数の信号線の一つと接続し、
前記第8配線層は前記共通配線と接続し、
前記第4の非線形素子は、
前記共通配線と接続する第5のゲート電極と、
前記第5のゲート電極を被覆する第4のゲート絶縁層と、
前記第4のゲート絶縁層上に設けられ、前記第5のゲート電極と重畳する第11酸化物半導体層と、
前記第11酸化物半導体層上に設けられ、端部が前記第5のゲート電極と重畳し、かつ、第7導電層と第12酸化物半導体層の積層を有する第9配線層と、
前記第11酸化物半導体層上に設けられ、端部が前記第5のゲート電極と重畳し、かつ、第8導電層と第13酸化物半導体層の積層を有する第10配線層と、
を有し、
前記第9配線層は前記複数の走査線の一つまたは前記複数の信号線の一つと接続し、
前記第10配線層は前記共通配線と接続することを特徴とする表示装置。 - 請求項1乃至請求項3のいずれか一項において、
前記第2酸化物半導体層は、前記第3酸化物半導体層および前記第4酸化物半導体層よりも酸素濃度が高いことを特徴とする表示装置。 - 請求項1乃至請求項3のいずれか一項において、
前記第2酸化物半導体層は、前記第3酸化物半導体層および前記第4酸化物半導体層よりも電気伝導度が低いことを特徴とする表示装置。 - 請求項1乃至請求項5のいずれか一項において、
前記第1の非線形素子および前記第2の非線形素子上に保護絶縁膜を有し、
前記保護絶縁膜は、前記第2酸化物半導体層および前記第5酸化物半導体層と接し、
前記保護絶縁膜は、酸化物を有し、前記第2の酸化物半導体および前記第5の酸化物半導体から酸素が引き抜かれることを防ぐ機能を有することを特徴とする表示装置。 - 請求項1乃至請求項6のいずれか一項において、
前記酸化物半導体層は、インジウム、ガリウム、及び亜鉛を含むことを特徴とする表示装置。 - 請求項1乃至請求項7のいずれか一項において、
前記チャネル形成領域の膜厚は、前記第1酸化物半導体層の他の領域の膜厚よりも小さいことを特徴とする表示装置。
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