466773 五、發明說明(1) 發明之領域 本發明提供一種薄膜電晶體液晶顯示器(th i n f i 1 m transistor liquid crystal display, TFT-LCD)系統的 製作方法,尤指一種利用五次黃光暨蝕刻製程 (photo-etching-process, PE’P)以製作TFT-LCD 元件的方 法,該TFT-LCD元件具有一備用内速線(redundant localized interconnection) 〇 背景說明 隨著電子資訊產業的蓬勃發展,平面顯示器(plat panel _d i sp 1 a.y )的應用範圍以及需求也不斷的擴大。現今 的平面顯示器類型主要包括有:液晶顧示器(1 iquid c r y s t a 1 d i s p 1 a y, L C D )、電聚顯示器(p 1 a s m a d i s p 1 a y pane 1, PDP )、電激發光顯示器(e 1 e c t r o - 1 um i ne sc en t d. i s p 1 a y,_E L D.)..、場發射顯示器( f ield-emission d i s p 1 a y, F E D )、發光二極體顯示器(1 i g h t e m i 11 i n g diode display,LED)、真空螢光顯示器(vacuum fluorescent display, VFD)等等。 目前,薄膜電晶體液晶顯示器(TFT-LCD)大部份都是 \ 利用成矩陣狀排列的薄膜電晶體,配合適當的電容、轉接 墊等電子元件來驅動液晶像素’以產生豐富亮麗的圖形。466773 V. Description of the invention (1) Field of the invention The present invention provides a method for manufacturing a thin film transistor liquid crystal display (thinfi 1 m transistor liquid crystal display, TFT-LCD) system, especially a five-time yellow light and etching process. (photo-etching-process, PE'P) A method for making a TFT-LCD element, which has a redundant localized interconnection. Background Description With the vigorous development of the electronic information industry, flat-panel displays (Plat panel _d i sp 1 ay) The application range and demand are also expanding. Today's flat-panel display types mainly include: liquid crystal display (1 iquid crysta 1 disp 1 ay, LCD), electro-polymer display (p 1 asmadisp 1 ay pane 1, PDP), and electro-excitation light display (e 1 ectro-1 um i ne sc en t d. isp 1 ay, _E L D.) .., field emission display (field-emission disp 1 ay, FED), light emitting diode display (1 ightemi 11 ing diode display, LED) Vacuum vacuum display (VFD) and so on. At present, most thin-film transistor liquid crystal displays (TFT-LCDs) use thin-film transistors arranged in a matrix, with appropriate capacitors, adapter pads and other electronic components to drive liquid crystal pixels to produce rich and beautiful graphics. .
466773 五、發明說明(2) 傳統的液晶顯示元件基本上包含有一透明基板 (transparent substrate) ’其上具有一陣歹的薄膜電晶 體、像素電極(pixel electrode)、垂直交錯的掃瞄線 ( scan l ine ; 〇r gate 1 i ne )以及訊號線(da t a i i ne ; or s i g n a 1 line)·、一 慮光板(color fi,Iter, substrate)、.以-及介於透明基板以及濾光板之間的液晶材料。由於 TFT-LCD具有外型輕薄、耗電量少以及無輕射污染等優 點,因此被廣泛地應用在筆記型電腦(notebook)、個人數 位胁理(P D A )等攜帶式資訊產品上,並且已經有取代傳統 桌上型電腦之CRT監視器的趨勢。 請參閱圖一’圖一為習知薄膜電晶體液晶顯示器(以 下稱T F T - L C D ) 1 0之部份佈局(1 a y 〇 u t)示意圖。習知 T FT - LC D 1 0是製作在一透明的玻璃基板1 1上。如圖一所 示’玻璃基板1 1的表面上具有至少一薄膜電晶體4 〇、複數 條掃瞎線1 2 .、以及複數條.與掃猫線1 2垂直交錯之訊號〜線 14。在TFT-LCD 10中’每一薄膜電晶體4 〇皆用來驅動一由 氧化銦錫(indium tin oxide, IT0)所構成之像素電極 1 6。薄膜電晶體4 0是由,閘極4 2、.源極4 3以及沒極44所構 成.。由多晶石夕所構成之閘極4 2係與掃瞄線12同時形成,源 極4 3以及没極4 4係分別藉由一接觸洞(c 0 n t a c t h ο 1 e ) 4 6與._ 訊號.線1 4以及像素電極1 6電連接。_為了方便說明, (.. T F T - L C D 1 0中之其它元件’例如電容以及至轉接墊等等, 並未顯示於圖一中。466773 V. Description of the invention (2) A traditional liquid crystal display element basically includes a transparent substrate with a thin film transistor, a pixel electrode, and a vertical staggered scan line. ine; 〇r gate 1 i ne) and signal line (da taii ne; or signa 1 line), a color fi (Iter, substrate), and-and between the transparent substrate and the filter plate Liquid crystal material. TFT-LCD is widely used in portable information products such as notebooks and personal digital assistants (PDAs) because it has the advantages of light and thin appearance, low power consumption, and no light pollution. There is a trend to replace traditional desktop computer CRT monitors. Please refer to FIG. 1 ′ FIG. 1 is a schematic diagram of a part of a layout (1 a y 〇 t) of a conventional thin film transistor liquid crystal display (hereinafter referred to as T F T-L C D) 10. The conventional T FT-LC D 1 0 is fabricated on a transparent glass substrate 1 1. As shown in FIG. 1, the surface of the glass substrate 11 has at least one thin film transistor 40, a plurality of scanning lines 12, and a plurality of signals intersecting perpendicularly to the scanning line 12 to lines 14. In the TFT-LCD 10, each of the thin film transistors 40 is used to drive a pixel electrode 16 composed of indium tin oxide (IT0). The thin film transistor 40 is composed of a gate electrode 4 2, a source electrode 4 3, and a non-electrode 44. The gate 4 2 composed of polycrystalline stone is formed at the same time as the scanning line 12, and the source 4 3 and the end 4 4 are respectively formed by a contact hole (c 0 ntacth ο 1 e) 4 6 and ._ The signal line 14 and the pixel electrode 16 are electrically connected. _ For the convenience of explanation, (.. other components in T F T-L C D 1 0 ', such as capacitors and to transfer pads, etc.) are not shown in Figure 1.
第5頁 4 ITB -3-¾ 華 4 cn4, tt s 禁 1 o Λ s 來6 1 $ ® 。 Λ«υ 捧6 2β ms ο a 1Η· 麻麻 雜ΤΟ i Sr o 41 ^ oft 1 s' 6 2 ,®-辦6 'J β .sPage 5 4 ITB -3-¾ Hua 4 cn4, tt s ban 1 o Λ s to 6 1 $ ®. Λ «υ 66 2β ms ο a 1Η · 麻 麻 hybrid ΤΟ i Sr o 41 ^ oft 1 s '6 2, ®- Office 6' J β .s
N Q f p Λ+ IT T¾N Q f p Λ + IT T¾
(I τ Ο ) ‘ H IF 癖ΐ 拳择鉍—— d I T Ο ) 6卬 b— & $/ Μ® 。 Jtr^T* ^ Mr , $ I :^商003方洳 E 6聆脅_擗菌7 V9.,齊 4 #p003 蚵 VV > ' 屈 ItIT? ~^Γ f F政麥 ΐ ^ b^, T—rnD 6 0 6 2(I τ Ο) ‘H IF ΐΐ Boxing bismuth — d I T Ο) 6 卬 b— & $ / Μ®. Jtr ^ T * ^ Mr, $ I: ^ 商 003 方 洳 E 6 胁 害 _ 擗 菌 7 V9. , 齐 4 # p003 蚵 VV > 'Qu ItIT? ~ ^ Γ f F 政 麦 ΐ ^ b ^, T—rnD 6 0 6 2
δ· ^Μ, ftM s 1 —MM— 1 h. J, β dx, s 4Γ ,t δ. l·讲 , 蝎會 o 择藤辦弟6 1 I s* s 1818 鉍扣療 3 τ F Τ —rc D ms ^ ^ f w .s > w I寐峰唞舶 T匀T — L· C D 卬O 參嫜吝命I Lr ^ k, uv 1祕满癖舯薛70 ' $ p $ f Sr Q w ft K 4? ^β Φ ― 祕寐轉挪雜T O 峥 m 斧截*i p森砵轉齒72。^t- 4fL綠择6 4 公, Η - β 对―$ S β £ ^ 0 i $, 网I Τ Ο ( χ- e d u η d a ηΓ+ 批$ & 4fL薄择翁9 逾! 8σ31ίΛ 沐V,和菌. 隸捧寐 sV/J002 Sr Q M 金!Γ 4fL -¾¾ m f 卡 m鉍奸 s 2 璘保翁 Ϊ 棒麸器馨孬 &tr 皂 择齊 ί ?择拿卡;irljr穿 m举忤 S & β β ^ψ ΆΤ U%- f J3-雜 smA-tiTFT—rCDS P* ο φ, 1002 濟 4?隸 邀';3005 靼祕 Akn $, d^r β Sr 6 4 _t_ 4 。如 m 穿淨$ m 6 Ο Θ咖Ρ麥 Τ F Η — Lc D 昧I鱟哥 β s 释64, 栽 ^ 6 4 Ρ s- hr 蚵漆 o 6 0 s Μι4 β 466773 五、發明說明(5) 奋阒^ f圖三,圖三顯示圖二令沿著直線V_V’之剖面示 ㊁:方Ϊ 5 :是利用一種包含五次黃光暨钱刻製程(PEP) ΐ Ϊ Ϊ Ξ明玻璃基板61上形成之TFTLCD 60的部分示 二二一《 Ζ ί所不,利用本發明所形成之液晶顯示器至少 1ί Ϊ晶體70及一訊號線64。薄膜電晶體70包含有 二ΞΓη屬層所構成之閑極90、一源極94以及一没極 =策,(PEP)中形成。訊號線64與掃瞄線62係位於不同平 7 (Ml由2 ί ΐ —絕緣層9 1以及一半導體層9 2。薄膜電晶體 Λ : ί Ϊ接觸洞86與像素電極72導通,且1Τ0導線66經 /同8 5以及訊號線接觸洞8 2來連接薄膜電晶體7 〇 u及訊號線6 4 〇δ · ^ Μ, ftM s 1 —MM— 1 h. J, β dx, s 4Γ, t δ. l · Speaking, scorpion will o 6 to choose the vine to do 6 1 I s * s 1818 bismuth therapy 3 τ F Τ --Rc D ms ^ ^ fw .s > w I 寐 峰 唞 船 T Uniform T — L · CD 卬 O Reference I I Lr ^ k, uv 1 Secret Maniac Xue 70 '$ p $ f Sr Q w ft K 4? ^ β Φ ― Miscellaneous TO 杂 TO 峥 m axe * ip Mori 砵 72. ^ t- 4fL green choice 6 4 male, Η-β pair ― $ S β £ ^ 0 i $, net I Τ Ο (χ- edu η da ηΓ + batch $ & 4fL thin selection Weng 9 over! 8σ31ίΛ Mu V , And fungus. 寐 sV / J002 Sr QM gold! Γ 4fL -¾¾ mf card m bismuth s 2 璘 保 ΪΪ stick bran 孬 & tr soap selection? 择 取 卡; irljr 穿 m 举忤 S & β β ^ ψ ΆΤ U%-f J3-Miscellaneous smA-tiTFT-rCDS P * ο φ, 1002 Invited 4; Invited '3005 Secret Akn $, d ^ r β Sr 6 4 _t_ 4 Such as m wear clean $ m 6 〇 ΘCΡ 麦 ΤF Η — Lc D 鲎 I β β s release 64, plant ^ 6 4 Ρ s- hr lacquer o 6 0 s Μι4 β 466773 5. Description of the invention (5 ) Fen ^ ^ f Figure 3, Figure 3 shows the cross section along the straight line V_V 'shown in Figure 2: Ling Fang 5: It uses a five-time yellow light and money engraving process (PEP) ΐ Ϊ Ϊ Ξ Ming glass substrate The part of the TFTLCD 60 formed on 61 is shown in FIG. 21, “Z. No, the liquid crystal display formed by the present invention has at least 1 ί crystal 70 and a signal line 64. The thin film transistor 70 includes two ΞΓη metal layers. Idle pole 90, one source pole 94, and one pole pole = policy (PEP). Signal line The 64 and the scanning line 62 are located at different planes 7 (M1 by 2 ΐ ΐ — an insulating layer 9 1 and a semiconductor layer 9 2. The thin film transistor Λ: Ϊ 洞 the contact hole 86 is in conduction with the pixel electrode 72, and the 1T0 wire 66 passes through / Same as 8 5 and the signal line contact hole 8 2 to connect the thin film transistor 7 〇u and the signal line 6 4 〇
Tn/tif考圖四Α至圖四Ε,圖四Α至圖四Ε為本發明製作 一:te赭6 〇之製程示意圖。本發明製作方法主要是應用在 一轉向-列(twi s t-nemat ic,TN)式TFT-LCD 的製作上。如 ΐ 所示、/本發明TFT_LCD 60是製作在一玻璃基板61的 上 首先在玻璃基板61的.表面上全面沈積一第一令® 接著進行一第.一黃光暨罐程(㈣])積/玻璃金基屬 1的表面上形成一閘極9 〇與一掃描線(未顯示於圖中), 且間極90係與掃瞄線相連接。 —如圖四β所示,在完成該第一黃光暨蝕刻製程之後, 著在破璃基板61上全面沈積一絕緣層91.、一半導體層Tn / tif consider Figure 4A to Figure 4E, Figure 4A to Figure 4E are schematic diagrams of the manufacturing process of the present invention: te 赭 60. The manufacturing method of the present invention is mainly applied to the manufacture of a twis t-nemat ic (TN) TFT-LCD. As shown in ΐ, the TFT_LCD 60 of the present invention is fabricated on a glass substrate 61, and firstly deposits a first order® on the surface of the glass substrate 61, and then performs a first. A yellow light and can process (㈣)) A gate electrode 90 and a scanning line (not shown in the figure) are formed on the surface of the metal / glass metal base 1. The intermediate electrode 90 is connected to the scanning line. —As shown in FIG. 4β, after the first yellow light and etching process is completed, an insulating layer 91 and a semiconductor layer are completely deposited on the broken glass substrate 61.
466773 五、發明說明(6) (semiconductor layer) 92、一掺雜矽層 1〇2 與一第二金 屬層104。半導體層92可選擇多晶矽(p〇iy-siiicon)或是 非晶矽(amorphous silicon)材料,視製程或顯示面積等 條件而定。接下來,進行一第二黃光暨蝕刻製夏一 (PEP- 2),定義半導體層92、該推雜矽層1〇2以及該第二金 屬層104之圖案,用以形成一薄膜電晶體島狀結構。 如圖四c所示’進行一第三黃光暨蝕刻製程(PEP_3), 於第二金屬層1 0 4以及摻雜矽層1 〇 2中形成一訊號線6 4、源 極電極94以及没極電極96,同時完成薄膜電晶體7〇的製 作0 接著’如圖四β所示,在第三黃光暨蝕刻製程之後, 於該玻璃基板上方形成一保護層(passivation layer) 10 6 且^蓋於薄膜電晶體7〇以及該訊號線64之表 面° _後進行一第四黃光暨蝕刻製程(P E P - 4 ),以於汲極 9 6、源極3 4以及訊號線6 4上方之保護層1 〇 6中分別形成源 極接觸-洞6、沒極接觸洞8 5、以及訊號線接觸洞8 2。如圖 四E所不,接著在姑姑w t , ,τ τ π、私桃.. 壤基板6 1上全面沈積一由氧化銦錫 (I T 0 )所構成之透明道办^ , oc , Λ ^ 月導電層,.並填滿接觸洞8 6、接觸洞 8 5、以及接觸洞8 2。θ μ ^ rpffp_,A ^ ^ 取後’進行一第五黃光暨银刻製程 a 你表/ ~透明導電層中形成一備用IT0導線圖案66 以及一像素電極圖案7 2 〇466773 V. Description of the invention (6) (semiconductor layer) 92. A doped silicon layer 102 and a second metal layer 104. The semiconductor layer 92 may be made of polycrystalline silicon or amorphous silicon, depending on conditions such as manufacturing process or display area. Next, a second yellow light and etching Xiayi (PEP-2) is performed to define the patterns of the semiconductor layer 92, the doped silicon layer 102, and the second metal layer 104 to form a thin film transistor. Island structure. As shown in FIG. 4c, a third yellow light and etching process (PEP_3) is performed to form a signal line 64, a source electrode 94, and a second metal layer 104 and a doped silicon layer 102. The electrode 96 is completed at the same time as the thin film transistor 70. Then, as shown in FIG. 4β, after the third yellow light and etching process, a passivation layer 10 6 is formed on the glass substrate. After covering the thin film transistor 70 and the surface of the signal line 64 °, a fourth yellow light and etching process (PEP-4) is performed, so as to be above the drain 9 6, the source 34, and the signal line 6 4 A source contact-hole 6, a non-polar contact hole 85, and a signal line contact hole 82 are formed in the protective layer 106 respectively. As shown in Fig. 4E, then on the aunt wt,, τ τ π, private peach .. A transparent channel composed of indium tin oxide (IT 0) is fully deposited on the soil substrate 6 1 ^, oc, Λ ^ month The conductive layer fills the contact hole 86, the contact hole 85, and the contact hole 82. θ μ ^ rpffp_, A ^ ^ After picking up ', a fifth yellow light and silver engraving process is performed. A surface of the transparent conductive layer is formed with a spare IT0 wire pattern 66 and a pixel electrode pattern 7 2 〇
第9頁 67 73 :4 β β T "7 3 Ί) .我於習知製作方法,本發明製作方法利用五次黃光 皇蝕刻製程(5ΡΕΡ)以製作TFT-LCD元件,該TFT-LCD元件於 訊號線64以及掃瞄線62的交錯區域8 1上方,具有一備用區 域I Τ 0導線(r e d u n d a n t 1 〇 c a 1 i z e d I Τ 0 )藉由訊號線接觸洞 8 2以及汲極接觸洞8 5分別與訊號線6 4以及薄膜電晶體7 0電 連接。此備用區域I TO導線6 6可與像素電極7 2於一黃光暨 蝕刻製中同時形成。本發明可以有效解決由於不潔物或微 粒子所造成的點缺陷問題,提高製程良率。此外,本發明 之TFT-LCD同時具有防止訊號線斷線之功能。 以上所述僅本發明之較佳實施例,凡依本發明申請專f 利範圍所做之均等變化與修飾,皆應屬本發明專利之涵蓋 範圍。Page 9 67 73: 4 β β T " 7 3 Ί). I am familiar with the production method, the production method of the present invention uses five yellow light emperor etching process (5PEP) to make a TFT-LCD element, the TFT-LCD The device has a spare area I TO line (redundant 1 0ca 1 ized I TO 0) above the staggered area 8 1 of the signal line 64 and the scan line 62 through the signal line contact hole 8 2 and the drain contact hole 8 5 is electrically connected to the signal line 64 and the thin film transistor 70 respectively. The spare area I TO wire 66 can be formed simultaneously with the pixel electrode 72 in a yellow light and etching process. The invention can effectively solve the problem of point defects caused by impurities or micro particles, and improve the process yield. In addition, the TFT-LCD of the present invention also has a function of preventing disconnection of a signal line. The above are only the preferred embodiments of the present invention, and any equivalent changes and modifications made in accordance with the patentable scope of the present application should fall within the scope of the patent of the present invention.
第10頁 46' 466773 圖式簡單說明 圖 示 之 簡 單說 明 圖 一 為習 知TFT-LCD 之 部 份 佈局 示 意 圖 0 圖 二 為本 發明TFT- LCD 之 部 份佈 局 示 意 圖 0 圖 二 為本 發明T F T - LCD 之 剖 面示 意 圖 〇 圖 四 A至圖四E為本 發明T F T -LCD 之 製 作 方 法 示 意圖。 圖 示 之 符 號說 明 10 、 60 TFT- LCD 11 Λ 6 1 玻 璃 基 板 12 > 62 掃描 線 14 64 訊 號 線 16 72 像素 電極 30 備 用 透 明 導 電 層導線 32 > 81 交錯 區域 40 70 薄 膜 電 晶 體 42 % 90 閘極 43 9 4 源 極 44 96 汲極 46 86 源 極 接 觸 洞 48 、 85 没極 接觸洞 50 > 83 虛 線 方 框 52 82 訊號 線接觸洞 66 備 用 區 域I TO導線 91 絕緣 層 92 半 導 體 層 1 02 掺雜 碎層 1 04 第 二 金 屬 層 1 06 保護 層Page 10 46 '466773 Schematic illustrations of the diagrams Brief description of the diagrams Figure 1 is a schematic layout of a part of a conventional TFT-LCD 0 Figure 2 is a schematic layout of a part of a TFT-LCD of the present invention 0 Figure 2 is a TFT of the present invention- A schematic cross-sectional view of an LCD. Figures 4A to 4E are schematic diagrams of a method for manufacturing a TFT-LCD of the present invention. Explanation of symbols in the figure 10, 60 TFT-LCD 11 Λ 6 1 Glass substrate 12 > 62 Scan lines 14 64 Signal lines 16 72 Pixel electrodes 30 Spare transparent conductive layer wires 32 > 81 Interlaced area 40 70 Thin film transistor 42% 90 Gate 43 9 4 Source 44 96 Drain 46 86 Source contact hole 48, 85 Non contact hole 50 > 83 Dotted box 52 82 Signal line contact hole 66 Spare area I TO wire 91 Insulation layer 92 Semiconductor layer 1 02 doped chip layer 1 04 second metal layer 1 06 protective layer
第11頁Page 11