JP2000284326A - Liquid crystal display device and its production - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify the patterning process of wiring and electrodes, to maintain connection stability at the terminals of wiring and to improve reliability of the product. SOLUTION: This device consists of an active matrix substrate, a color filter substrate and a liquid crystal layer 18 of a liquid crystal compsn. held in the gap between the active matrix substrate and the color filter substrate. The active matrix substrate is prepared by forming gate wiring (electrodes) 2, 3, gate insulating layer 4, semiconductor layer 5, contact layer 6, source and drain wirings 8, 9, passivation layer 10 and pixel electrode 11 on the inner face of an insulating substrate 1. The color filter substrate is prepared by forming a color filter layer 14, smoothening layer 15, common electrode 16 and insulating protective layer 17 on the inner face of an insulating substrate 12. In this device, the gate wiring 2, 3 and source and drain wirings 7, 8 consist of laminar wirings of an alloy layer 3 and an aluminum alloy layer 2. The alloy layer essentially comprises molybdenum and contains at least one of chromium, titanium, tantalum and niobium as the additive elements which dissolves molybdenum as a sold soln.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a liquid crystal display device having a high aperture ratio and a method of manufacturing the same, and more particularly to an active matrix type liquid crystal display device having active elements such as thin film transistors and a method of manufacturing the same.

[0002]

2. Description of the Related Art A liquid crystal display device basically uses a liquid crystal panel in which a liquid crystal layer is sandwiched between two substrates at least one of which is made of transparent glass or the like, and a pixel formed on each of the two substrates. A type in which a predetermined pixel is turned on and off by selectively applying a voltage to an electrode for formation (a so-called simple matrix type), and a liquid crystal in which an active element (switching element) for pixel selection is arranged on the seed electrode. It is broadly classified into a type (for example, an active matrix type using a thin film transistor (TFT) as an active element) in which a predetermined pixel is turned on and off by forming a panel and selecting the active element.

In particular, the latter active matrix type liquid crystal display device has become the mainstream of the liquid crystal display device because of its contrast performance, high-speed display performance and the like.

In recent years, there has been a demand for a larger screen area. To construct a large-area liquid crystal display device, aluminum (Al) or copper (Cu) having a low specific resistance is used as a wiring material. Is suitable. In particular, aluminum wiring is suitable as this kind of wiring material because of its excellent corrosion resistance, and its practical use is progressing.

[0005] On the other hand, however, aluminum wiring has the disadvantage that heat resistance is inferior and contact characteristics with a silicon (Si) film are not good. Therefore, high-melting films are stacked above and below the aluminum film.

In particular, the drain wiring has a long wiring length in a pixel, and has a large effect on the aperture ratio. That is, if the line width is increased to prevent disconnection, the aperture ratio will decrease.

Further, if a plurality of photolithography steps are performed for forming the drain wiring, it is necessary to increase the pattern matching allowance, which causes a reduction in the aperture ratio.
Therefore, conventionally, the drain wiring has been etched by one photolithography step.

[0008] Materials that can be etched together with the aluminum wiring include molybdenum (Mo) and titanium (Ti).

An active matrix type liquid crystal display device of this type is disclosed, for example, in Japanese Patent Application Laid-Open No. 63-309921.

[0010]

The batch etching of the laminated structure of the molybdenum (Mo) film and the aluminum (Al) layer can be realized by using a wet etching method.
However, in this case, since the molybdenum (Mo) layer has poor dry etching resistance, molybdenum (Mo) itself is etched in a dry etching step for processing a terminal portion of a passivation layer formed thereon, and aluminum under the molybdenum (Mo) layer is etched. (Al) appears on the surface.

In this case, when a transparent conductive layer (oxide transparent conductive layer, for example, indium tin oxide: ITO) such as a pixel electrode is formed on the passivation layer, a contact between aluminum (Al) and the oxide transparent conductive film is formed. There is a disadvantage that the characteristics are not good and the contact resistance gradually increases.

Further, pure molybdenum has poor adhesion to a resist or a base film of an etching mask, and there has been a problem of disconnection due to resist peeling and film peeling from a substrate.

Further, when a titanium (Ti) layer and an aluminum (Al) layer are laminated to form a laminated wiring, it is possible to dry-etch the laminated wiring collectively using a chlorine-based gas. For this purpose, when the source and drain wirings are processed, the underlying semiconductor layer (a-S
It was necessary to have a channel passivation structure provided with a protective film so that the i-layer) was not etched.

In this case, there is a disadvantage that the manufacturing process becomes complicated as compared with the so-called back channel etching structure.

An object of the present invention is to solve the above-mentioned problems of the prior art, and to make an electrode composition and an electrode or wiring by using an alloy composition which can maintain etching selectivity with other layers while maintaining a simple layer structure. An object of the present invention is to provide a liquid crystal display device which simplifies a patterning process, secures connection stability at a terminal portion of a wiring, and improves product reliability, and a method of manufacturing the same.

[0016]

In order to achieve the above object, the present invention makes it possible to perform batch etching by employing an alloy layer as a gate wiring, a source and a drain wiring. To describe a typical configuration of the present invention,
It is as follows.

(1) An active matrix substrate having a gate wiring, a gate insulating layer, a semiconductor layer, a contact layer, source and drain wirings, a passivation layer, and a pixel electrode formed on an inner surface of an insulating substrate, and a color filter layer formed on an inner surface of the insulating substrate. A color filter substrate on which a smooth layer, a common electrode, and an insulating protective layer are formed, and a liquid crystal layer made of a liquid crystal composition interposed between opposing gaps between the active matrix substrate and the color filter substrate. An alloy layer in which the wiring is mainly composed of molybdenum (Mo) and contains at least one of chromium (Cr), titanium (Ti), tantalum (Ta), and niobium (Nb) as an additional element in which molybdenum is dissolved; , And an aluminum alloy layer.

(2) The gate wiring in (1) is composed of a molybdenum-chromium alloy (Mo-Cr) or two layers of a titanium alloy and an aluminum alloy, and the source and drain wirings are formed of a molybdenum-chromium alloy or a titanium alloy. And a three-layer structure of aluminum alloy, molybdenum-chromium alloy or titanium alloy.

(3) An active matrix substrate having a gate wiring, a gate insulating layer, a semiconductor layer, a contact layer, source and drain wirings, a passivation layer, and a pixel electrode formed on the inner surface of the insulating substrate, and a color filter layer formed on the inner surface of the insulating substrate. A color filter substrate on which a smooth layer, a common electrode, and an insulating protective layer are formed, and a method for manufacturing a liquid crystal display device including a liquid crystal layer formed of a liquid crystal composition interposed between opposing gaps between the active matrix substrate and the color filter substrate. The gate wiring, the source and the drain wiring are formed by simultaneously etching a molybdenum alloy containing at least one of chromium, titanium, tantalum and niobium as an additive element and an aluminum alloy with the same etching solution. .

(4) An active matrix substrate having a gate wiring, a gate insulating layer, a semiconductor layer, a contact layer, source and drain wirings, a passivation layer, and a pixel electrode formed on the inner surface of the insulating substrate, and a color filter layer formed on the inner surface of the insulating substrate. A color filter substrate on which a smooth layer, a common electrode, and an insulating protective layer are formed, and a method for manufacturing a liquid crystal display device including a liquid crystal layer formed of a liquid crystal composition interposed between opposing gaps between the active matrix substrate and the color filter substrate. Dry etching is used for processing the passivation layer of the active matrix substrate, and the etching selectivity of the passivation layer to a molybdenum alloy containing at least one of chromium, titanium, tantalum, and niobium as an additional element of the source and drain wirings is determined. It is special that 4 or more To.

Next, the reason why the object of the present invention can be achieved by the above configuration will be described in detail.

In a thin film transistor (TFT) having a channel etching structure, a wet etching method is suitable for etching source and drain wirings. This is because, in the dry etching method, the selectivity of the a-Si layer, which is the semiconductor layer under the fluorine-based gas and the chlorine-based gas, is small, and only the wiring cannot be etched.

The laminated wiring of the pure molybdenum (Mo) layer and the aluminum layer is formed by using a wet etching solution composed of phosphoric acid, nitric acid, acetic acid and water while ensuring a sufficient selectivity with respect to the a-Si layer. Thus, the film having the laminated structure can be etched at a time.

However, after that, when dry etching is used for etching the passivation layer, pure molybdenum has no resistance. Therefore, in order to perform batch etching with the aluminum layer using a phosphoric acid-based etching solution, a fluorine-based gas is used. As an alloy element having dry etching resistance, an element containing at least one of chromium, titanium, tantalum, and niobium is added to molybdenum.

These elements form a solid solution with molybdenum in all compositions. That is, it does not precipitate as a second phase in the molybdenum matrix. Even if a small amount of the above element is added, the element is uniformly added to molybdenum, so that the etching behavior of the molybdenum alloy does not become uneven in the layer.

That is, in the etching characteristics of the molybdenum alloy and the dry etching resistance of the passivation layer (silicon nitride: SiN) layer formed on the layer during the dry etching, the etching is partially uneven in the layer due to the uneven etching rate. No residue is generated.

Since the elements of chromium, titanium, tantalum, and niobium have a considerably higher boiling point than that of molybdenum, the dry etching resistance of the alloy layer can be increased by adding a small amount of these elements.

When chromium is added to molybdenum, by adding 0.5 wt% or more of chromium, dry etching resistance can be added while enabling etching with a phosphoric acid-based etchant.

With a phosphoric acid-based etching solution containing chromium, chromium itself cannot be etched. However, since chromium is an element that forms a solid solution with molybdenum in a total composition, the second phase must be dispersed in the layer. Since chromium itself does not dissolve in a phosphoric acid-based etching solution, etching can be performed with a small amount because the chromium itself is not dissolved in a single phase.

The upper limit of the amount of addition of the above elements is determined by the etching rate. Since it has been found that the addition of 10 wt% makes it impossible to etch the molybdenum alloy itself, it is desirable that the addition amount of chromium be 0.5 wt% or more and less than 10 wt%.

By adding 0.5% by weight or more of titanium to molybdenum, dry etching resistance to a fluorine-based etching gas can be obtained, and the selectivity to the passivation layer increases as the amount of addition increases.

Similarly, when titanium, tantalum, and niobium are added, they cannot be etched with a phosphoric acid-based etching solution. Since titanium, tantalum, and niobium form a solid solution with molybdenum in a total composition, it can be removed as an alloy up to about 5 wt%. Further, by adding 0.5% by weight or more of hydrofluoric acid or ammonium fluoride to the etching solution using phosphoric acid, nitric acid, acetic acid, and water, titanium,
Tantalum and niobium can be dissolved.

In this case, if the addition amount of hydrofluoric acid or ammonium fluoride is too large, the a-Si layer and the gate insulating layer (S
Since the etching rate of the (iN layer) also increases and is etched, the upper limit of the added amount is about 10 wt%.

The greater the amount of titanium, tantalum and niobium added, the greater the amount of hydrofluoric acid or ammonium fluoride added to the etchant. But,
In order to minimize the etching of the a-Si layer while etching the alloy element, the amount of hydrofluoric acid or ammonium fluoride is preferably within 5 wt%.

Titanium which can be etched in this addition range,
The addition amounts of tantalum and niobium are within 20 wt%. Therefore, titanium, tantalum, into molybdenum,
And the addition amount of niobium is 0.5 wt% or more and 20 wt%
Is less than.

By laminating the above-mentioned molybdenum-chromium, titanium, tantalum, and niobium alloys, a laminated structure of a molybdenum alloy and aluminum can be subjected to collective etching.

As the amount of addition of these alloy elements increases, the etching rate of the molybdenum alloy decreases. Therefore, by controlling the amount of addition, the etching rate of the molybdenum alloy and the aluminum alloy can be adjusted, and the etching shape of the laminated structure can be controlled.

Further, by adjusting the composition of the etchant so that the molybdenum alloy layer and the aluminum alloy layer have substantially the same etching rate, it is possible to process the wiring end face into a forward tapered shape.

Further, since pure molybdenum has an oxide film that is not dense and an oxide of molybdenum is etched by a developer, a gap is easily formed between the resist and the metal layer. As a result, the etchant may seep into the gaps, leading to a reduction in wiring dimensions or disconnection.
Oxide prevents dissolution by adding titanium, tantalum, niobium, and chromium, which are stable to the alkali developer.
Wiring thinning can be prevented.

In particular, when titanium is added, titanium oxide (TiO ₂ ) generated on the surface reacts with light and decomposes organic substances attached to the surface by itself, so that surface contamination can be removed by itself and the adhesion of the resist can be stabilized. And a local resist defect can be prevented.

Further, when titanium is added, surface contamination is removed, and the hydrophobic molybdenum surface can be changed to fresh water. By making the molybdenum surface new water, the occurrence of water stain on the surface can be suppressed, and local oxidation and contamination can be prevented.

In the case of the gate wiring, the wiring has a two-layer structure in which a molybdenum alloy is laminated only on the aluminum layer. This is because the adhesion of the molybdenum layer is reduced on the insulating substrate (glass substrate). In addition, in order to prevent the breakage of latent scratches due to minute scratches on the glass substrate which is an insulating substrate, it is better to directly form an aluminum layer on the insulating substrate.

In the case of the source and drain wirings, a three-layer structure in which a molybdenum alloy layer is stacked above and below an aluminum alloy layer is formed so that the lower layer is in contact with the a-Si layer and the upper layer is in the uppermost layer. A contact with the transparent pixel electrode can be secured.

According to the structure of the present invention, the resistance of the gate, source and drain wirings can be reduced, and a large-area active matrix substrate can be manufactured by five photolithography processes. Further, since the low-resistance drain wiring can be made thinner, the aperture ratio can be greatly improved.

The present invention is not limited to the above-described configuration, and various modifications can be made without departing from the technical concept of the present invention.

[0046]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is a schematic sectional view of a main part for explaining one embodiment of a liquid crystal display device according to the present invention. This liquid crystal display device is made of a liquid crystal composition in an opposing gap between an active matrix substrate having a thin film transistor TFT or the like formed on the inner surface of a glass substrate 1 and a color filter substrate having a color filter 14 formed on the inner surface of a glass substrate 12. The liquid crystal layer 18 is sandwiched therebetween.

FIG. 2 is a schematic cross-sectional view of a main part of a liquid crystal display device according to an embodiment of the present invention, illustrating a laminated structure of gate wirings. FIG. FIG. 5 is a schematic cross-sectional view of a main part, illustrating an example of a wiring stack structure. FIG. 4 shows a thin film transistor T
This shows a structure in which a source and a drain wiring at a location distant from the FT and a wiring terminal is formed at the end.

That is, as shown in FIG. 1, in the active matrix substrate, an aluminum-9 wt% niobium alloy is formed as an aluminum wiring 2 on the inner surface of a glass substrate 1. Next, as the molybdenum layer 3, molybdenum-
5 wt% chromium alloy (Mo-5 wt% Cr) or molybdenum-10 wt% titanium alloy (Mo-10 wt% T
i) is continuously formed at a film formation temperature of 120 ° C. by a sputtering method.

After a resist pattern for the gate wiring is formed by photolithography, wet etching is carried out collectively with an etching solution comprising phosphoric acid, nitric acid, acetic acid and water. When a Mo-10 wt% Ti alloy is used as the molybdenum alloy, an etching solution further containing ammonium fluoride is used. By adjusting the composition of the molybdenum alloy and the composition of the etching solution so that the etching rate of the molybdenum alloy becomes slightly faster than that of the aluminum alloy, the end face shape of the wiring is processed into a forward tapered shape as shown in FIG.

After the gate wiring is etched, the resist is stripped off, and the gate insulating layers 4 and i of SiN are formed by plasma CVD.
The −a-Si layer 5 and the n + a-Si layer 6 are continuously formed. Then, in order to process the island of the a-Si layer, a resist is applied in the same manner as in the processing of the gate wiring, and i is applied by dry etching.
Etching the -a-Si layer 5 and the n + a-Si layer 6.

After stripping the processing resist on the islands of the a-Si layer, as shown in FIG. 3, a molybdenum-titanium alloy (Mo-Ti alloy) layer 2 'for source and drain wirings, an aluminum-niobium alloy A (Al-Nb alloy) layer 2 and a molybdenum-titanium alloy (Mo-Ti alloy) layer 3 are successively formed to form a three-layer structure layer. Next, a resist for a source electrode and a drain electrode is formed by a photolithography process.

Then, similarly to the etching process of the gate wiring, the above-mentioned multilayer structure layer is collectively etched by an etching solution of a mixed acid composed of phosphoric acid, nitric acid, acetic acid and water.
When etching with phosphoric acid to which nitric acid is added, the etching rate of pure molybdenum (Mo) is aluminum (A).
Since the etching rate is much faster than the etching rate of 1), only the molybdenum layer is etched quickly and quickly, and does not have a good shape. Therefore, molybdenum (Mo) is replaced by chromium (C
r), titanium (Ti), and tantalum (Ta) are added to lower the etching rate of the alloy to slightly exceed the etching rate of aluminum.

FIG. 5 is an explanatory diagram of the dependence of the wet etching rate of metal wiring on the amount of alloy addition. FIG. 5 also shows the dependency of the addition amount of the molybdenum alloy to which tungsten (W) is added for reference.

That is, 2 wt% is added for chromium (Cr), and 5 to 20 for titanium (Ti) and tantalum (Ta).
With the addition of wt%, the etching rate of the molybdenum alloy can be set slightly faster and faster than that of aluminum (Al).

Further, by adjusting the composition of the mixed acid, it becomes possible to process the end face shape of the wiring of the three-layered structure layer into a forward tapered shape.

Although the etching time is long in the continuous etching of the laminated structure layer, the adhesion between the molybdenum alloy and the resist can be greatly improved by adding titanium. With pure chromium, the surface oxide film easily dissolves in the developing solution, and as a result, minute cavities are formed at the interface between the resist and the laminated structure layer, and the etching solution penetrates there and the wiring becomes thin locally. Or break.

However, when the added titanium is oxidized to titanium oxide, contaminants on the surface are decomposed, and the fresh water on the surface can be increased. As a result, local water spots can be prevented, and disconnection due to poor adhesion of the resist can be prevented.

Next, using the passivation of the source and drain wirings as a mask, the n + a-Si layer 6 in the channel portion is removed by dry etching.

After that, a silicon nitride layer (SiN) as the passivation layer 10 is formed by using the CVD method.

For each terminal of the gate wiring and the drain wiring, a through hole is formed on each terminal. The through hole of the drain wiring is indicated by reference numeral 19 in FIG. 1, and the through hole of the gate wiring is indicated by reference numeral 20 in FIG.

As shown in FIG. 4, when forming a gate wiring terminal, holes are formed in both the passivation layer 10 and the gate insulating layer 4. In this embodiment, a through-hole pattern is formed using the same photomask, and both layers are simultaneously processed by dry etching.

By forming a layer having a high etching rate on the uppermost portion of the passivation layer 10 and preferentially performing side etching on the uppermost portion, the end surface shapes of the passivation layer 10 and the gate insulating layer 4 are formed into a forward tapered shape. Process into

Since the thicknesses of the passivation layer 10 and the gate insulating layer 4 at the gate wiring terminal are larger than those of the thin film transistor TFT shown in FIG. Deeper than the through hole 19. Therefore,
During the processing of the through holes, the through holes 19 of the drain and source wirings are processed first. The lower electrode, that is, the electrode having a laminated structure of the aluminum alloy layer 8 and the molybdenum alloy layer 9 in FIG. 1 is exposed to the dry etching atmosphere for a long time.

At this time, if the metal in the upper layer of the lower layer structure is pure molybdenum, the etching rate is high, and the aluminum layer below the pure molybdenum layer appears in the upper layer. FIG. 6 shows the dry etching rates when various elements were added to increase the dry etching resistance of the upper pure molybdenum layer.

That is, FIG. 6 is an explanatory diagram of the dependency of the dry etching rate of the metal wiring on the alloy addition amount. As shown in FIG. 6, all the elements studied have the effect of reducing the dry etching rate. This is presumably because the alloying increases the binding energy of each element. Among these, in particular, about 17% for niobium (Nb).
at%, about 4 at% for tantalum (Ta), titanium (T
In the case of adding about 3 at% in i) and about 2 at% or more in chromium (Cr), the dry etching rate can be reduced to 1/4 or less of the dry etching rate of silicon nitride (SiN) as the passivation layer 10. .

This means that the molybdenum alloy to which the above-mentioned elements are added can reduce the dry etching rate to １ ／ or less of that of silicon nitride. That is, by stacking a molybdenum alloy to which the above elements are added on the aluminum layer, it is possible to prevent aluminum from appearing on the electrode surface of the through holes for the drain and source wiring terminals.

Since the dry etching resistance is improved, if there is no problem in resistance, Mo-Ti, Mo-T
a, Mo-Cr, Mo-W single phase can also be applied as wiring. Also in this case, wet etching can be used for the etching.

After the formation of the through-hole, good contact with the ITO (indium tin oxide) film serving as the pixel electrode is maintained in the drain and source electrodes, and good contact with the ITO film 11 formed thereon is formed in the drain wiring terminal. Therefore, it is possible to provide a liquid crystal display device in which the connection stability at the terminal portion of the wiring is secured and the reliability of the product is improved.

Next, the configuration of the main part of an active matrix type liquid crystal display device to which the present invention is applied will be described.

FIG. 7 is a schematic plan view of one pixel portion formed on an active matrix substrate of a liquid crystal display device to which the present invention is applied. Reference numeral 1 denotes an active matrix substrate, 2A denotes a gate wiring (electrode), 3A denotes a drain wiring, 3B denotes a drain electrode, 3C denotes a source electrode, 11A denotes a pixel electrode, 5 denotes a semiconductor layer, 19 denotes a contact hole, and TFT denotes a thin film transistor. Since the drain wiring 3A, the drain electrode 3B and the source electrode 3C have the same laminated structure, they are collectively shown as drain and source wirings (electrodes) in FIG. In addition, the drain wiring (electrode) 3A and the source wiring (electrode) 3B are replaced during operation. For convenience of explanation, they are described as drain or source wiring (electrode) in FIG.

The drain wiring 3A, the drain electrode 3B, and the source electrode 3C have the laminated structure of the aluminum alloy layer 8 and the molybdenum alloy layer 9 in FIG. 1, and the gate wiring (electrode) 2A is the aluminum alloy layer 2 in FIG.
And a molybdenum alloy layer 3.

Substrate 1 on which gate wiring (electrode) 2A is formed
A gate wiring (electrode) 2A and a silicon nitride (SiN) layer as a gate insulating layer 4 for interlayer insulation between the drain wiring 3A, the drain electrode 3B, and the source electrode 3C are formed on the entire surface of the semiconductor device (see FIG. 1). (Fig. 1).

Then, the gate electrode 2A and the drain wiring 3
A thin film transistor TFT is formed above the gate insulating layer 4 at one corner of the pixel region surrounded by A. In the region where the thin film transistor TFT is formed, amorphous silicon is formed on the surface of the gate insulating layer 4 located above the gate electrode 3B on the passivation layer 4 functioning as a gate insulating film so as to straddle the gate electrode 2A. A semiconductor layer 5 made of (a-Si) is formed.

The semiconductor layer 5 is formed below the formation region of the drain electrode 3B and the source electrode 3C. The reason why the drain electrode 3B and the source electrode 4 have a stacked structure of the semiconductor layer 5 is to prevent disconnection and to reduce the capacitance between the gate electrode 3A and the intersection.

A drain electrode 3B and a source electrode 3C are formed on the surface of the semiconductor layer 5 in the region where the thin film transistor TFT is formed, and these electrodes 3B and 3C have the gate electrode 2A therebetween when viewed in plan. Are arranged facing each other.

The drain electrode 3 on the surface of the semiconductor layer 5
At the interface between B and the source electrode 3C, a contact layer in which the semiconductor layer 5 is doped with a high concentration of impurities is formed, but is not shown. This high-concentration impurity layer is formed on the entire surface when the semiconductor layer 5 is formed, and the impurity layer exposed from each electrode is etched by using a drain electrode or a source electrode formed later as a mask. Formed by Then, the drain electrode 3B and the source electrode 3C are formed in the same step and of the same material.

Further, as shown in FIG.
C is formed so as to extend to the formation region of the pixel electrode 11A, and is configured to make contact with the pixel electrode 11A in this extended portion. In FIG. 1, this pixel electrode 11A is shown as ITO11.

A passivation layer 10 made of, for example, a silicon nitride film (SiN) is formed on the entire surface of the substrate 1 thus processed in order to avoid direct contact of the liquid crystal with the thin film transistor TFT (FIG. 2). (Fig. 1).
In the passivation layer 10, a contact hole 19 exposing a part of the extension of the source electrode 3C is formed.

Then, in the pixel region on the upper surface of the passivation layer 10, a pixel electrode 5 made of a transparent conductive layer such as an ITO film is formed. The pixel electrode 11A is electrically connected to the source electrode 3C through the contact hole 19.

In this case, a part of the pixel electrode 11A is formed so as to extend over another adjacent gate electrode 2A 'different from the gate electrode 2A for driving the thin film transistor TFT, whereby the pixel electrode 11A An additional capacitor Cadd having a stacked body of the gate insulating layer 4 and the passivation layer 10 interposed between the adjacent gate electrode 2A 'and the dielectric film is formed.

As shown in FIG. 1, the active matrix substrate 1 on which various films are formed as described above is the other substrate (color filter substrate) 1 with the liquid crystal layer 18 interposed therebetween.
It is bonded to 2. On the liquid crystal layer LC side of the color filter substrate 12, a plurality of color filters 14 partitioned by a black matrix 13;
A common electrode 16 common to each pixel region is formed of, for example, ITO via a smooth layer 15 that covers the black matrix 13. Note that a protective film 17 is formed on the common electrode 16, and an interface between the protective film 17 and the liquid crystal layer 18.
At the interface between the active matrix substrate 1 and the liquid crystal layer 18, an alignment film for regulating the alignment direction of the liquid crystal composition constituting the liquid crystal layer 18 is formed, but is not shown.

With the above-described configuration, it is possible to obtain a liquid crystal display device in which various wirings (electrodes) are formed favorably, and connection stability at terminals thereof is ensured to improve product reliability. it can.

FIG. 8 is a schematic plan view for explaining a wiring structure near one pixel of an active matrix substrate constituting a liquid crystal display device to which the present invention is applied, wherein 1 is a substrate, 2A gate wiring, and 2A 'is an adjacent gate. Wiring, 3A is a drain wiring, 3A 'is an adjacent drain wiring, 3B is a drain electrode,
3C is a source electrode, 11A is a pixel electrode, TFT is a thin film transistor, and Cadd is an additional capacitance element.

The central area except the periphery of the active matrix substrate 1 is a display area. As described above, this display area is sealed with a liquid crystal layer in a bonding gap with another color filter substrate. ing.

In this display area, gate wirings 2A and 2A 'extending in the X direction in the figure and drain wirings 3A provided in the Y direction are formed. Further, a drain electrode 3B and a source electrode 3C which are insulated from the gate wirings 2A and 2A 'and extend in the Y direction and are provided in the X direction are formed.

The areas surrounded by the gate wirings 2A, 2A 'and the drain wirings 3A, 3A' each constitute one pixel area. That is, the display region is formed by an aggregate of a large number of pixel regions arranged in a matrix.

Each pixel region has a thin film transistor TF which is turned on by the supply of a scanning signal from the gate line 2A.
T and a pixel electrode 11A to which a video signal is supplied from the drain wiring 3A via the turned-on thin film transistor TFT is formed.

In addition to the thin film transistor TFT and the pixel electrode 11A, an additional capacitance element Cadd is provided between the pixel electrode 11A and another adjacent scanning signal line 2A 'different from the gate wiring 2A for driving the thin film transistor TFT.
Are formed.

The additional capacitance element Cadd is provided to store a long video signal in the pixel electrode 5 even when the thin film transistor TFT is turned off.

In this type of liquid crystal display device, the above-mentioned various wirings for selecting pixels are formed on the substrate 1 by using various film forming means and patterning means as described in the above embodiment. .

FIG. 9 is an exploded perspective view for explaining the whole structure of an active matrix type liquid crystal display device to which the present invention is applied. FIG. 1 illustrates a specific structure of a liquid crystal display device (hereinafter, referred to as an MDL in which a liquid crystal display panel, a circuit board, a backlight, and other components are integrated) according to the present invention.

SHD is a shield case (also called a metal frame) made of a metal plate, WD is a display window, INS1
To 3 are insulating sheets, PCB1 to 3 are circuit boards (PCB1
Is the drain side circuit board: the circuit board for driving the video signal wiring,
PCB2 is a gate side circuit board: a scanning signal wiring driving circuit board, PCB3 is an interface circuit board), JN1
3, a joiner for electrically connecting the circuit boards PCB1 to PCB3, a tape carrier package for TCP1 and TCP2, a liquid crystal panel for PNL, a rubber cushion for GC, IL
S is a light shielding spacer, PRS is a prism sheet, SPS is a diffusion sheet, GLB is a light guide plate, RFS is a reflection sheet, M
CA is a lower case (mold frame) formed by integral molding, MO is an MCA opening, LP is a fluorescent tube, L
PC is a lamp cable, GB is a rubber bush supporting the fluorescent tube LP, BAT is a double-sided adhesive tape, BL is a backlight made of a fluorescent tube, a light guide plate, etc., and a liquid crystal display is formed by stacking diffusion plate members in the arrangement shown in the figure. The module MDL is assembled.

The liquid crystal display module MDL has two kinds of storage / holding members of a lower case MCA and a shield case SHD, and includes insulating sheets INS1 to 3 and circuit boards PCB1 to PCB1.
3. A metal shield case SHD in which the liquid crystal display panel PNL is housed and fixed, and a lower case MCA in which a backlight BL including a fluorescent tube LP, a light guide plate GLB, a prism sheet PRS, and the like are housed are combined.

An integrated circuit chip for driving each pixel of the liquid crystal display panel PNL is mounted on the drain side circuit board PCB1, and an interface circuit board PCB3 receives video signals from an external host, and controls timing signals and the like. An integrated circuit chip that receives signals, a timing converter TCON that processes timing to generate a clock signal, and the like are mounted.

The clock signal generated by the timing converter is integrated on the video signal line driving circuit board PCB1 via the clock signal line CLL laid on the interface circuit board PCB3 and the video signal line driving circuit board PCB1. Supplied to the circuit chip.

The interface circuit board PCB3 and the video signal line driving circuit board PCB1 are multilayer wiring boards, and the clock signal line CLL is connected to the interface circuit board PCB3 and the video signal line driving circuit board PC
It is formed as an inner wiring of B1.

The liquid crystal display panel PNL is formed by laminating a TFT substrate on which TFTs and various wirings / electrodes are formed, and a filter substrate on which a color filter is formed, and sealing a liquid crystal in a gap therebetween. , A TFT-side circuit board PCB1, a gate-side circuit board PCB2, and an interface circuit board PCB3 for driving TFTs are connected by tape carrier packages TCP1 and TCP2, and the circuit boards are connected by joiners jN1, 2, and 3. .

According to the above-described liquid crystal display device, it is possible to shorten the manufacturing steps of various wirings and electrodes of the liquid crystal panel,
A highly reliable liquid crystal display device in which occurrence of disconnection or the like is reduced can be provided.

The present invention is not limited to the above-described thin film transistor type liquid crystal display device, but can be similarly applied to other types of liquid crystal display devices and other semiconductor element wiring or electrode patterning.

[0101]

As described above, the gate wiring (electrode) and the source and drain wirings (electrodes) are mainly composed of molybdenum, and chromium, titanium,
By forming a laminated wiring of an alloy layer containing at least one of tantalum and niobium as an additional element and an aluminum alloy layer, it is easy to reduce the resistance of the wiring for increasing the area of the screen, and It is possible to provide a low-cost and highly reliable liquid crystal display device free from display defects by simplifying the photoetching process of the wiring or the electrode.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view of a main part illustrating an embodiment of a liquid crystal display device according to the present invention.

FIG. 2 is a schematic cross-sectional view of a main part, illustrating a laminated structure of a gate wiring of one embodiment of the liquid crystal display device according to the present invention.

FIG. 3 is a schematic cross-sectional view of an essential part for explaining an example of a laminated structure of source and drain wirings in one embodiment of the liquid crystal display device according to the present invention.

FIG. 4 is a schematic cross-sectional view of an essential part for explaining an example of a structure of a wiring terminal at an end of a source and a drain wiring in one embodiment of the liquid crystal display device according to the present invention.

FIG. 5 is an explanatory diagram of the dependence of the wet etching rate of metal wiring on the amount of alloy addition.

FIG. 6 is an explanatory diagram of the dependence of the dry etching rate of metal wiring on the amount of alloy addition.

FIG. 7 is a schematic plan view of one pixel portion formed on an active matrix substrate of a liquid crystal display device to which the present invention is applied.

FIG. 8 is a schematic plan view illustrating a wiring structure in the vicinity of one pixel of an active matrix substrate constituting a liquid crystal display device to which the present invention is applied.

FIG. 9 is an exploded perspective view illustrating the overall configuration of an active matrix liquid crystal display device to which the present invention is applied.

[Explanation of symbols]

 Reference Signs List 1 active matrix substrate 12 color filter substrate 18 liquid crystal layer 2 aluminum alloy layer 3 molybdenum alloy layer 4 gate insulating layer 5 semiconductor layer (ia-Si layer) 6 contact layer (n + a-Si layer) 7 molybdenum alloy layer 8 aluminum alloy Layer 9 Molybdenum alloy layer 10 Passivation layer 11 Transparent conductive layer (ITO) 12 Molybdenum alloy layer 19, 20 Through holes.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification FI FI Theme Court ゛ (Reference) H04N 5/66 102 H01L 29/78 616V 616U 617M 617L (72) Inventor Takahiro Ochiai 3300 Hayano Mobara City, Chiba Prefecture F-term (Reference) 2H092 JA26 JA28 JA29 JA40 JA44 JA46 JB57 JB64 KA05 KA07 KA12 KA19 KB24 MA07 MA18 NA27 NA28 5C058 AA09 AB01 BA08 BA35 5C094 AA02 AA44 BA03 BA43 CA19 CA23 EA03 FB12 FB14 GB01 5F110 AA16 BB01 CC07 DD02 EE03 EE06 EE14 EE23 EE44 FF03 FF30 GG02 GG15 GG35 GG45 HK03 HK06 HK09 HK16 HK22 HK33 HK35 HL07 HM03 NN02 NN24 NN35 NN72 QQ03 Q05

Claims (4)

[Claims] An active matrix substrate having a gate wiring, a gate insulating layer, a semiconductor layer, a contact layer, a source and drain wiring, a passivation layer and a pixel electrode formed on an inner surface of an insulating substrate; a color filter layer on an inner surface of the insulating substrate; A color filter substrate on which a smooth layer, a common electrode, and an insulating protective layer are formed, and a liquid crystal layer made of a liquid crystal composition interposed between opposing gaps between the active matrix substrate and the color filter substrate; Is composed of a laminated wiring of an alloy layer containing molybdenum as a main component, at least one of chromium, titanium, tantalum, and niobium which forms a solid solution of molybdenum as an additional element, and an aluminum alloy layer. Liquid crystal display. 2. The semiconductor device according to claim 1, wherein said gate wiring comprises two layers of a molybdenum-chromium alloy or a titanium alloy and an aluminum alloy; The liquid crystal display device according to claim 1, wherein the liquid crystal display device has a three-layer structure of an alloy. 3. An active matrix substrate having a gate wiring, a gate insulating layer, a semiconductor layer, a contact layer, a source and drain wiring, a passivation layer, and a pixel electrode formed on an inner surface of an insulating substrate; a color filter layer on an inner surface of the insulating substrate; A method for manufacturing a liquid crystal display device comprising: a color filter substrate on which a smoothing layer, a common electrode, and an insulating protective layer are formed; and a liquid crystal layer made of a liquid crystal composition interposed between opposing gaps between the active matrix substrate and the color filter substrate. The gate wiring, the source and the drain wiring are formed by collective etching of a molybdenum alloy and an aluminum alloy containing at least one of chromium, titanium, tantalum, and niobium as additional elements by the same etching solution. Of manufacturing a liquid crystal display device. 4. An active matrix substrate having a gate wiring, a gate insulating layer, a semiconductor layer, a contact layer, a source and drain wiring, a passivation layer, and a pixel electrode formed on an inner surface of an insulating substrate; a color filter layer on an inner surface of the insulating substrate; A method for manufacturing a liquid crystal display device comprising: a color filter substrate on which a smoothing layer, a common electrode, and an insulating protective layer are formed; and a liquid crystal layer made of a liquid crystal composition interposed between opposing gaps between the active matrix substrate and the color filter substrate. Using dry etching for processing the passivation layer of the active matrix substrate, chromium, titanium, tantalum,
An etching selectivity of the passivation layer to a molybdenum alloy containing at least one of niobium is set to 4
A method of manufacturing a liquid crystal display device as described above.