JP4666008B2 - 記憶装置 - Google Patents
記憶装置 Download PDFInfo
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- JP4666008B2 JP4666008B2 JP2008148726A JP2008148726A JP4666008B2 JP 4666008 B2 JP4666008 B2 JP 4666008B2 JP 2008148726 A JP2008148726 A JP 2008148726A JP 2008148726 A JP2008148726 A JP 2008148726A JP 4666008 B2 JP4666008 B2 JP 4666008B2
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Description
図1は、本発明によるメモリアレイの構成例を示している。同図では、メモリアレイの動作に必要なロウデコーダXDEC、カラムデコーダYDEC、読み出し回路RC、書き込み回路WCも同時に示されている。この構成の特徴は、データ線に平行なソース線を設け、双方を等電位に駆動するプリチャージ回路と、選択ソース線を選択的に駆動する回路を配置することにより、選択されたワード線と選択されたソース線の交点にある選択セルにのみ電流経路を発生する点にある。
なお、プリチャージ回路はQC1、QD1〜QCm、QDm全体と解することができ、QC1とQD1はDL1とSL1の対毎に設けられた要素プリチャージ回路と見ることができる。
記憶素子は、少なくともアンチモン(Sb)とテルル(Te)を含むGe−Sb−Te系、Ag−In−Sb−Te系などのカルコゲナイド材料を記録層の材料として用いている。カルコゲナイド材料を用いた相変化メモリの特性は、例えば、[文献3]で述べられている。この記憶素子に記憶情報‘0’を書き込む場合、図3に示すように、素子をカルコゲナイド材料の融点Ta以上に熱してから急冷するようなリセットパルスを印加する。リセットパルスを短くして与える全エネルギーを小さくし、冷却時間t1を短く、例えば約1nsに設定することにより、カルコゲナイド材料は高抵抗のアモルファス状態となる。逆に、記憶情報‘1’を書き込む場合、記憶素子を融点よりも低く、ガラス転移点と同じかそれよりも高い結晶化温度Txより高い温度領域に保つようなセットパルスを印加することにより、カルコゲナイド材料は低抵抗の多結晶状態となる。結晶化に要する時間t2はカルコゲナイド材料の組成によって異なるが、例えば、約50nsである。同図に示した素子の温度は、記憶素子自身が発するジュール熱、および周囲への熱拡散に依存する。したがって、図4のI−V特性に示すように、書き込み情報に応じた値の電流パルスを記憶素子に印加することにより、記憶素子の結晶状態が制御される。同図は、カルコゲナイド材料を用いた記憶素子の動作原理を模式的に示しており、IW1からIW0の範囲内のセット電流を印加する場合に記憶情報‘1’が書き込まれ、IW0以上のリセット電流を印加する場合に記憶情報‘0’が書き込まれることを示している。ただし、どちらの状態を‘0’、どちらの状態を‘1’としても良い。以下では、同図に従い、四通りの書き込み動作を詳しく説明する。
次に、図5に従い、図1に示したアレイ構成を用いたメモリセルの読み出し動作について説明する。ここで、図5は、メモリセルMC11を選択する場合の動作波形を示している。
さらに、図6に従い、図1に示したアレイ構成を用いたメモリセルの書き込み動作について説明する。但し、図6は、メモリセルMC11を選択する場合の動作波形である。
次に、メモリアレイの構造の例を説明する。この構造の特徴は、ワード線とデータ線及びソース線に対し、MOSトランジスタの活性領域を傾けて配置していることである。ソース線を第一金属層、データ線を第二金属層で配線し、データ線に対応してソース線を設けたメモリセル構造を実現している。
以上で述べたメモリアレイおよびメモリセルの構成と動作による効果を、以下にまとめる。第一に、本実施例によるメモリアレイは、図1に示したようにデータ線DLに平行なソース線SLが設けられ、メモリセル内の選択トランジスタQMのソースが対応するソース線SLに接続された構成とすることにより、読み出し動作における消費電力を低減することができる。具体的には、データ線DLおよびソース線SLに選択トランジスタQA、QBがそれぞれ配置され、さらにプリチャージ用トランジスタQC、QDがそれぞれ配置される。このような構成において、選択したデータ線に対応するソース線をソース電圧VSLに駆動することができる。このため、選択ワードと選択ソース線の交点のセルにのみ電流経路を形成し、選択データ線にのみ読み出し信号を発生することができる。したがって、非選択データ線の充放電を抑制することにより、例えば相変化メモリやMRAMの読み出し動作における消費電力を低減することができる。なお、相変化メモリに本発明を適用した場合、書き込み動作においても読み出し動作と同様の選択動作が行われるので、全体として低電力の相変化メモリを実現することができる。
次に、メモリアレイの構造の別な例を説明する。この構造の特徴は、図1に示したサブアレイ内の選択トランジスタQMとして、縦型構造のMOSトランジスタを用いていることである。
このような構成により、選択する二つのメモリセルの各々に対して、図5と同じような読み出し動作が可能となる。すなわち、プリチャージ電圧VDLに駆動された複数のデータ線DLおよびソース線SLCの中から、選択したい二本のデータ線に対応するソース線を駆動することにより、選択したいデータ線対及びソース線に接続されたメモリセルにのみ、電圧差を印加する。次に、ワード線を選択することにより、所望の二つのメモリセルにのみ電流経路を形成し、選択する二本のデータ線にのみ読み出し信号を発生する。さらに、これらの読み出し信号を、二本の共通データ線I/O1、I/O2を介した二つの読み出し回路RC1、RC2でそれぞれ弁別することにより、2ビットの記憶情報を同時に読み出す。書き込み動作の場合も、選択する二つのメモリセルの各々に対して、図6と同じような書き込み動作が可能となる。すなわち、読み出し動作と同じような選択動作を行い、二つの書き込み回路WC1、WC2を用いて共通データ線I/O1、I/O2に書き込み電流IWC1、IWC2をそれぞれ発生することにより、2ビットの記憶情報を同時に書き込む。
Claims (5)
- 記憶装置であって、
複数のワード線と、
前記複数のワード線に交差する複数のデータ線と、
前記複数のワード線と前記複数のデータ線との交点に配置され、記憶情報に応じて抵抗が変化する記憶素子とMOSトランジスタをそれぞれ含む複数のメモリセルと、
前記複数のワード線に交差し、各々が前記複数のデータ線の一つに対をなすように設けられた複数の制御線と、
前記複数のデータ線と前記複数の制御線を第1電位にプリチャージするためのプリチャージ回路と、
共通データ線と、
前記複数のデータ線の一つを選択して前記共通データ線に接続するための第1スイッチ回路と、
前記複数のデータ線の内選択されたデータ線に対応する前記複数の制御線の一つを選択して第2電位に駆動するための第2スイッチ回路とを備え、
前記MOSトランジスタは、ソースとドレイン間の電流経路が対応する前記複数のデータ線の一つに対して斜めに形成される構造を持ち、
前記複数のワード線のうちの選択されたワード線に接続された前記複数のメモリセルが選択され、
前記メモリセルの前記記憶素子は2つのノードを持つ抵抗素子であり、一方のノードが対応する前記複数のデータ線の一つに接続され、他方のノードが前記MOSトランジスタのドレインに接続され、
前記複数のワード線のうちの選択されたワード線と、前記複数のデータ線のうちの選択されたデータ線と、前記複数の制御線のうちの選択された制御線との交点に存在する前記複数のメモリセルの一つが選択される記憶装置。 - 請求項1において、
前記記憶装置の待機時において、前記プリチャージ回路は、前記複数のデータ線及び前記複数の制御線を前記第1電位にプリチャージし、
前記記憶装置の読み出し時において、前記プリチャージ回路はプリチャージを停止し、
前記第1スイッチ回路は前記複数のデータ線の一つを選択して前記共通データ線に接続するとともに、前記第2スイッチ回路は前記選択されたデータ線と対をなす複数の制御線の一つを選択して前記第2電位に接続することにより、
前記選択されたデータ線と前記選択された制御線との間に電位差を発生する記憶装置。 - 請求項1において、
前記プリチャージ回路は、前記第1電位を供給するための第1電源線と前記複数のデータ線との間に配置された複数の第1トランジスタと、前記第1電源線と前記複数の制御線との間に配置された複数の第2トランジスタを含み、
前記第1スイッチ回路は、前記共通データ線と前記複数のデータ線との間に配置された複数の第3トランジスタを含み、
前記第2スイッチ回路は、前記第2電位を供給するための第2電源線と前記複数の制御線との間に配置された複数の第4トランジスタを含み、
前記記憶装置の待機時において、前記複数の第1トランジスタと前記複数の第2トランジスタが導通することにより、前記複数のデータ線及び前記複数の制御線を前記第1電位にプリチャージし、
前記記憶装置の読み出し時において、前記複数の第1トランジスタと前記複数の第2トランジスタはオフ状態となり、前記複数の第3トランジスタの一つは前記複数のデータ線の一つを選択して前記共通データ線に接続するとともに、前記第4トランジスタは前記選択されたデータ線と対をなす複数の制御線の一つを選択して前記第2電源線に接続することにより、
前記選択されたデータ線と前記選択された制御線との間に電位差を発生する記憶装置。 - 請求項1において、
前記記憶素子の抵抗素子は、ジュール熱を印加することにより結晶状態が変化し、その抵抗値が結晶状態に応じて変化する記憶装置。 - 請求項1において、
前記記憶素子は、カルコゲナイド材料を含む記憶装置。
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US7116593B2 (en) | 2006-10-03 |
US20080062736A1 (en) | 2008-03-13 |
JP4218527B2 (ja) | 2009-02-04 |
US20060280010A1 (en) | 2006-12-14 |
US20040184331A1 (en) | 2004-09-23 |
US20100188877A1 (en) | 2010-07-29 |
WO2003065377A1 (fr) | 2003-08-07 |
JPWO2003065377A1 (ja) | 2005-05-26 |
JP2008283200A (ja) | 2008-11-20 |
US7324372B2 (en) | 2008-01-29 |
US7719870B2 (en) | 2010-05-18 |
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