US7890892B2 - Balanced and bi-directional bit line paths for memory arrays with programmable memory cells - Google Patents

Balanced and bi-directional bit line paths for memory arrays with programmable memory cells Download PDF

Info

Publication number
US7890892B2
US7890892B2 US11/940,542 US94054207A US7890892B2 US 7890892 B2 US7890892 B2 US 7890892B2 US 94054207 A US94054207 A US 94054207A US 7890892 B2 US7890892 B2 US 7890892B2
Authority
US
United States
Prior art keywords
memory
current
design structure
system
memory cells
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related, expires
Application number
US11/940,542
Other versions
US20090129195A1 (en
Inventor
John K. De Brosse
Mark C. H. Lamorey
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to US11/940,542 priority Critical patent/US7890892B2/en
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: DE BROSSE, JOHN K., LAMOREY, MARK C.H.
Publication of US20090129195A1 publication Critical patent/US20090129195A1/en
Application granted granted Critical
Publication of US7890892B2 publication Critical patent/US7890892B2/en
Application status is Expired - Fee Related legal-status Critical
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

Disclosed is a design structure of an improved large scale memory system and, more particularly, an improved memory system that incorporates an array of memory cells that are subjected to minimal location dependent power variations and that, optionally, allows for bi-directional random access of millions of bits. Specifically, the system architecture provides a consistent amount of bit line resistance in the write and read paths to each memory cell in the array, independent of position, in order to minimize variations in power delivery to the cells and, thereby, allow for optimal cell distributions. The system architecture further allows current to pass in either direction through the cells in order to minimize element electro-migration and, thereby, extend memory cell life.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is related to U.S. application Ser. No. 11/539,233 filed Oct. 6, 2007, the complete disclosure of which, in its entirety, is herein incorporated by reference.

BACKGROUND

1. Field of the Invention

The embodiments of the invention generally relate to memory arrays incorporating memory cells with programmable memory elements, and, more particularly, to such a memory array with balanced and, optionally, bi-directional bit line paths.

2. Description of the Related Art

Electrical impulses applied to phase change materials can “tune” or “program” them such that they exhibit a desired resistive property to store data. For example, the material can be programmed to store one binary state (e.g., “0”) at a low resistance state and another binary state (e.g., “1”) at a high resistance state. Additionally, such phase change materials can be programmed to multiple different resistance states (e.g., a high resistance completely amorphous state, multiple mid-resistance semi-amorphous/semi-crystalline states, and a low resistance completely crystalline state) in order to store more than just a single bit (0,1) of information.

The state of a phase change material can be switched through a heating and cooling process which is controlled electrically by passing current through the phase change element and the ohmic heating that occurs. To transform the cell from a high resistance amorphous state to a lower resistance state (i.e., to SET the material), a current pulse is sent through the programmable resistor, heating the phase change material above a predetermined temperature (i.e., above its crystallization temperature) for a given period of time to completely or partially crystallize the material. To transform the cell from a semi-amorphous/semi-crystalline or completely crystalline state to a completely amorphous state (i.e., to RESET the material), a high current pulse is applied to the cell, causing the phase change material to melt. During a subsequent quench cooling, the phase change material is amorphized.

Data that is stored in the programmable resistor can be read without destructing the programmed state of the phase change material. Specifically, a predetermined voltage that is less than the voltage required to achieve the crystallization temperature can be applied to a memory cell and, using a sense amplifier, the magnitude of the readout current through the cell can be detected and analyzed to determine the resistance state of the cell and, thereby, the binary state of the stored data in the cell.

A key to phase change memory technology is determining how to design large scale memory systems which allow random access of millions of bits. This has been accomplished through a system with an array of memory cells, each of which contains a programmable resistor (i.e., a phase change element) that is gated by an access transistor. The current passing through each memory cell and, more particularly, through each programmable resistor, is controlled via a matrix of word lines coupled to each access transistor gate and bit lines coupled to a terminal of each phase change element. Thus, for example, in order to write, set or reset each phase change element, a predetermined voltage is applied to the access transistor gates via the word lines, thereby allowing a current pulse to flow through the bit lines into the phase change elements (See Bedeschi et al., “4 Mb MOSFET-selected phase change memory experimental chip”, ESSCIRC 2004). However, one problem associated with such a memory array configuration is that cell current and, hence, power is initially lower than intended. This lower initial power causes the initial heating rate of the memory cells to lag. Another problem is that the total energy that is deposited into each phase change element varies depending upon the location of the phase change element in the array. This location dependent energy can introduce additional fluctuations and a broader cell distribution. Therefore, there is a need in the art for an improved large scale memory system that allows random access of millions of bits through an array of memory cells, each of which contains a programmable resistor.

SUMMARY

In view of the foregoing, disclosed herein are embodiments of an improved large scale memory system and, more particularly, an improved system that allows optional bi-directional random access of millions of bits and incorporates an array of memory cells that are not subjected to location dependent power variations. Specifically, the system architecture provides a consistent amount of bit line resistance in the write and read paths to each memory cell in a memory array, independent of position, in order to minimize variations in power delivery to the cells. The system architecture can further be configured to allow current to pass in either direction through the cells in order to minimize element electro-migration and, thereby, extend memory cell life.

More particularly, an embodiment of the memory system of the invention comprises a plurality of memory cells controlled via a matrix of bit lines and word lines.

Each memory cell comprises an access transistor coupled to a programmable resistor (e.g., a phase change element for a phase change random access memory). Specifically, the access transistor comprises two source/drain regions (i.e., first and second source/drain regions) and a gate. The programmable resistor comprises two terminals (i.e., first and second terminals). The second source/drain region of the access transistor is coupled to the first terminal of the programmable resistor. The first source/drain region of the access transistor and the second terminal of the programmable resistor are each coupled to different bit lines. Additionally, the gate of each access transistor in each memory cell is coupled to a word line.

The system also comprises a plurality of isolation devices (e.g., isolation transistors) that are coupled to the bit lines and are configured to establish predetermined current pathways through the bit lines and memory cells. These current pathways each comprise a first segment of one bit line coupled to the memory cell and a second segment of another bit line also coupled the memory cell. Each first segment has a corresponding first resistance and each second segment has a corresponding second resistance couple. Depending upon the memory cell location with the array, the first resistance and the second resistance may vary between the current pathways. However, the sum of the first and second resistances in each current pathway is approximately equal. Thus, the total resistance of a given current pathway that runs through a given memory cell is approximately equal to the total resistance of any other current path that runs through any other memory cell in the array, regardless of the location of the memory cell within the system.

The current passing through each memory cell and, more particularly, through each programmable resistor, is controlled via the matrix of word lines that are coupled to each access transistor gate and the different bit line segments that are coupled to the terminals of each programmable resistor. The magnitude of the memory cell heating process can be controlled by either a current source or voltage source. Thus, for example, in order to write to a programmable resistor (i.e., set or reset a phase change element), predetermined voltages are applied to both the access transistor gate and isolation transistor gate via the word line, thereby, allowing a current pulse that is generated at the source to be steered (e.g., by a decode circuit) through the targeted current pathway. Specifically, the current is directed through a pass gate, a segment of one bit line in the current pathway (i.e., a first segment), the phase change element, a segment of a different bit line in the current pathway (i.e., a second segment), the access transistor and the isolation transistor to ground.

In one embodiment of the invention, decode circuits can be coupled at one end of the current pathways and isolation transistors connected to ground can be coupled at the other end. A write driver and a sensing amplifier (i.e., write and read circuits) can be coupled to the decode circuits, thus, allowing write and read current to pass only in a single direction through the current pathways.

In another embodiment of the invention, decode circuits (i.e., first and second decode circuits) as well as isolation transistors connected to ground (i.e., first and second isolation transistor) can be coupled at both ends (i.e., both the first and second ends) of each current pathway. The first decode circuits can be adapted to direct a current in a first direction through the memory cells and the second decode circuits can be adapted to direct the current in a second direction through the memory cells. The first and second decode circuits can each be connected to first and second write drivers as well as first and second sensing amplifiers, respectively. Thus, write currents (i.e., set and reset currents) and read currents can be allowed to flow bi-directionally through the current pathways. A controller connected to the decode circuits (i.e., the first and second decode circuits) can be adapted to periodically switch the currents (i.e., the write and/or read currents) between the first direction and the second direction. For example, the controller can be adapted to switch write current directions after each cycle, after a predetermined number of cycles, after a predetermined period of time or depending upon whether a SET or RESET current is required.

Alternatively, the decode circuits at one end of the current pathways (i.e., first decode circuits) can be coupled to a write driver and the decode circuits at the other end of the current pathways (i.e., the second decode circuits) can be coupled to a sensing amplifier. Thus, write current would be allowed to flow in one direction through the current pathways and read current would be allowed to flow in the opposite direction through the same current pathways.

While the memory system, discussed above, has been described as a phase change random access memory that incorporates phase change elements as the programmable resistors of the memory cells, it is anticipated that the system configuration may be used for other types of random access memory that incorporate other types of programmable resistors in the memory cells. For example, the embodiment that provides for bi-directional write currents to pass through the memory cells may comprise a magnetic random access memory with spins valves or the like as the programmable resistors in each memory cells.

Also disclosed is an embodiment of an associated method of operating a random access memory system. The method comprises providing a memory array, as described above, comprising a plurality of memory cells controlled by a matrix of word lines and bit lines, wherein each memory cell is coupled to a word line and two of bit line. Current pathways are established through the bit lines and memory cells, using isolation transistors, so that the total resistance of each of the current pathways is approximately equal regardless of the location of the memory cell within the memory. A write current (i.e., a set or reset current) is directed through the current pathways and since the resistance in each of the current pathways is approximately equal, the total energy that is deposited in each of the memory cells is also approximately equal, regardless of the location of memory cell within the array.

Depending upon the configuration of the memory system (e.g., depending upon the placement of decode circuits, write drivers and sensing amps and upon the programming of the controller), the current can be directed in different directions (i.e., in a first direction and a second direction) through the current pathways in order to extend a lifetime of the memory cells. For example, the controller can be programmed so that the direction of current flow is switched after each write cycle, after a predetermined number of write cycles, or after a predetermined period of time. Additionally, the controller can be programmed to switch write current directions depending upon the type of write current (i.e., set or reset). Specifically, the maximum attainable power may be different in different directions, due to the amount of gate to source overdrive in the access transistors. Thus, for example, if the maximum obtainable power is greater if current flows in a first direction rather than a second direction through the current pathways, then the controller can be programmed so that reset currents are directed in the first direction and set currents are directed in the second direction because more power is required to reset a phase change material than to set a phase change material.

These and other aspects of the embodiments of the invention will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following descriptions, while indicating preferred embodiments of the invention and numerous specific details thereof, are given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the embodiments of the invention without departing from the spirit thereof, and the embodiments of the invention include all such modifications.

BRIEF DESCRIPTION OF THE DRAWINGS

The embodiments of the invention will be better understood from the following detailed description with reference to the drawings, in which:

FIG. 1 is a schematic diagram illustrating a memory array;

FIG. 2 is a schematic diagram illustrating an exploded view of a portion of the memory array of FIG. 1;

FIG. 3 is a schematic diagram illustrating an embodiment of a memory array of the invention;

FIG. 4 is a schematic diagram illustrating an exploded view of exemplary single memory cell with the memory array of FIG. 3;

FIG. 5 is a schematic diagram illustrating an embodiment of a system of the invention incorporating the memory array of FIG. 3;

FIG. 6 is schematic diagram of an exploded view of a portion of the system of FIG. 5 illustrating single direction current pathways;

FIG. 7 is a schematic diagram illustrating another embodiment of a system of the invention incorporating the memory array of FIG. 3;

FIG. 8 is schematic diagram illustrating another embodiment of a system of the invention incorporating the memory array of FIG. 3;

FIG. 9 is a schematic diagram of an exploded view of a portion of the system of FIG. 7 or 8 illustrating bi-directional current pathways;

FIG. 10 is a flow diagram illustrating an embodiment of the method of the invention; and

FIG. 11 is a flow diagram of a design process used in semiconductor design, manufacturing, and/or test.

DETAILED DESCRIPTION THE EMBODIMENTS OF THE INVENTION

The embodiments of the invention and the various features and advantageous details thereof are explained more fully with reference to the non-limiting embodiments that are illustrated in the accompanying drawings and detailed in the following description. It should be noted that the features illustrated in the drawings are not necessarily drawn to scale. Descriptions of well-known components and processing techniques are omitted so as to not unnecessarily obscure the embodiments of the invention. The examples used herein are intended merely to facilitate an understanding of ways in which the embodiments of the invention may be practiced and to further enable those of skill in the art to practice the embodiments of the invention. Accordingly, the examples should not be construed as limiting the scope of the embodiments of the invention.

As mentioned above, the state of a phase change material can be switched through a heating and cooling process which is controlled electrically by passing current through the phase change element and the ohmic heating that occurs. To transform the cell from a high resistance amorphous state to a lower resistance state (i.e., to SET the material), a current pulse is sent through the programmable resistor, heating the phase change material above a predetermined temperature (i.e., above its crystallization temperature) for a given period of time to completely or partially crystallize the material. To transform the cell from a semi-amorphous/semi-crystalline or completely crystalline state to a completely amorphous state (i.e., to RESET the material), a high current pulse is applied to the cell, causing the phase change material to melt. During a subsequent quench cooling, the phase change material is amorphized.

The following U.S. patents and U.S. patent applications (incorporated herein by reference) discuss phase-change materials and methods for switching the resistances of such materials: U.S. Pat. No. 6,673,691 issued to Zhuang et al. on Jan. 6, 2004; U.S. Pat. No. 6,204,139 issued to Liu et al. on Mar. 20, 2001; and, U.S. Patent Application Pub. No. US 2004/0252544, Lowery et al., Dec. 16, 2004. Also see the following articles: Lai et al., “OUM-a 180 nm non-volatile memory cell element technology for stand alone and embedded applications”, IEDM 2001; Ha et al., “An edge contact type cell for phase change RAM featuring very low power consumption”, VLSI, 2003; and Horii et al., “A novel cell technology using N-doped GeSbTe films for phase change RAM”, VLSI, 2003.

Recently, the availability of such phase change materials as well as progress in lithographic and deposition techniques have provided momentum towards the realization of practical phase change memory (PCM) cells for memory or storage applications, for example, as illustrated in the following patent applications (incorporated herein by reference): U.S. Patent Application Pub. No. US 2004/0036065 A1, Doan et al., Feb. 26, 2004; and U.S. Patent Application Pub. No. US 2003/0219924 A1, Bez et al., Nov. 27, 2003.

A key to phase change memory technology is determining how to design large scale memory systems which allow random access of millions of bits. Referring to FIGS. 1 and 2 in combination, this has been accomplished through a system with an array 50 of memory cells (e.g., see memory cells 1 a-b), each of which contains a programmable resistor 2 (i.e., a phase change element) that is gated by an access transistor 10. The current passing through each memory cell 1 a-b and, more particularly, through each programmable resistor 2 in each cell, is controlled via a matrix of word lines 15 coupled to each access transistor 10 gate and bit lines 5 coupled to a terminal of each phase change element 2. The magnitude of the memory cell heating process can be controlled by either a current source or voltage source. Thus, for example, in order to write (i.e., set or reset) each phase change element 2, a predetermined voltage is applied to the access transistor 10 gate via the word line 15, thereby, allowing a current pulse that is generated at the source to be steered (e.g., by decode circuit 70) through a pass gate, the bit line 5, the phase change element 2 and the access transistor 10 to ground.

One problem associated with a configuration as in memory array 50 is that cell current and, hence, power is initially lower than intended. This lower initial power is the result of parasitic capacitance of each bit line which causes the initial heating rate of the memory cells to lag. Another problem is that the total energy that is deposited into each phase change element varies depending upon the location of the phase change element in the array, due to location-dependent resistance levels in each bit line. This location dependent deposited energy can introduce additional fluctuations and a broader cell distribution. That is, variations in power delivery to cells up and down the bit line may limit array size and margin. Furthermore, a perceived lifetime failure mechanism of phase change elements and other programmable resistors (e.g., spin valves in magnetic random access memories) is elemental migration (i.e., the precipitation in a given direction of one element from the programmable resistor). It is thought that this precipitation is the result of repeated application of a current in a single direction. A mitigation technique to extend the lifetime of the bit is to pass write current in opposing directions on different write cycles. Therefore, there is a need in the art for an improved large scale memory system and, more particularly, an improved system that allows optional bi-directional random access of millions of bits and incorporates an array of memory cells that are subjected to minimal location dependent power variations.

In view of the foregoing, disclosed herein are embodiments of an improved large scale memory system and, more particularly, an improved memory system that incorporates an array of memory cells that are subjected to minimal location dependent power variations and that, optionally, allows for bi-directional random access of memory cells. Specifically, the system architecture provides a consistent amount of bit line resistance (e.g., eliminates up to 99% of variations in bit line resistance) in the write and read paths to each memory cell in the array, independent of position, in order to minimize variations in power delivery to the cells and, thereby, allow for optimal cell distributions. An optimized write control system will deliver a prescribed total power over a given period of time independent of array location and process variations. The system architecture further allows current to pass in either direction through the cells in order to minimize element electro-migration and, thereby, extend memory cell life.

More particularly, FIG. 3 is a schematic diagram illustrating a memory array 100 in and FIG. 4 is a schematic diagram illustrating an individual memory cell 101 within that memory array 100. Referring to FIGS. 3 and 4 in combination, an embodiment of the memory system of the invention comprises a memory array 100 comprising a plurality of memory cells 101 (e.g., see 101 a and 101 b) controlled via a matrix of bit lines 105 and word lines 115. The word lines can be formed, for example, of a polysilicon gate material and the bit lines can be formed, for example, of a metal interconnect material.

Each memory cell 101 comprises an access transistor 110 coupled to a programmable resistor 102. Specifically, the access transistor 110 comprises two source/drain regions (i.e., first and second source/drain regions 151, 152) and a gate 155. The programmable resistor 102 comprises two terminals (i.e., first and second terminals 153, 154). The second source/drain region 152 of the access transistor 110 is coupled to the first terminal 153 of the programmable resistor 102. The first source/drain region 151 of the access transistor 110 and the second terminal 154 of the programmable resistor 102 are each coupled to different bit lines 105. Additionally, the gate 155 of each access transistor 102 in each memory cell 101 is coupled to a word line 115.

FIG. 5 is a schematic diagram illustrating an embodiment of a system of the invention incorporating the memory array 100 of FIG. 3 configured with balanced bit line resistance and also configured to allow current (e.g., read current and write (i.e., set or reset) current) to flow in only a single direction through the memory cells. FIG. 6 is a schematic diagram illustrating an exemplary single direction current pathway in the memory array 100. FIGS. 7 and 8 are schematic drawings illustrating alternative embodiments of the system of the invention incorporating the memory array of FIG. 3 configured with balanced bit line resistance, but also configured to allow current (e.g., read current and write (i.e., set or reset) current) to flow bi-directionally through the memory cells. FIG. 9 is a schematic drawing illustrating an exemplary bi-directional current pathway in the memory array 100.

Referring to both FIGS. 6 and 9, each embodiment of the system of the invention comprises a plurality of isolation devices (e.g., see isolation transistors 120). Each isolation device 120 is coupled between a bit line 105 and ground. These devices 120 can be connected to one end of each bit line 105, as illustrated in FIG. 6, and configured to establish predetermined single direction current pathways through the bit lines 105 and memory cells 101 within the array 100. Alternatively, these devices 120 can be connected at both ends of each bit line 105, as illustrated in FIG. 9, and configured to establish predetermined bi-directional current pathways 180 through the bit lines 105 and memory cells 101 within the array 100.

Each current pathway 180 comprises a first segment 116 of one bit line 105 coupled to the second terminal 154 of a programmable resistor 102 of a given memory cell 101 and a second segment 126 of another bit line 105 coupled to the first source/drain region 151 of the access transistor 110 of the same memory cell 101. Each first segment 116 has a corresponding first resistance 119 (e.g., RBL*(1−X)) and each second segment 126 has a corresponding second resistance 129 (e.g., RBL*X). Depending upon the memory cell location within the array 100, the first resistance 119 and the second resistance 129 may vary between the current pathways 180. However, the sum of the first and second resistances 119, 129 in each current pathway 180 is approximately equal. Thus, the total bit line resistance of a given current pathway, whether single or bi-directional, that runs through a given memory cell and is seen by a driver or sense amplifier is approximately equal to the total resistance of any other current pathway that runs through any other memory cell in the array, regardless of the location of the memory cell within the system (i.e., regardless of the bit accessed is nearest the source or farthest from the source).

The current passing through each memory cell 101 and, more particularly, through each programmable resistor 102, is controlled via the matrix of word lines 115 that are coupled to each access transistor gate 155 and the different bit line segments 116, 126 that are coupled to the first source/drain region 151 of the access transistor and to the second terminal 154 of the programmable resistor 102, respectively. The magnitude of the memory cell heating process can be controlled by either a current source or voltage source. Thus, for example, in order to write (i.e., set or reset a phase change element), predetermined voltages are applied to both the access transistor gate 155 and isolation transistor gate 121 via the word line 115, thereby, creating a current pathway and allowing a current pulse that is generated at the source to be steered (e.g., by a decode circuit 170) through this current pathway 180. Specifically, when the access and isolation transistors are activated by the word line, current is directed through the pathway 180 comprising a pass gate, a segment of one bit line in the current pathway (i.e., a first segment 116), the phase change element 102, a segment of a different bit line in the current pathway (i.e., a second segment 126), the access transistor 110 and the isolation transistor 120 to ground.

As mentioned above, electrical impulses applied to programmable resistors 102 in the memory cells 101 (e.g., phase change elements in phase change memory cells) can “tune” or “program” them such that they exhibit a desired resistive property and, thereby, write data to the cells. For example, programmable resistors 102 can be programmed to store one binary state (e.g., “0”) at a low resistance state and another binary state (e.g., “1”) at a high resistance state. Alternatively, a phase change element that is used as a programmable resistor 102 can be programmed to multiple different resistance states (e.g., a high resistance completely amorphous state, multiple mid-resistance semi-amorphous/semi-crystalline states, and a low resistance completely crystalline state) in order to store more than just a single bit (0,1) of information. The state of the phase change element can be switched through a heating and cooling process which is controlled electrically by passing current through the phase change element and the ohmic heating that occurs. To transform the cell from a high resistance amorphous state to a lower resistance state (i.e., to SET the material), a current pulse is sent through the programmable resistor, heating the phase change material above a predetermined temperature (i.e., above its crystallization temperature) for a given period of time to completely or partially crystallize the material. To transform the cell from a semi-amorphous/semi-crystalline or completely crystalline state to a completely amorphous state (i.e., to RESET the material), a high current pulse is applied to the cell, causing the phase change material to melt. During a subsequent quench cooling, the phase change material is amorphized.

Data that is written to the programmable resistor 102 can be read without destructing the resistance state of the phase change material. Specifically, a predetermined voltage that is less than the voltage required to achieve the crystallization temperature can be applied to a memory cell and the magnitude of the readout current through the cell can be detected and analyzed (e.g., using a sensing amplifier) to determine the resistance state of the cell and, thereby, the binary state of the stored data in the cell.

Referring to FIGS. 5 and 6 in combination, this embodiment of the memory system of the invention can further comprise word line decode circuits 590 coupled to one end of the word lines 115 and bit line decode circuits 170 coupled to one end of the bit lines 105. Specifically, the bit line decode circuits 170 can be coupled to one end of the single direction current pathways 180 opposite the isolation devices 120. The system can further comprise a write driver 550 and a sensing amplifier 560 (i.e., write and read circuits) coupled to the bit line decode circuits 170, thereby, allowing write current (i.e., set and reset current) and read current to pass only in a single direction through the current pathways. The system can further comprise a controller 540 that coupled to the various components of the system (e.g., the write driver, sensing amplifier, bit line decode circuits and word line decode circuit) and adapted to control those components.

Referring to FIGS. 7, 8 and 9 in combination, these embodiments of the memory system of the invention can similarly comprise word line decode circuits 590 coupled to one end of the word lines 115. However, instead of bit line decode circuits 170 coupled only to one end of the bit lines 105, first bit line decode circuits 170 a can be coupled at a first end 901 of the bit lines 105 and second bit line decode circuits 170 b can be coupled at a second end 902 of each of the bit lines 105. Isolation transistors 120 connected to ground (i.e., first and second isolation transistor) can similarly be coupled at both ends 901, 902 of each bit line 105. The first decode circuits 170 at the first end 901 of the bit lines 105 can be adapted to direct a current in a first direction through the memory cells 101 and the second decode circuits 170 at the second end 902 of the bit lines 105 can be adapted to direct the current in a second direction through the memory cells 101.

Specifically, referring to FIG. 7, while it may be ideal to use the same write driver all the time, due to matching, it is possible that a bi-directional write current may help the endurance of the bit and possibly even improve the distributions of the resistances and breakdown voltage. Therefore, the decode circuits 170 a, 170 b at either end of the array 100 can be connected to separate write drivers 550 a-b and separate sensing amplifiers 560 a-b, respectively. That is, the first and second decode circuits 170 a-b can each be connected to first and second write drivers 550 a-b as well as first and second sensing amplifiers 560 a-b, respectively. Thus, write currents (i.e., set and reset currents) and read currents can be allowed to flow bi-directionally through the current pathways 180. As with the previously described embodiment, the system can further comprises a controller 540 adapted to control the functions of the various system components (e.g., the write drivers, sensing amplifiers, bit line decode circuits and word line decode circuits). Specifically, the controller 540 can be connected to the decode circuits 170 a-b (i.e., the first and second decode circuits) and can be adapted to periodically switch the current (i.e., write or read currents) between the first direction and the second direction. For example, the controller 540 can be adapted to switch write current directions (e.g., by toggling a latch) after each write cycle, after a predetermined number of write cycles or after a predetermined period of time. The controller 540 can further be adapted to switch write current directions depending upon whether a set or reset current is required (e.g., by toggling one of two independent latches tracking set and reset, separately).

Alternatively, referring to FIG. 8, the decode circuits at one end 901 of the current pathways (i.e., first decode circuits 170 a) can be coupled to a single write driver 550 and the decode circuits at the other end 902 of the current pathways (i.e., the second decode circuits 170 b) can be coupled to a single sensing amplifier 560. Thus, write current would only be allowed to flow in one direction through the current pathways 180 and read current would only be allowed to flow in the opposite direction through the same current pathways 180.

While the memory system, discussed above, has been described as a phase change random access memory that incorporates phase change elements as the programmable resistors of the memory cells, it is anticipated that the system configuration may be used for other types of random access memory that incorporate other types of programmable resistors in the memory cells. For example, the embodiment that provides for bi-directional write currents to pass through the memory cells may comprise a magnetic random access memory with spins valves or the like as the programmable resistors in each memory cells.

Additional advantages and features of the system embodiments, described above and illustrated in FIGS. 3-9, include the fact that the systems may be implemented with only one level of metal, that oversized devices may be incorporated at one end of the array to compensate for mismatch of power delivery based upon the current direction, and that the minimum obtainable cell size can be improved by suing a wiggled bit line.

Referring to FIG. 10, also disclosed is an embodiment of an associated method of operating a random access memory system. The method comprises providing a memory array, as described above, comprising a plurality of memory cells controlled by a matrix of word lines and bit lines, wherein each memory cell is coupled to a word line and two of bit line (1002). Current pathways are established through the bit lines and memory cells, using isolation transistors, so that the total resistance of each of the current pathways is approximately equal regardless of the location of the memory cell within the memory (1003). A write current (i.e., a set or reset current) is directed through the current pathways (1004) and since the resistance in each of the current pathways is approximately equal, the total energy that is deposited in each of the memory cells is also approximately equal, regardless of the location of memory cell within the array.

Depending upon the configuration of the memory system (e.g., depending upon the placement of decode circuits, write drivers and sensing amps and upon the programming of the controller), the current can be directed in different directions through the current pathways in order to extend a lifetime of the memory cells. That is, the current can be directed in a first direction through the current pathways (1004), as discussed above. Then, the direction of the current can be switched, as indicated by a predetermined current direction switch mode, so that it flows in a second opposite direction through the same current pathways (1005). For example, the controller can be programmed with a specific current direction switch mode so that the direction of current flow is switched after each write cycle (1006), after a predetermined number of write cycles (1007), or after a predetermined period of time (1008). Alternatively, the controller can be programmed to switch write current directions depending upon the type of write current (i.e., set or reset) (1009). Specifically, the maximum attainable power may be different in different directions, due to the amount of gate to source overdrive in the access transistors. Thus, for example, if the maximum obtainable power is greater if current flows in a first direction rather than a second direction through the current pathways, then the controller can be programmed so that reset currents are directed in the first direction and set currents are directed in the second direction because more power is required to reset a phase change material than to set a phase change material.

FIG. 11 shows a block diagram of an example design flow 1100. Design flow 1100 may vary depending on the type of IC being designed. For example, a design flow 1100 for building an application specific IC (ASIC) may differ from a design flow 1100 for designing a standard component. Design structure 1120 is preferably an input to a design process 1110 and may come from an IP provider, a core developer, or other design company or may be generated by the operator of the design flow, or from other sources. Design structure 1120 comprises the circuit in FIGS. 1-9 in the form of schematics or HDL, a hardware-description language (e.g., Verilog, VHDL, C, etc.). Design structure 1120 may be contained on one or more machine readable medium. For example, design structure 1120 may be a text file or a graphical representation of the circuit in FIGS. 1-9. Design process 1110 preferably synthesizes (or translates) the circuit in FIGS. 1-9 into a netlist 1180, where netlist 1180 is, for example, a list of wires, transistors, logic gates, control circuits, I/O, models, etc. that describes the connections to other elements and circuits in an integrated circuit design and recorded on at least one of machine readable medium. This may be an iterative process in which netlist 1180 is resynthesized one or more times depending on design specifications and parameters for the circuit.

Design process 1110 may include using a variety of inputs; for example, inputs from library elements 1130 which may house a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.), design specifications 1140, characterization data 1150, verification data 1160, design rules 1170, and test data files 1185 (which may include test patterns and other testing information). Design process 1110 may further include, for example, standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc. One of ordinary skill in the art of integrated circuit design can appreciate the extent of possible electronic design automation tools and applications used in design process 1110 without deviating from the scope and spirit of the invention. The design structure of the invention is not limited to any specific design flow.

Design process 1110 preferably translates an embodiment of the invention as shown in FIG. 11, along with any additional integrated circuit design or data (if applicable), into a second design structure 1190. Design structure 1190 resides on a storage medium in a data format used for the exchange of layout data of integrated circuits (e.g. information stored in a GDSII (GDS2), GL1, OASIS, or any other suitable format for storing such design structures). Design structure 1190 may comprise information such as, for example, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a semiconductor manufacturer to produce an embodiment of the invention as shown in FIG. 11. Design structure 1190 may then proceed to a stage 1195 where, for example, design structure 1190: proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, etc.

Therefore, disclosed above are embodiments of an improved large scale memory system and, more particularly, an improved memory system that incorporates an array of memory cells that are subjected to minimal location dependent power variations and that, optionally, allows for bi-directional random access of memory cells. Specifically, the system architecture provides a consistent amount of bit line resistance in the write and read paths to each memory cell in the array, independent of position, in order to minimize variations in power delivery to the cells and, thereby, allow for optimal cell distributions. The system architecture further allows current to pass in either direction through the cells in order to minimize element electro-migration and, thereby, extend memory cell life.

The foregoing description of the specific embodiments will so fully reveal the general nature of the invention that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, those skilled in the art will recognize that the embodiments of the invention can be practiced with modification within the spirit and scope of the appended claims.

Claims (15)

1. A system comprising:
a non-transitory computer readable medium storing a design structure for a memory system; and
a machine for manufacturing said memory system, said machine comprising instructions and executing said instructions so as to retrieve said design structure and produce said memory system based on said design structure such that said memory system comprises:
a plurality of memory cells;
a plurality of bit lines, each of said memory cells being coupled between two of said bit lines;
and a plurality of isolation devices coupled to said bit lines and configured to establish a plurality of different current pathways through said bit lines and said memory cells, each of said different current pathways comprising a first segment of a first bit line, a second segment of a second bit line different from said first bit line and a memory cell connected in series between said first segment and said second segment, said first segment having a first resistance and said second segment having a second resistance such that a total resistance of each of said current different current pathways is approximately equal for all memory cell locations within said memory system.
2. The system according to claim 1, said design structure comprising a netlist which describes a circuit.
3. The system according to claim 1, said design structure residing on a non-transient storage medium as a data format used for the exchange of layout data of integrated circuits.
4. The system according to claim 1, said design structure comprising at least one of test data files, characterization data, verification data, and design specifications.
5. A system comprising:
a non-transitory computer readable medium storing a design structure for a memory system; and
a machine for manufacturing said memory system, said machine comprising instructions and executing said instructions so as to retrieve said design structure and produce said memory system based on said design structure such that said memory system comprises:
a plurality of memory cells;
a plurality of bit lines, each of said memory cells being coupled between two of said bit lines;
a plurality of isolation devices coupled to said bit lines and configured to establish a plurality of different bi-directional current pathways through said bit lines and said memory cells, each of said different bi-directional current pathways comprising a first segment of a first bit line, a second segment of a second bit line different from said first bit line and a memory cell connected in series between said first bit line and said second bit line such that a total resistance of each of said current pathways is approximately equal for all memory cell locations within said memory system; and
a first decode circuit connected to a first end of each of said current pathways and a second decode circuit connected to a second end of each of said current pathways, said first decode circuit directing a current in a first direction through said memory cells and said second decode circuit directing said current in a second direction, different than said first direction, through said memory cells.
6. The system according to claim 5, depending upon said memory cell locations within said memory system, first resistances and second resistances of said different bi-directional current pathways will vary.
7. The system according to claim 5, said memory system further comprising a write driver coupled to said first decode circuit and a sensing amplifier coupled to said second decode circuit.
8. The system according to claim 5, said design structure comprising a netlist which describes a circuit.
9. The design structure according to claim 5, said design structure residing on a non-transient storage medium as a data format used for the exchange of layout data of integrated circuits.
10. The design structure according to claim 5, said design structure comprising at least one of test data files, characterization data, verification data, and design specifications.
11. A system comprising:
a non-transitory computer readable medium storing a design structure for a memory system; and
a machine for manufacturing said memory system, said machine comprising instructions and executing said instructions so as to retrieve said design structure and produce said memory system based on said design structure such that said memory system comprises:
a plurality of memory cells;
a plurality of bit lines, each of said memory cells being coupled to two of said bit lines and comprising:
an access transistor comprising:
a first source/drain region coupled to one of said two of said bit lines; and
a second source/drain region; and
a programmable resistor comprising:
a first terminal coupled to said second source/drain region; and
a second terminal coupled to another of said two of said bit lines; and
a plurality of isolation devices coupled to said bit lines and configured to establish current pathways through said bit lines and said memory cells such that a resistance of each of said current pathways is approximately equal for all memory cell locations within said system;
a first decode circuit connected to a first end of each of said current pathways and a second decode circuit connected to a second end of each of said current pathways, wherein said first decode circuit is adapted to direct a write current in a first direction through said memory cells and wherein said second decode circuit is adapted to direct said write current in a second direction through said memory cells; and
a controller connected to said first decode circuit and said second decode circuit and adapted to periodically switch said write current between said first direction and said second direction.
12. The system according to claim 11, said current pathways each comprising a first segment with a first resistance and a second segment with a second resistance and, depending upon said memory cell location, said first resistance and said second resistance varying between said current pathways.
13. The system according to claim 11, said design structure comprising a netlist which describes a circuit.
14. The system according to claim 11, said design structure residing on a non-transient storage medium as a data format used for the exchange of layout data of integrated circuits.
15. The system according to claim 11, said design structure comprising at least one of test data files, characterization data, verification data, and design specifications.
US11/940,542 2007-11-15 2007-11-15 Balanced and bi-directional bit line paths for memory arrays with programmable memory cells Expired - Fee Related US7890892B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/940,542 US7890892B2 (en) 2007-11-15 2007-11-15 Balanced and bi-directional bit line paths for memory arrays with programmable memory cells

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/940,542 US7890892B2 (en) 2007-11-15 2007-11-15 Balanced and bi-directional bit line paths for memory arrays with programmable memory cells

Publications (2)

Publication Number Publication Date
US20090129195A1 US20090129195A1 (en) 2009-05-21
US7890892B2 true US7890892B2 (en) 2011-02-15

Family

ID=40641813

Family Applications (1)

Application Number Title Priority Date Filing Date
US11/940,542 Expired - Fee Related US7890892B2 (en) 2007-11-15 2007-11-15 Balanced and bi-directional bit line paths for memory arrays with programmable memory cells

Country Status (1)

Country Link
US (1) US7890892B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080298121A1 (en) * 2007-06-01 2008-12-04 Jan Otterstedt Method of operating phase-change memory
US20130121056A1 (en) * 2011-11-10 2013-05-16 Micron Technology, Inc. Apparatuses and operation methods associated with resistive memory cell arrays with separate select lines
US20130301335A1 (en) * 2012-05-08 2013-11-14 Adrian E. Ong Architecture, system and method for testing resistive type memory
US9390792B2 (en) 2013-12-23 2016-07-12 Micron Technology, Inc. Apparatuses, memories, and methods for address decoding and selecting an access line

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7882455B2 (en) * 2008-05-09 2011-02-01 International Business Machines Corporation Circuit and method using distributed phase change elements for across-chip temperature profiling
US8331164B2 (en) 2010-12-06 2012-12-11 International Business Machines Corporation Compact low-power asynchronous resistor-based memory read operation and circuit
JP5598338B2 (en) * 2011-01-13 2014-10-01 ソニー株式会社 Storage device and operation method thereof
CN103716038B (en) * 2013-12-25 2016-05-25 华中科技大学 Based on the logic gate nonvolatile phase change memory
US9972385B2 (en) * 2014-11-04 2018-05-15 Hewlett Packard Enterprise Development Lp Memory array driver

Citations (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5937295A (en) 1995-09-29 1999-08-10 International Business Machines Corporation Nano-structure memory device
US6289412B1 (en) * 1998-03-13 2001-09-11 Legend Design Technology, Inc. Layout synopsizing process for efficient layout parasitic extraction and circuit simulation in post-layout verification
US6405160B1 (en) * 1998-08-03 2002-06-11 Motorola, Inc. Memory compiler interface and methodology
US20020131295A1 (en) 2001-01-30 2002-09-19 Naji Peter K. MRAM architecture and system
US6480438B1 (en) 2001-06-12 2002-11-12 Ovonyx, Inc. Providing equal cell programming conditions across a large and high density array of phase-change memory cells
US20030067013A1 (en) 2001-09-27 2003-04-10 Kabushiki Kaisha Toshiba Phase change nonvolatile storage device and drive circuit
US20030206433A1 (en) 2002-05-03 2003-11-06 Glen Hush Dual write cycle programmable conductor memory system and method of operation
US20040184331A1 (en) 2002-02-01 2004-09-23 Satoru Hanzawa Storage device
US6842362B2 (en) 2002-09-25 2005-01-11 Kabushiki Kaisha Toshiba Magnetic random access memory
US20050018493A1 (en) 2002-02-19 2005-01-27 Casper Stephen L. Programmable conductor random access memory and method for sensing same
US6862721B2 (en) * 2001-06-15 2005-03-01 Artisan Components, Inc. Method for identification of faulty or weak functional logic elements under simulated extreme operating conditions
US20050068804A1 (en) 2003-09-25 2005-03-31 Samsung Electronics Co., Ltd. Phase-change memory device and method that maintains the resistance of a phase-change material in a reset state within a constant resistance range
US6885602B2 (en) 2003-08-22 2005-04-26 Samsung Electronics Co., Ltd. Programming method of controlling the amount of write current applied to phase change memory device and write driver circuit therefor
US20050128799A1 (en) 2003-12-05 2005-06-16 Renesas Technology Corp. Semiconductor integrated circuit device
US6943395B2 (en) 2003-06-04 2005-09-13 Samsung Electronics Co., Ltd. Phase random access memory with high density
US6944065B2 (en) 2001-03-30 2005-09-13 Intel Corporation Method, apparatus, and system to enhance negative voltage switching
US6961277B2 (en) 2003-07-08 2005-11-01 Micron Technology, Inc. Method of refreshing a PCRAM memory device
US6967865B2 (en) 2003-04-04 2005-11-22 Samsung Electronics Co., Ltd. Low-current and high-speed phase-change memory devices and methods of driving the same
US20060013038A1 (en) 2004-07-13 2006-01-19 Headway Technologies, Inc. Adaptive algorithm for MRAM manufacturing
US6992369B2 (en) 2003-10-08 2006-01-31 Ovonyx, Inc. Programmable resistance memory element with threshold switching material
US20060023532A1 (en) 2001-11-20 2006-02-02 Glen Hush Method of operating a complementary bit resistance memory sensor
US7398506B2 (en) * 2005-02-24 2008-07-08 Renesas Technology Corp. Net list producing device producing a net list with an interconnection parasitic element by hierarchical processing
US20080310207A1 (en) * 2007-06-13 2008-12-18 Yue Tan 3-d sram array to improve stability and performance

Patent Citations (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5937295A (en) 1995-09-29 1999-08-10 International Business Machines Corporation Nano-structure memory device
US6289412B1 (en) * 1998-03-13 2001-09-11 Legend Design Technology, Inc. Layout synopsizing process for efficient layout parasitic extraction and circuit simulation in post-layout verification
US6405160B1 (en) * 1998-08-03 2002-06-11 Motorola, Inc. Memory compiler interface and methodology
US20020131295A1 (en) 2001-01-30 2002-09-19 Naji Peter K. MRAM architecture and system
US6944065B2 (en) 2001-03-30 2005-09-13 Intel Corporation Method, apparatus, and system to enhance negative voltage switching
US6480438B1 (en) 2001-06-12 2002-11-12 Ovonyx, Inc. Providing equal cell programming conditions across a large and high density array of phase-change memory cells
US6862721B2 (en) * 2001-06-15 2005-03-01 Artisan Components, Inc. Method for identification of faulty or weak functional logic elements under simulated extreme operating conditions
US20030067013A1 (en) 2001-09-27 2003-04-10 Kabushiki Kaisha Toshiba Phase change nonvolatile storage device and drive circuit
US20060023532A1 (en) 2001-11-20 2006-02-02 Glen Hush Method of operating a complementary bit resistance memory sensor
US7242603B2 (en) * 2001-11-20 2007-07-10 Micron Technology, Inc. Method of operating a complementary bit resistance memory sensor
US7116593B2 (en) * 2002-02-01 2006-10-03 Hitachi, Ltd. Storage device
US20040184331A1 (en) 2002-02-01 2004-09-23 Satoru Hanzawa Storage device
US20050018493A1 (en) 2002-02-19 2005-01-27 Casper Stephen L. Programmable conductor random access memory and method for sensing same
US20030206433A1 (en) 2002-05-03 2003-11-06 Glen Hush Dual write cycle programmable conductor memory system and method of operation
US6842362B2 (en) 2002-09-25 2005-01-11 Kabushiki Kaisha Toshiba Magnetic random access memory
US6967865B2 (en) 2003-04-04 2005-11-22 Samsung Electronics Co., Ltd. Low-current and high-speed phase-change memory devices and methods of driving the same
US6943395B2 (en) 2003-06-04 2005-09-13 Samsung Electronics Co., Ltd. Phase random access memory with high density
US6961277B2 (en) 2003-07-08 2005-11-01 Micron Technology, Inc. Method of refreshing a PCRAM memory device
US6885602B2 (en) 2003-08-22 2005-04-26 Samsung Electronics Co., Ltd. Programming method of controlling the amount of write current applied to phase change memory device and write driver circuit therefor
US7242605B2 (en) * 2003-09-25 2007-07-10 Samsung Electronics Co., Ltd. Phase-change memory device and method that maintains the resistance of a phase-change material in a reset state within a constant resistance range
US20050068804A1 (en) 2003-09-25 2005-03-31 Samsung Electronics Co., Ltd. Phase-change memory device and method that maintains the resistance of a phase-change material in a reset state within a constant resistance range
US6992369B2 (en) 2003-10-08 2006-01-31 Ovonyx, Inc. Programmable resistance memory element with threshold switching material
US20050128799A1 (en) 2003-12-05 2005-06-16 Renesas Technology Corp. Semiconductor integrated circuit device
US7123535B2 (en) * 2003-12-05 2006-10-17 Renesas Technology Corp. Semiconductor integrated circuit device
US7085183B2 (en) * 2004-07-13 2006-08-01 Headway Technologies, Inc. Adaptive algorithm for MRAM manufacturing
US20060013038A1 (en) 2004-07-13 2006-01-19 Headway Technologies, Inc. Adaptive algorithm for MRAM manufacturing
US7398506B2 (en) * 2005-02-24 2008-07-08 Renesas Technology Corp. Net list producing device producing a net list with an interconnection parasitic element by hierarchical processing
US20080310207A1 (en) * 2007-06-13 2008-12-18 Yue Tan 3-d sram array to improve stability and performance

Non-Patent Citations (10)

* Cited by examiner, † Cited by third party
Title
Bedeschi et al., "$-Mb MOSFET-Selected Phase-Change Memory Experimental Chip," 2004 IEEE, pp. 207-210. *
DeBrosse et al., 'A High-Speed 128kb MRAM Core for Future Universal Memory Applications, IEEE J. of Solid-State Circuits, vol. 39, No. 4, Apr. 2004, pp. 678-683. *
DeBrosse et al., U.S. Appl. No. 11/539,233, Office Action Communication, Aug. 29, 2008, 8 pages.
Ha et al., "An Edge Contact Type Cell for Phase Change RAM Featuring Very Low Power Consumption," 2003 Symposium on VLSI Technology Digest of Technical Paperrs, pp. 175-176. *
Horii et al., "A Novel Cell Technology Using N-doped GeSbTe Films for Phase Change RAM," 2003 Symposium on VLSI Technology Digest of Technical Papers, pp. 177-178. *
John De Brosse et al., U.S. Appl. No. 11/539,233, Notice of Allowance, pp. 1-3, Oct. 31, 2008.
Lai et al., 'OUM-A 180 nm Nonvolatile Memory Cell Element Technology for Stand Alone and Embedded Applications, 2001 IEEE, pp. 803-806. *
Lai et al., 'OUM—A 180 nm Nonvolatile Memory Cell Element Technology for Stand Alone and Embedded Applications, 2001 IEEE, pp. 803-806. *
Maffitt et al., "Design considerations for MRAM," IBM J. Res. & Dev. vol. 50 No. 1 Jan. 2006, pp. 25-39. *
Wong et al., "Flexible Test Mode Design for DRAM Characterization," 1996 Symposium on VLSI Circuits Digest of Technical Papers, pp. 194-195. *

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080298121A1 (en) * 2007-06-01 2008-12-04 Jan Otterstedt Method of operating phase-change memory
US8125821B2 (en) 2007-06-01 2012-02-28 Infineon Technologies Ag Method of operating phase-change memory
US20130121056A1 (en) * 2011-11-10 2013-05-16 Micron Technology, Inc. Apparatuses and operation methods associated with resistive memory cell arrays with separate select lines
US9548335B2 (en) * 2011-11-10 2017-01-17 Micron Technology, Inc. Apparatuses and operation methods associated with resistive memory cell arrays with separate select lines
US8681529B2 (en) * 2011-11-10 2014-03-25 Micron Technology, Inc. Apparatuses and operation methods associated with resistive memory cell arrays with separate select lines
US20140233300A1 (en) * 2011-11-10 2014-08-21 Micron Technology, Inc. Apparatuses and operation methods associated with resistive memory cell arrays with separate select lines
US9378818B2 (en) * 2011-11-10 2016-06-28 Micron Technology, Inc. Apparatuses and operation methods associated with resistive memory cell arrays with separate select lines
US8711646B2 (en) * 2012-05-08 2014-04-29 Samsung Electronics Co., Ltd. Architecture, system and method for testing resistive type memory
US20130301335A1 (en) * 2012-05-08 2013-11-14 Adrian E. Ong Architecture, system and method for testing resistive type memory
US9390792B2 (en) 2013-12-23 2016-07-12 Micron Technology, Inc. Apparatuses, memories, and methods for address decoding and selecting an access line
US9786366B2 (en) 2013-12-23 2017-10-10 Micron Technology, Inc. Apparatuses, memories, and methods for address decoding and selecting an access line
US10163501B2 (en) 2013-12-23 2018-12-25 Micron Technology, Inc. Apparatuses, memories, and methods for address decoding and selecting an access line

Also Published As

Publication number Publication date
US20090129195A1 (en) 2009-05-21

Similar Documents

Publication Publication Date Title
US7187577B1 (en) Method and system for providing current balanced writing for memory cells and magnetic devices
US8644049B2 (en) Circuit and system of using polysilicon diode as program selector for one-time programmable devices
US8566674B2 (en) Using a phase change memory as a high volume memory
US8913415B2 (en) Circuit and system for using junction diode as program selector for one-time programmable devices
US9761635B1 (en) Selector device for two-terminal memory
US7292466B2 (en) Integrated circuit having a resistive memory
US9478306B2 (en) Circuit and system of using junction diode as program selector for one-time programmable devices with heat sink
US7359231B2 (en) Providing current for phase change memories
US9324447B2 (en) Circuit and system for concurrently programming multiple bits of OTP memory devices
KR100610014B1 (en) Semiconductor memory device capable of compensating for leakage current
CN102804277B (en) Programming reversible resistance-switching element
CN101329910B (en) Phase change memory device
KR20100064715A (en) Nonvolatile memory device using variable resistive element
KR101357175B1 (en) Non-volatile memory cell with non-ohmic selection layer
US8830720B2 (en) Circuit and system of using junction diode as program selector and MOS as read selector for one-time programmable devices
US7215592B2 (en) Memory device with reduced word line resistance
KR101047251B1 (en) Method and system for providing magnetic memory structure using spin transfer
US7880160B2 (en) Memory using tunneling field effect transistors
US20080205179A1 (en) Integrated circuit having a memory array
US7505330B2 (en) Phase-change random access memory employing read before write for resistance stabilization
US8203893B2 (en) Write current compensation using word line boosting circuitry
US9042153B2 (en) Programmable resistive memory unit with multiple cells to improve yield and reliability
US9025357B2 (en) Programmable resistive memory unit with data and reference cells
US6480438B1 (en) Providing equal cell programming conditions across a large and high density array of phase-change memory cells
US6128239A (en) MRAM device including analog sense amplifiers

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DE BROSSE, JOHN K.;LAMOREY, MARK C.H.;REEL/FRAME:020121/0511;SIGNING DATES FROM 20071020 TO 20071022

Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DE BROSSE, JOHN K.;LAMOREY, MARK C.H.;SIGNING DATES FROM 20071020 TO 20071022;REEL/FRAME:020121/0511

SULP Surcharge for late payment
REMI Maintenance fee reminder mailed
FPAY Fee payment

Year of fee payment: 4

LAPS Lapse for failure to pay maintenance fees

Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Expired due to failure to pay maintenance fee

Effective date: 20190215