JP4190906B2 - シリコン半導体基板及びその製造方法 - Google Patents

シリコン半導体基板及びその製造方法 Download PDF

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Publication number
JP4190906B2
JP4190906B2 JP2003030642A JP2003030642A JP4190906B2 JP 4190906 B2 JP4190906 B2 JP 4190906B2 JP 2003030642 A JP2003030642 A JP 2003030642A JP 2003030642 A JP2003030642 A JP 2003030642A JP 4190906 B2 JP4190906 B2 JP 4190906B2
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Prior art keywords
semiconductor substrate
silicon semiconductor
plane
silicon
main surface
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Expired - Fee Related
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JP2003030642A
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English (en)
Japanese (ja)
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JP2004265918A (ja
Inventor
秀記 山中
清史 出水
忠弘 大見
章伸 寺本
成利 須川
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Shin Etsu Handotai Co Ltd
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Shin Etsu Handotai Co Ltd
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Application filed by Shin Etsu Handotai Co Ltd filed Critical Shin Etsu Handotai Co Ltd
Priority to JP2003030642A priority Critical patent/JP4190906B2/ja
Priority to CNB2004800035838A priority patent/CN100380580C/zh
Priority to KR1020057012728A priority patent/KR101030455B1/ko
Priority to US10/543,166 priority patent/US7411274B2/en
Priority to PCT/JP2004/000869 priority patent/WO2004070798A1/ja
Priority to EP04706361A priority patent/EP1592045A4/en
Priority to TW093102420A priority patent/TW200416806A/zh
Publication of JP2004265918A publication Critical patent/JP2004265918A/ja
Publication of JP4190906B2 publication Critical patent/JP4190906B2/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H10D62/405—Orientations of crystalline planes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/12—Preparing bulk and homogeneous wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/12—Preparing bulk and homogeneous wafers
    • H10P90/14—Preparing bulk and homogeneous wafers by setting crystal orientation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2924—Structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2926—Crystal orientations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/36—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done before the formation of the materials

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
JP2003030642A 2003-02-07 2003-02-07 シリコン半導体基板及びその製造方法 Expired - Fee Related JP4190906B2 (ja)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP2003030642A JP4190906B2 (ja) 2003-02-07 2003-02-07 シリコン半導体基板及びその製造方法
PCT/JP2004/000869 WO2004070798A1 (ja) 2003-02-07 2004-01-29 シリコン半導体基板及びその製造方法
KR1020057012728A KR101030455B1 (ko) 2003-02-07 2004-01-29 실리콘 반도체 기판 및 그 제조방법
US10/543,166 US7411274B2 (en) 2003-02-07 2004-01-29 Silicon semiconductor substrate and its manufacturing method
CNB2004800035838A CN100380580C (zh) 2003-02-07 2004-01-29 硅半导体基板及其制造方法
EP04706361A EP1592045A4 (en) 2003-02-07 2004-01-29 SILICON SUBSTRATE SUBSTRATE AND METHOD FOR THE PRODUCTION THEREOF
TW093102420A TW200416806A (en) 2003-02-07 2004-02-03 Silicon semiconductor substrate and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003030642A JP4190906B2 (ja) 2003-02-07 2003-02-07 シリコン半導体基板及びその製造方法

Publications (2)

Publication Number Publication Date
JP2004265918A JP2004265918A (ja) 2004-09-24
JP4190906B2 true JP4190906B2 (ja) 2008-12-03

Family

ID=32844274

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JP2003030642A Expired - Fee Related JP4190906B2 (ja) 2003-02-07 2003-02-07 シリコン半導体基板及びその製造方法

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Country Link
US (1) US7411274B2 (https=)
EP (1) EP1592045A4 (https=)
JP (1) JP4190906B2 (https=)
KR (1) KR101030455B1 (https=)
CN (1) CN100380580C (https=)
TW (1) TW200416806A (https=)
WO (1) WO2004070798A1 (https=)

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JP2007070131A (ja) * 2005-09-05 2007-03-22 Sumco Corp エピタキシャルウェーハの製造方法およびエピタキシャルウェーハ
JP2008060355A (ja) * 2006-08-31 2008-03-13 Sumco Corp 貼り合わせウェーハの製造方法および貼り合わせウェーハ
JP5023900B2 (ja) 2006-09-05 2012-09-12 株式会社Ｓｕｍｃｏ エピタキシャルシリコンウェーハ
JP2008177530A (ja) * 2006-12-21 2008-07-31 Covalent Materials Corp 半導体基板およびその製造方法
JP2008177529A (ja) * 2006-12-21 2008-07-31 Covalent Materials Corp 半導体基板およびその製造方法
US20080164572A1 (en) * 2006-12-21 2008-07-10 Covalent Materials Corporation Semiconductor substrate and manufacturing method thereof
JP2009094156A (ja) * 2007-10-04 2009-04-30 Tohoku Univ 半導体基板および半導体装置
US8623137B1 (en) 2008-05-07 2014-01-07 Silicon Genesis Corporation Method and device for slicing a shaped silicon ingot using layer transfer
DE102008026784A1 (de) 2008-06-04 2009-12-10 Siltronic Ag Epitaxierte Siliciumscheibe mit <110>-Kristallorientierung und Verfahren zu ihrer Herstellung
US8815710B2 (en) 2008-06-10 2014-08-26 Sumco Corporation Silicon epitaxial wafer and method for production thereof
JP2010018504A (ja) * 2008-07-14 2010-01-28 Japan Atomic Energy Agency Ｓｉ（１１０）表面の一次元ナノ構造及びその製造方法
JP5593107B2 (ja) 2009-04-02 2014-09-17 株式会社半導体エネルギー研究所 半導体装置の作製方法
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JP5375768B2 (ja) * 2010-08-17 2013-12-25 信越半導体株式会社 シリコンエピタキシャルウェーハの製造方法
US9064808B2 (en) 2011-07-25 2015-06-23 Synopsys, Inc. Integrated circuit devices having features with reduced edge curvature and methods for manufacturing the same
US8609550B2 (en) 2011-09-08 2013-12-17 Synopsys, Inc. Methods for manufacturing integrated circuit devices having features with reduced edge curvature
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JP2013254982A (ja) * 2013-08-21 2013-12-19 Tohoku Univ 半導体基板および半導体装置
JP6973475B2 (ja) * 2017-04-06 2021-12-01 株式会社Sumco エピタキシャルシリコンウェーハの製造方法およびエピタキシャルシリコンウェーハ
US11139402B2 (en) 2018-05-14 2021-10-05 Synopsys, Inc. Crystal orientation engineering to achieve consistent nanowire shapes
KR102662765B1 (ko) * 2018-08-02 2024-05-02 삼성전자주식회사 기판과 이를 포함하는 집적회로 소자 및 그 제조 방법
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KR102523367B1 (ko) * 2020-02-13 2023-04-21 세메스 주식회사 실리콘 구조물 표면 러프니스 개선 방법 및 기판 처리 장치
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Also Published As

Publication number Publication date
KR20050098860A (ko) 2005-10-12
EP1592045A1 (en) 2005-11-02
TW200416806A (en) 2004-09-01
EP1592045A4 (en) 2010-09-08
CN100380580C (zh) 2008-04-09
CN1748287A (zh) 2006-03-15
TWI326103B (https=) 2010-06-11
US20060131553A1 (en) 2006-06-22
JP2004265918A (ja) 2004-09-24
WO2004070798A1 (ja) 2004-08-19
US7411274B2 (en) 2008-08-12
KR101030455B1 (ko) 2011-04-25

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