Classifications

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  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/01—Manufacture or treatment
  • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
  • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
  • H10D64/01332—Making the insulator
  • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
• • H—ELECTRICITY
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/40—Crystalline structures
  • H10D62/405—Orientations of crystalline planes
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  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
  • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
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  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
  • H10P90/12—Preparing bulk and homogeneous wafers
• • H—ELECTRICITY
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  • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
  • H10P90/12—Preparing bulk and homogeneous wafers
  • H10P90/14—Preparing bulk and homogeneous wafers by setting crystal orientation
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  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
  • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
  • H10P14/2901—Materials
  • H10P14/2902—Materials being Group IVA materials
  • H10P14/2905—Silicon, silicon germanium or germanium
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  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
  • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
  • H10P14/2924—Structures
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  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
  • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
  • H10P14/2926—Crystal orientations
• • H—ELECTRICITY
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  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
  • H10P14/34—Deposited materials, e.g. layers
  • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
  • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
  • H10P14/3411—Silicon, silicon germanium or germanium
• • H—ELECTRICITY
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  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
  • H10P14/36—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done before the formation of the materials

Definitions

• the present invention relates to a single crystal silicon semiconductor substrate used for manufacturing a semiconductor integrated circuit device and a method for manufacturing the same.
• the gate insulating film of MIS ⁇ FET Metal-Insulator-Semiconductor Field Effect Transistor manufactured using single crystal silicon wafer has low leakage current characteristics and low interface state density. High-performance electrical characteristics such as high resistance to ion implantation and high reliability are required.
• a technique for forming a gate insulating film that satisfies these requirements a technique for forming a silicon dioxide film (sometimes simply referred to as an oxide film) by a thermal oxidation method is mainstream. This is so-called MOS • FET (Meta1—Oxide—SemiconduncctorFieldEffefetTransistor).
• the interface state density of the oxide films formed on the ⁇ 110 ⁇ plane and the ⁇ 111 ⁇ plane is high. If the interface state density is high, the electrical characteristics of the oxide film, such as the withstand voltage characteristics and the leakage current characteristics, are poor.
• the silicon wafer substrate on which the MOS FET is formed Until now, the ⁇ 100 ⁇ direction has been used, or the Ahachi tilted about 4 ° from ⁇ 100 ⁇ has been used.
• the semiconductor device on the ⁇ 100 ⁇ plane has a current driving capability of p-type FET, that is, a carrier mobility of about 0.3 times that of n-type FET.
• a method of forming a high-quality insulating film that does not depend on the plane orientation of the silicon wafer surface that is, a radical oxidation method or a radical nitridation method has been developed.
• VL SIT echnology Honolulu, Hawaii, June 1 3—15, 2 0 0 0 "A dvancedof R phenomenon 1 O xidation for Imroving R e 1 iabi 1 ityof U ltra— Thin Gate O xide" .
• a high-quality insulating film can be formed on a surface other than ⁇ 100 ⁇ .
• the present inventors fabricated a semiconductor device having a ⁇ 110 ⁇ plane as a main surface, evaluated its characteristics, and obtained various findings.
• the current drive capability of the p-type FET is about 2.5 times higher than that of ⁇ 100 ⁇ , but the current drive capacity of the n-type FET is expected to decrease by about 0.6 times. The result was contrary. If the electron mobility of this n-type FET is equal to or higher than the electron mobility of the ⁇ 100 ⁇ plane, semiconductor integrated circuit devices using the ⁇ 110 ⁇ plane have been put into practical use and widely used. Will be done.
• Carrier mobility is affected by impurity scattering, phonon scattering (lattice vibration scattering), and surface roughness scattering. If the effects of these scatterings are large Carrier mobility decreases.
• the electron mobility of the ⁇ 100 ⁇ plane is greatly affected by the roughness of the silicon surface, and it has been shown that the lower the roughness, the lower the electron mobility (T. Ohmieta 1 .: IEEE Trans. E lectron D evices, vol. 13 7, p. 53 7, 1992).
• the following two methods have been proposed to reduce the surface roughness. That is, (1) formation of an oxide film on the surface of a semiconductor substrate in an atmosphere containing oxygen radicals (M. Nag amineeta 1., IEDM Tec h. Digp593, 19998) , And (2) This is a method of cleaning the substrate surface other than the RCA cleaning (W. Kerneta 1 .: RCAR eview, vol. 31, .187, 197 0).
• radical oxygen which is an oxidizing species, has a high probability of adhering to the protrusions on the silicon surface, and o + and o 2 + oxygen ions are attracted to the negatively charged protrusions It is thought that the surface roughness is reduced by synergistic effects and preferential oxidation of the protrusions.
• Conventional oxidation in dry oxygen (dry oxygen) atmosphere causes surface roughness to deteriorate by about 20%, whereas radical oxidation reduces surface roughness by about 40%.
• the cleaning method of (2) has already been disclosed as Japanese Patent Application Laid-Open No. H11-076366.
• the cleaning process disclosed in Japanese Patent Application Laid-Open No. 11-057636 discloses the use of an alkaline solution because the cleaning process using an alkaline solution for RCA cleaning, which has been widely used, deteriorates the surface roughness. It has a cleaning process that does not include it, and has the ability to remove particles, remove organic contaminants, and remove metal impurities equivalent to or better than RCA cleaning. Since this new cleaning step is composed of five steps, it will be abbreviated as a five-step cleaning in the present specification.
• the reason that the surface roughness deteriorates in the cleaning process including the RCA cleaning solution is that the weak Si-Si bond is preferentially etched by hydroxide ions (OH ions). is there.
• the radical oxidation method (1) is a method for reducing surface roughness
• the cleaning method (5) in (2) is a method for reducing surface roughness. Rather, it is a method to reduce the amount of RCA cleaning. In fact, the five-step cleaning can reduce the deterioration of about 50% by the conventional RCA cleaning from 0% to 10%.
• the surface roughness is reduced by the radical oxidation method, it is possible to further reduce the surface roughness by repeating this radical oxidation before forming the gate oxide film. is there. Radical oxidation is performed at a low temperature of about 300 ° C. (up to about 500 ° C.). At this temperature, oxygen donors are formed, and the electrical resistivity inside the substrate changes. When oxidizing at C or higher, the formation and growth of oxygen precipitation nuclei also occur on the surface of the substrate, which causes leakage current ⁇ dielectric breakdown of the gate oxide film.
• Reducing the surface roughness of a silicon semiconductor substrate is to flatten the surface at the atomic level.
• the surface of a mirror-polished and cleaned silicon wafer having a specific crystal plane has countless irregularities, which is the cause of the surface roughness called micro-roughness. This is formed by the fact that a large number of microfacets different from the cut surface appear on the surface due to the chemical reaction between the chemical used for polishing and cleaning and the silicon surface.
• the ⁇ 111 ⁇ plane itself is a facet plane, so a flat surface at the atomic level is likely to be formed.
• Y.J.Chaba 1 and others are washed with an aqueous solution of ammonium fluoride to terminate and stabilize dangling pounds (bonds with no covalent bond partner) on the surface silicon atoms with hydrogen atoms.
• the ⁇ 111 ⁇ plane is slightly inclined several degrees in the [111] or [ ⁇ [2] direction, and is washed with an aqueous solution of ammonium fluoride to form steps and terraces at the atomic level to form atomic and atomic steps. It has also been clarified that the surface can be flattened (H. Sakaueetal., Appl. Phys. Lett. Vol. 78, p. 309, 2001). However, in the most widely used ⁇ 100 ⁇ plane silicon substrate, there is no report that flattening at the atomic level was achieved only by cleaning a mirror-polished substrate.
• the polished and cleaned silicon semiconductor substrate is referred to as a mirror-polished silicon semiconductor substrate.
• the term “silicon semiconductor substrate” is used to refer to the generic term including epitaxy silicon semiconductor substrates.
• the surface roughness of the mirror-polished silicon semiconductor substrate is about 0.12 nm when expressed in terms of root-mean-square average roughness (Root-mean-squarreoughnesss; Rms).
• Rms root-mean-square average roughness
• the typical Rms of a silicon semiconductor substrate after RCA cleaning in a device maker is about 0.18 nm.
• an oxide film of about 5 nm is formed in a conventional dry oxygen (dry oxygen) atmosphere to form a gate oxide film on this substrate, the Rms at the interface deteriorates to 0.22 nm.
• the Rms is about 0.08 nm, and the surface roughness can be significantly reduced.
• Introducing this radical sacrificial oxidation process to a silicon semiconductor substrate maker is one method of reducing surface roughness, but as described above, the number of processes is increased and productivity is reduced. Therefore, from the standpoint of manufacturing silicon semiconductor substrates used in the manufacture of semiconductor integrated circuit devices, silicon semiconductor substrates with reduced surface roughness without sacrificial oxidation such as radical oxidation or special cleaning are required. Need to be manufactured. Disclosure of the invention
• An object of the present invention is to produce a silicon semiconductor substrate for a semiconductor integrated circuit device in which the carrier mobility of the ⁇ 110 ⁇ plane, particularly the mobility of electrons which is the carrier of the n-type FET, shows a higher value.
• Conventional RCA cleaning without special cleaning such as the five-step cleaning described above is used, and the surface is flattened at the atomic level without radical oxidation, reducing surface roughness. It is an object of the present invention to provide a silicon semiconductor substrate and a method for manufacturing the same.
• a first aspect of the silicon semiconductor substrate of the present invention is a silicon semiconductor substrate having a ⁇ 110 ⁇ plane or a plane inclined to a ⁇ 110 ⁇ plane as a main surface.
• the surface is characterized by having on the surface an atomic level step along the ⁇ 110> direction on average. It is preferable that the ⁇ 1 1 0 ⁇ plane is inclined in the ⁇ 1 0 0> direction as the inclined plane of the ⁇ 1 1 0 ⁇ plane.
• the biggest feature of using a silicon semiconductor substrate whose principal surface is the ⁇ 110 ⁇ plane or the plane inclined to the ⁇ 110 ⁇ plane for the semiconductor integrated circuit element is that the hole mobility in the p-type FET is high. This is about 2.5 times higher in the ⁇ 110> direction than in the ⁇ 100 ⁇ plane. Therefore, in a semiconductor integrated circuit device in which the n-type FET electron mobility of these silicon semiconductor substrates is improved to be higher than the electron mobility of the ⁇ 100 ⁇ plane, the channel direction in which electrons and holes flow is less than the 110> direction. Fabrication in this manner can further miniaturize circuit elements.
• the surface roughness does not become lower than the surface roughness of the ⁇ 100 ⁇ plane.
• the electron mobility is smaller than the electron mobility of the ⁇ 100 ⁇ plane.
• Atomic level surface flattening is required to reduce surface roughness It is.
• a terrace is formed between the steps, and the terrace surface becomes an atomically flat surface. If the edge of the step is set in the ⁇ 110> direction, the carriers flowing in the ⁇ 110> direction will flow just below the flat terrace surface or will not be scattered by the step difference. Thus, the influence of scattering due to surface roughness is reduced, and high mobility can be realized.
• the edge of the step is not a straight line at the atomic level but has irregularities of several atoms, and that part is called a kink part. Therefore, a step along the ⁇ 110> direction means a step along the ⁇ 110> direction on average in micrometer order.
• a silicon single crystal thin film is formed on a surface of a silicon semiconductor substrate having a principal surface with a ⁇ 110 ⁇ plane inclined in a ⁇ 100> direction by an epitaxial growth method.
• the silicon semiconductor substrate having a silicon single crystal thin film formed on its surface by the epitaxial growth method is, in other words, an epitaxial silicon semiconductor substrate.
• this will be referred to as the epitaxial silicon of the present invention. It may be called a semiconductor substrate.
• the epitaxial growth of silicon semiconductor substrates is described by a model in which the steps grow two-dimensionally while silicon atoms are deposited on the kinks of the steps formed on the terrace.
• Terraces and steps are not formed on the surface of the ⁇ 110 ⁇ mirror-polished silicon semiconductor substrate that has not been slightly tilted and has been polished and cleaned, and terraces and steps are not formed by ordinary RCA cleaning. Crofacet is present. This is the cause of the surface roughness deterioration.
• countless microfacets play the role of a kink, and the deposition of silicon atoms occurs uniformly. Therefore, steps and terraces oriented in the ⁇ 110> direction are not formed.
• the terrace and the step are observed despite the fact that the principal surface of the mirror-polished silicon semiconductor substrate before the epitaxial growth is a slightly inclined surface is slightly inclined.
• the principal surface of the mirror-polished silicon semiconductor substrate before the epitaxial growth is a slightly inclined surface is slightly inclined.
• terraces and steps are formed during the growth process.
• the flatness of the terrace surface at the atomic level improves surface roughness.
• a vicinal mirror-polished silicon semiconductor substrate potentially includes factors that cause terraces and steps to form.
• the silicon semiconductor substrate having the principal surface with the ⁇ 110 ⁇ plane inclined in the ⁇ 100> direction may be replaced with hydrogen gas, argon gas, or a mixture thereof.
• This silicon semiconductor substrate may be referred to as a heat-treated silicon semiconductor substrate hereinafter.
• the silicon atoms on the surface are rearranged by the high-temperature treatment. Steps and terraces are formed on the surface.
• a second aspect of the silicon semiconductor substrate of the present invention is a silicon semiconductor substrate having, as a main surface, a surface inclined in the ⁇ 100> direction passing through the ⁇ 110 ⁇ plane.
• the surface is mirror-polished (hereinafter, this silicon semiconductor substrate is sometimes referred to as a mirror-polished silicon semiconductor substrate).
• this silicon semiconductor substrate is sometimes referred to as a mirror-polished silicon semiconductor substrate.
• no steps and terraces are formed on a silicon substrate that has been slightly polished in the ⁇ 100> direction passing through the ⁇ 111 ⁇ plane and has been polished and cleaned, but is epitaxially grown on that substrate.
• Steps and terraces can be formed by performing heat treatment in an atmosphere of hydrogen gas or argon gas. Therefore, the factors for forming steps and terraces are inherent in the surface of a silicon substrate.
• Steps and terraces can be formed in a cleaning step and a heat treatment step in an initial step for forming a semiconductor integrated circuit element.
• the fine tilt angle in the silicon semiconductor substrate of the present invention is not less than 0 ° and less than 8 °.
• the ⁇ 1 1 0 ⁇ plane inclined by 8 ° in the ⁇ 100> direction becomes another low-index plane ⁇ 5 5 1 ⁇ , and ⁇ 5 5 1 ⁇ to form steps and terraces on this surface.
• ⁇ The surface needs to be slightly inclined. Therefore, less than 8 ° is preferable. As the angle of slight inclination increases, the terrace width decreases and the step density increases.
• the step of the monoatomic layer step on the ⁇ 110 ⁇ plane is 0.192 nm
• the calculated terrace width at 8 ° is 1.36 nm
• the step of the two atom step is Since it is 0.394 nm
• the terrace width is 2.73 nm
• the terrace width and the step difference are the same.
• the higher the density of the step the higher the kink density, the more difficult it is for the two-dimensional epitaxy to grow by the step, and the step and terrace oriented in a specific direction will not be formed.
• the inclusion of 0 ° is due to equipment accuracy issues.
• the orientation flat It is preferable that the notch or the notch be formed in the ⁇ 110> direction.
• the inclination direction is the same as the front and back of the wafer cut from the crystal ingot, and there is no need to manage the front and back of the wafer. Sex can be excluded.
• a first aspect of the method for manufacturing a silicon semiconductor substrate of the present invention is to produce a silicon semiconductor substrate having a principal plane with a ⁇ 110 ⁇ plane inclined in a ⁇ 100> direction, and to form an epitaxy on the surface.
• the method is characterized in that the silicon semiconductor substrate according to the first aspect of the present invention is manufactured by growing a silicon single crystal thin film by a growth method.
• a silicon semiconductor substrate having a principal surface with a ⁇ 110 ⁇ plane inclined in a ⁇ 100> direction is produced, and The heat treatment is performed in an atmosphere of hydrogen gas, argon gas, or a mixed gas thereof to produce the above-described silicon semiconductor substrate of the first aspect of the present invention.
• FIG. 1 is an AFM image showing the states of steps and terraces formed on the surface of the epitaxial silicon semiconductor substrate in Example 1 when the inclination angle is 0.1 °.
• FIG. 2 is a schematic diagram of FIG.
• FIG. 3 shows the epitaxial silicon semiconductor substrate in Example 1 with a slight tilt angle of 7.9.
• 3 is an AFM image showing the state of steps and terraces formed on the surface in the case of.
• FIG. 4 is a schematic diagram of FIG.
• FIG. 5 shows a hydrogen-heat-treated silicon semiconductor substrate according to the present invention with a slight tilt angle of 0.1.
• AFM image showing the state of steps and terraces formed on the surface in case of is there.
• FIG. 6 is a schematic diagram of FIG.
• FIG. 7 is an explanatory diagram showing that the front and back sides are equivalent by attaching an orientation flat in the ⁇ 110> direction on the silicon semiconductor substrate of the present invention.
• FIG. 8 is an explanatory diagram showing that when an orientation flat is applied in the ⁇ 100> direction on a silicon semiconductor substrate, the front and back are not equivalent but front and back management is required.
• FIG. 9 is a graph showing the dependence of the surface roughness (Rms) of the epitaxial silicon semiconductor substrate and the mirror-polished silicon semiconductor substrate of the present invention on the fine inclination angle in the first embodiment.
• FIG. 10 is a graph showing the dependence of the surface roughness (Rms) of the hydrogen-heat-treated silicon semiconductor substrate and the mirror-polished silicon semiconductor substrate on the slight inclination angle in Example 2.
• FIG. 1 shows an AFM (A tomic Force Microscope) image of the epitaxial silicon semiconductor substrate W of the present invention tilted by 0.1 ° in the ⁇ 110 ⁇ plane in the ⁇ 110> direction
• FIG. 2 is a schematic diagram
• FIG. 3 shows an AFM image of the epitaxial silicon semiconductor substrate W of the present invention inclined at 7.9 ° in the ⁇ 110 ⁇ plane in the ⁇ 110> direction
• FIG. 4 is a schematic diagram thereof.
• Figure 5 shows that the ⁇ 1 1 0 ⁇ plane is tilted by 0.1 ° in the ⁇ 1 1 0> direction.
• 3 shows an AFM image of the hydrogen-heat-treated silicon semiconductor substrate W
• FIG. 6 is a schematic diagram thereof.
• the silicon semiconductor substrate W of the present invention has a ⁇ 110 ⁇ plane or a plane inclined at the ⁇ 110 ⁇ plane as a main surface, and has a step S at an atomic level along the ⁇ 110> direction on the surface.
• the example shown in Fig. 1 to Fig. 6 is a case where the principal plane is the plane tilted from the ⁇ 110 ⁇ plane).
• step S In order to reduce the surface roughness of the silicon semiconductor substrate W, it is necessary to planarize the surface at the atomic level.
• steps S By forming steps S on the surface of the silicon semiconductor substrate W, terraces T are formed between the steps S, and the terraces T are flat at the atomic level. If the edge of step S is set in the 1 110> direction, the carrier flowing in the 1 110> direction will flow just below the flat terrace T surface or will be scattered by the step in step S. By flowing without any influence, the effect of scattering due to surface roughness is reduced, and high mobility can be realized.
• the edge of Step S is not a straight line at the atomic level, but has irregularities of several atoms, and that part is called a kink. Therefore, the step S along the ⁇ 110> direction means the step S along the ⁇ 110> direction on average in the micrometer order.
• the epitaxial silicon semiconductor substrate according to the present invention has a feature of forming steps along the ⁇ 110> direction.
• a silicon single crystal thin film formed by epitaxial growth on the surface of a mirror-polished silicon semiconductor substrate whose principal surface is the surface inclined at the ⁇ 100> direction. is there.
• FIG. 7 is an explanatory diagram showing that the front and back sides are equivalent by attaching an orientation flat in the ⁇ 100> direction in the silicon semiconductor substrate of the present invention.
• the (111) plane of the silicon semiconductor substrate W is represented as the (110) plane, and the orientation flat in the [110] direction.
• Figure 8 shows an orientation flat OF of a silicon semiconductor substrate W formed in the [001] direction.
• the [110] axis (arrow OA) perpendicular to the (110) plane is tilted in the [001] direction as in Fig. 7, the new axis becomes the arrow OA 'in the figure. To That. As a result the main surface is a new The plane is perpendicular to the axis OA '.
• the inclination direction becomes the arrow OA "shown on the bottom side of the wafer, and the inclination direction is 180 ° with respect to the orientation flat F.
• the tilt direction is oriented in the direction of the orientation flat ([0 0 1]) in one eave, while the orientation is oriented in the direction of the orientation flat ([0 0 0 1]) Therefore, in the device fabrication process in which the silicon semiconductor substrate is aligned in various directions with reference to the orientation flat to perform various processes to fabricate a semiconductor element, the inclination direction is 1 Since wafers differing by 80 degrees are mixed, it becomes impossible to manufacture devices having the same characteristics.
• a first aspect of the method for manufacturing a silicon semiconductor substrate of the present invention is to produce a silicon semiconductor substrate having a principal plane with a ⁇ 110 ⁇ plane inclined in a ⁇ 100> direction, and to form an epitaxy on the surface.
• the silicon semiconductor substrate of the present invention is manufactured by growing a silicon single crystal thin film by a growth method.
• a silicon semiconductor substrate having a principal surface with a ⁇ 110 ⁇ plane inclined in a ⁇ 100> direction is produced, and
• the silicon semiconductor substrate of the present invention is manufactured by performing heat treatment in an atmosphere of hydrogen gas, argon gas, or a mixed gas of these gases.
• the silicon single crystal pulled in the [110] direction is moved in the [001] direction.
• the wafer was cut at an angle of 10.0 ° to produce a wafer.
• the crystal is a P-type doped with boron and has an electrical resistivity of 10 to 12 ⁇ cm.
• the diameter is 150 mm.
• the cut wafer was mirror-finished by ordinary chemical mechanical polishing, and then subjected to RCA cleaning.
• a silicon single crystal thin film having a thickness of about 5 im was formed on these mirror-polished silicon semiconductor substrates by epitaxy. Growth was performed at a reaction temperature of 110 ° C. in a hydrogen atmosphere using trichlorosilane (SiHC 13) as a source gas.
• SiHC 13 trichlorosilane
• the surface roughness can be measured using the AFM (Atomic Force Microscope) function, which can measure minute irregularities on the surface using the SEI KO INS TRUMENT S SPA360.
• the quantity is represented by Rms.
• Figure 9 shows the dependence of Rms on the inclination angle of the epitaxial silicon semiconductor substrate. For comparison, a mirror-polished silicon semiconductor substrate having each inclination angle is also shown. When the slight inclination angle is 0 °, the Rms of the mirror-polished silicon semiconductor substrate and the Rms of the epitaxial silicon semiconductor substrate are 0.118 nm and 0.112 nm, respectively.
• Rms 0.118 nm of the mirror-polished ⁇ 1 110 ⁇ plane mirrorless silicon semiconductor substrate is almost the same value as Rms of the mirror-polished ⁇ 100 ⁇ plane semiconductor substrate without slope. is there. Even at a slight inclination angle of 0.1 °, the surface roughness of the epitaxial silicon semiconductor substrate is smaller than that of the mirror-polished silicon semiconductor substrate. The reduction effect is at least 7.9. Up to the angle of inclination.
• the step at the monoatomic layer step on the ⁇ 1 1 0 ⁇ plane is 0.192 nm
• the calculated terrace width at 7.9 ° is 1.38 nm
• the terrace width is 2.76 nm
• the terrace width and the step difference are in the same order.
• the step interval becomes narrower and the density increases, the kink density also increases and the Two-dimensional epitaxy growth with At 10.0 °, the surface roughness deteriorates.
• Figure 1 shows an AFM image of the surface roughness of an epitaxial silicon semiconductor substrate with a slight tilt angle of 0.1 °
• Figure 2 shows a schematic diagram of the AFM image.
• step S and terrace T can be recognized.
• Step S is formed in the ⁇ 110> direction on average.
• the width of the terrace T is about 100 nm.
• the step of a single atom step is 0.192 nm, and the step of a two atom step is 0.384 nm.
• the terrace width is 110 nm for a single atom step. It almost matches the prediction.
• the estimated terrace width by a single atom step is less than 10 nm.
• step S is formed which is considerably wider than the expected terrace width of 1.38 nm or 2.76 nm.
• the direction of step S is generally ⁇ 110>, but it is curved, which means that the growth of step S is fluctuating.
• the rather wide terrace T was formed is that when the ⁇ 110 ⁇ plane is tilted by 7.9 ° in the ⁇ 100> direction, the principal plane is the ⁇ 55 ⁇ plane, which is a low-index plane. Is inclined by 0.15 °, so that its main surface is slightly inclined from the facet plane ⁇ 5551 ⁇ . And there. This is inferred from the fact that the steps and terraces are formed when the facet plane ⁇ 1 1 1 ⁇ plane is slightly inclined in the 1 1 2> direction.
• the surface roughness of the heat-treated silicon semiconductor substrate will be described.
• the silicon single crystal pulled in the [110] direction is placed in the [001] direction at 0 °, 0.1 °, 1.0 °, 2.0 °. °, 4.0 °, 6.0 °, 7.9 °, and 10.0 ° were cut at an angle to produce wafers.
• RCA cleaning was performed.
• These mirror-polished silicon semiconductor substrates were subjected to a heat treatment at 115 ° C. for 1 hour in a hydrogen gas atmosphere.
• FIG. 10 shows the dependence of Rms of the hydrogen heat-treated silicon semiconductor substrate on the slight inclination angle.
• a mirror-polished silicon semiconductor substrate is also shown.
• the tilt angle is 0 °
• the Rms of the mirror-polished silicon semiconductor substrate and the Rms of the hydrogen-heat treated silicon semiconductor substrate are 0.118 nm and 0.111 nm, respectively.
• the dependence of Rms on the slight tilt angle is the same as that of the epitaxial silicon semiconductor substrate. That is, the surface roughness of the hydrogen-heat-treated silicon semiconductor substrate is reduced from 0.1 ° to 7.9 ° at a slight inclination angle as compared with the mirror-polished silicon semiconductor substrate.
• Fig. 5 shows an AFM image when the tilt angle is 0-1 °
• Fig. 6 shows a schematic diagram of the AFM image.
• steps and terraces are formed.
• the steps and terraces are harder to form than the epitaxial silicon semiconductor substrate, but the surface roughness Rms of the slightly inclined heat-treated silicon semiconductor substrate is smaller than that of the mirror-polished silicon semiconductor substrate, so that the surface of the carrier is reduced. Scattering due to roughness can be reduced. (Example 3)
• Mirror-polished silicon semiconductor substrates with the main surface inclined at ⁇ 100 ⁇ over the ⁇ 110 ⁇ plane at 0 °, 0.1 °, and 7.9 ° and a thickness of 5
• An epitaxial silicon semiconductor substrate on which an m silicon single crystal thin film was formed and a heat-treated silicon semiconductor substrate heat-treated in a hydrogen atmosphere were used.
• the diameter, electrical resistivity, and oxygen concentration of the mirror-polished silicon substrate are 150 mm, p-type 10 to 12 Qcm, and 16 ppma (converted to JEI DA), respectively.
• the electrical resistivity of the epitaxial silicon layer was centered at 11 ⁇ cm.
• Hydrogen heat treatment is a treatment at 1150 ° C for 1 hour.
• a non-tilted ⁇ 100 ⁇ mirror-polished silicon semiconductor substrate was also added as a reference sample.
• the electrical resistivity and oxygen concentration are almost the same as the above values.
• JEIDA is the abbreviation of Japan Electronics Industry Promotion Association (currently JEITA: renamed Japan Electronics and Information Technology Industries Association).
• a n-type field-effect transistor was formed.
• For the first element isolation form the shape of the trench for device isolation by STI (S hall ow T rench I solation) method, filling the trench with the silicon oxide film (S i ⁇ 2).
• RCA cleaning was performed to remove organic substances, particles, and metals, and a 5 nm gate oxide film was formed in a dry oxidizing atmosphere.
• Boron (B) was ion-implanted over the entire surface of the substrate to control the gate threshold voltage.
• a polycrystalline silicon film is deposited on the entire surface of the substrate by a CVD (Chemical Vapor or Deposition) method, and is patterned to form a polycrystalline silicon film on the gate oxide film in the transistor formation region. Silicon electrodes were formed.
• phosphorus (P) was ion-implanted at a low concentration to form an n- ⁇ source and an n- ⁇ drain region for relaxing the high electric field. One where electrons flow The direction is the ⁇ 1 110> direction.
• a silicon oxide film was deposited on the entire surface of the substrate by CVD so as to cover the gate electrode, and anisotropic etching was performed to form a side wall insulating film on the side wall of the gate electrode.
• the electron mobility of the slightly polished mirror-polished silicon semiconductor substrate is about 0.8 times that of the ⁇ 100 ⁇ plane, which is inferior to that of the ⁇ 110 ⁇ plane without inclination. Since it is 1.3 times higher, the effect of tilting is apparent.
• the conventional RCA cleaning method was used in the semiconductor device fabrication process, but electron mobility may be further improved by improving the cleaning method and the heat treatment method. For example, by performing the above-described five-step cleaning and radical sacrificial acid value treatment, the surface roughness can be further improved, and the carrier mobility can be expected to be higher.
• the silicon semiconductor substrate of the present invention is flattened at the atomic level, the surface roughness is reduced by about 10% as compared with the conventional silicon semiconductor substrate, and the surface step at the atomic level is reduced. Since it is formed along the direction in which the carrier of the device flows, the carrier mobility of the semiconductor device can be improved by up to 40% as compared with the case of the conventional silicon semiconductor substrate.
• the silicon semiconductor substrate of the present invention as a substrate of a semiconductor integrated circuit device, high performance of the device performance can be realized. Further, according to the method of the present invention, the silicon semiconductor substrate of the present invention can be effectively manufactured.

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• Insulated Gate Type Field-Effect Transistor (AREA)
• Recrystallisation Techniques (AREA)
• Crystals, And After-Treatments Of Crystals (AREA)

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