JPS6170748A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS6170748A
JPS6170748A JP59191542A JP19154284A JPS6170748A JP S6170748 A JPS6170748 A JP S6170748A JP 59191542 A JP59191542 A JP 59191542A JP 19154284 A JP19154284 A JP 19154284A JP S6170748 A JPS6170748 A JP S6170748A
Authority
JP
Japan
Prior art keywords
plane
face
substrate
face orientation
orientation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59191542A
Other languages
English (en)
Inventor
Masaaki Aoki
正明 青木
Toshiaki Masuhara
増原　利明
Shoji Hanamura
花村　昭次
Yoshio Sakai
芳男 酒井
Seiichi Isomae
誠一 磯前
Satoshi Meguro
目黒　怜
Shuji Ikeda
修二 池田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP59191542A priority Critical patent/JPS6170748A/ja
Priority to US06/774,705 priority patent/US4768076A/en
Publication of JPS6170748A publication Critical patent/JPS6170748A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8221—Three dimensional integrated circuits stacked in different levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明はＣＭＯＳデバイスに関し、従来に比べて高速で
動作できる半導体装置に関する。
〔発明の背景〕
特許公報昭４２−２１９７６ シリコン結晶面に作成したｎチャネルＭＯＳトランジス
タのキャリア移動度は、大野らの発明による特許（特公
昭４２−２１９７６）のに示されているように、（１０
０）面表面にデバイスを作成した場合にほぼ最大となる
。このため、従来、ＭＯ３集積回路は（１００）面ある
いはその近傍の面に作成されてきた。しかるにＰチャネ
ルＭＯＳトランジスタのキャリア移動度実測値は、第１
図に示すように、（１００）面表面にデバイスを作成し
た場合にほぼ最小となることが明らかである。ｎチャネ
ルトランジスタとＰチャネルトランジスタを同一基板上
に集積化したＣＭＯＳデバイスの動作速度は、ｎ＋Ｐ両
タイプのトランジスタのキャリア移動度値に等しく依存
している。
従って、ＰｕＯ２のキャリア移動度がほぼ最小となって
しまう（１ｏＯ）面は、ＣＭＯＳデバイス用の最適面方
位ではないことが明らかである。
〔発明の目的〕
本発明の目的は、ＣＭＯＳデバイスの高速動作にとって
最適な結晶面を用いた、ＣＭＯＳデバイス構造を提供す
ることである。
〔発明の概要〕
第２図に示すようなＣＭＯＳインバータの遅延時間につ
いて、その面方位依存性を室温において実測した結果を
第３図に示す。ここで、ｎ＋Ｐ両ＭＯ３は同一サイズ（
同一のゲート長とゲート幅）で形成している。また、ｎ
、ｐｉｉｊｉＭＯｓのチャネルは同一方向に形成してお
り、これを面内で（１００＞方向に、平行に形成した結
果には／＜１００＞と付記し、＜ｉｏｏ＞方向に垂直に
形成した結果には上＜ｉｏｏ＞と付記した。
＜ｏｉｔ＞方向に関しても同様である。第３図に示した
、インバータ遅延の面方位依存性の結果より、同遅延は
（１１０）面と（０２３）面あるいはその近傍で最小に
なることが明らかである。
本発明は、ＣＭＯＳデバイスの高速化を図るために、（
１１０）面方位または（０２３）面方位、あるいはその
近傍の面方位（実質的に前記面に平行な面方位）の半導
体結晶面にＣＭＯＳデバイスを作成することを特徴とし
ている。
また、低温では第１図に示したようなキャリア移動度の
面方位依存性がより顕著となり、面による移動度の差が
より増幅される。従って、上記したような結晶面の採用
は、ＣＭＯＳデバイスを低温下（例えば１００に以下）
で動作させる場合により大きな効果を発揮して、デバイ
スの高速化に役立つ。
〔発明の実施例〕
以下、本発明の実施例を第４図により説明する。
第４図において４０は（１１０）面方位または（０２３
）面方位のｎ型Ｓｉ基板で、４１はｐ型ウェルである。
以下、通常のＣＭＯＳプロセスに従って、ｐチャネルＭ
Ｏ３ＦＥＴは基板４０の表面領域に４２．４３なるＰ型
高濃度不純物領域をそれぞれソース、ドレインとして、
４６をゲートとして形成される。ｎチャネルＭＯ３ＦＥ
Ｔはｐウェル４１の表面領域に４４．４５なるｎ型濃度
不純物領域をそれぞれドレイン、ソースとして。
４７をゲートとして形成される。４６と４７を接続して
入力端子４８とし、４３と４４を接続して出力端子４９
とし、４２を電源端子、４５を接地端子とすれば１本発
明のＣＭＯＳインバータ回路を構成できる。
本実施例では、基板の結晶面方位として（１１０）面ま
たは（０２３）面を採用したため。
室温におけるＣＭＯＳインバータ遅延は従来値の約７割
まで短縮する。低温、例えばＩ　ＯＯＫ以下では面によ
る移動度の差がより増幅されるので。
同遅延をさらに、大幅に短くすることができる。
上記実施例ではｎ基板を用いたＣＭＯＳデバイスの実施
例を述べたが１本発明は基板に（１１０）面方位または
（０２３）面方位のｐ型Ｓｉ基板を用いてＣＭ　ＯＳデ
バイスを作成する場合にも実現可能であることは勿論で
ある。
【図面の簡単な説明】
第１図はｐＭＯＳ）−ランジスタのキャリア移動度の面
方位依存性を示す図、第２図はＣＭＯＳインバータの回
路図、第３図はＣＭＯＳインバータ遅延の面方位依存性
を示す図、第４図は本発明のＣＭＯＳデバイス構造の実
施例を示す図である。 ４０・・・　ｎ基板、４１　・・・　Ｐウェル、４２．
４３．４６−−・　ｐＭＯｓのソーＸ、Ｉ−’Ｌ／イン
、ゲート、４４，４５．４７−　ｎＭＯ３のドレイン、
ソース、ゲート。 笛１図 面方位 ｃｃ 第３図 懐 ｌｆｌ　　方　位

Claims (1)

  1. 【特許請求の範囲】 １、ほぼ平坦な面を有する半導体基体と、前記基体の第
    １導電型領域中に形成された第２導電型のソース、ドレ
    イン領域と、前記面上に形成された絶縁ゲートからなる
    第２導電型のＭＯＳトランジスタを含み、前記基体の第
    ２導電型領域中に形成された第１導電型のソース、ドレ
    イン領域と、前記面上に形成された絶縁ゲートからなる
    第１導電型ＭＯＳトランジスタを含み、前記ほぼ平坦な
    面は（１１０）面または（０２３）面あるいはその近傍
    の面に平行な結晶面であることを特徴とする半導体装置
    。 ２、１００Ｋ以下の温度範囲で動作させることを特徴と
    する特許請求の範囲第１項記載の半導体装置。
JP59191542A 1984-09-14 1984-09-14 半導体装置 Pending JPS6170748A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP59191542A JPS6170748A (ja) 1984-09-14 1984-09-14 半導体装置
US06/774,705 US4768076A (en) 1984-09-14 1985-09-11 Recrystallized CMOS with different crystal planes

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59191542A JPS6170748A (ja) 1984-09-14 1984-09-14 半導体装置

Publications (1)

Publication Number Publication Date
JPS6170748A true JPS6170748A (ja) 1986-04-11

Family

ID=16276403

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59191542A Pending JPS6170748A (ja) 1984-09-14 1984-09-14 半導体装置

Country Status (1)

Country Link
JP (1) JPS6170748A (ja)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6292361A (ja) * 1985-10-17 1987-04-27 Toshiba Corp 相補型半導体装置
JPH0235808A (ja) * 1988-07-25 1990-02-06 Nec Corp 演算増幅器
JP2002131161A (ja) * 2000-10-27 2002-05-09 Denso Corp 半導体圧力センサ
WO2003032399A1 (fr) * 2001-10-03 2003-04-17 Tokyo Electron Limited Dispositif semi-conducteur fabrique a la surface de silicium ayant un plan cristallin de direction <110> et procede de production correspondant
US6657259B2 (en) 2001-12-04 2003-12-02 International Business Machines Corporation Multiple-plane FinFET CMOS
US6794718B2 (en) * 2002-12-19 2004-09-21 International Business Machines Corporation High mobility crystalline planes in double-gate CMOS technology
JP2007027677A (ja) * 2005-06-17 2007-02-01 Tohoku Univ 半導体装置
US7411274B2 (en) 2003-02-07 2008-08-12 Shin-Etsu Handotai Co., Ltd. Silicon semiconductor substrate and its manufacturing method
JP2009141376A (ja) * 2009-01-05 2009-06-25 Tadahiro Omi 相補型ｍｉｓ装置

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6292361A (ja) * 1985-10-17 1987-04-27 Toshiba Corp 相補型半導体装置
JPH0235808A (ja) * 1988-07-25 1990-02-06 Nec Corp 演算増幅器
JP2002131161A (ja) * 2000-10-27 2002-05-09 Denso Corp 半導体圧力センサ
WO2003032399A1 (fr) * 2001-10-03 2003-04-17 Tokyo Electron Limited Dispositif semi-conducteur fabrique a la surface de silicium ayant un plan cristallin de direction <110> et procede de production correspondant
JP2003115587A (ja) * 2001-10-03 2003-04-18 Tadahiro Omi ＜１１０＞方位のシリコン表面上に形成された半導体装置およびその製造方法
US6903393B2 (en) 2001-10-03 2005-06-07 Tadahiro Ohmi Semiconductor device fabricated on surface of silicon having <110> direction of crystal plane and its production method
US6657259B2 (en) 2001-12-04 2003-12-02 International Business Machines Corporation Multiple-plane FinFET CMOS
US6815277B2 (en) 2001-12-04 2004-11-09 International Business Machines Corporation Method for fabricating multiple-plane FinFET CMOS
US6794718B2 (en) * 2002-12-19 2004-09-21 International Business Machines Corporation High mobility crystalline planes in double-gate CMOS technology
US7411274B2 (en) 2003-02-07 2008-08-12 Shin-Etsu Handotai Co., Ltd. Silicon semiconductor substrate and its manufacturing method
JP2007027677A (ja) * 2005-06-17 2007-02-01 Tohoku Univ 半導体装置
JP2009141376A (ja) * 2009-01-05 2009-06-25 Tadahiro Omi 相補型ｍｉｓ装置

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