JP4055941B2 - 原子層堆積法を用いて基板上に高誘電率材料を堆積する方法 - Google Patents

原子層堆積法を用いて基板上に高誘電率材料を堆積する方法 Download PDF

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JP4055941B2
JP4055941B2 JP2002180523A JP2002180523A JP4055941B2 JP 4055941 B2 JP4055941 B2 JP 4055941B2 JP 2002180523 A JP2002180523 A JP 2002180523A JP 2002180523 A JP2002180523 A JP 2002180523A JP 4055941 B2 JP4055941 B2 JP 4055941B2
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atomic layer
layer deposition
deposition chamber
nitrate
introducing
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JP2003068732A (ja
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オノ ヨシ
サン ウェイ−ウェイ
サランキ ラジェンドラ
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Description

【０００１】
【発明の属する技術分野】
本発明は、概して、集積回路（ＩＣ）製造プロセスに関し、より詳細には、シリコン上に高誘電率材料を形成する方法に関する。
【０００２】
【従来の技術】
現在Ｓｉ ＶＬＳＩ技術では、ＭＯＳデバイスのゲート誘電体としてＳｉＯ２が用いられている。デバイスのサイズが縮小されていくにつれ、ゲート領域とチャネル領域との間で同じキャパシタンスを維持するためには、ＳｉＯ２層の厚さも薄くする必要がある。将来的には、２ナノメートル（ｎｍ）未満の厚さが予想される。しかしながら、そのようなＳｉＯ２薄層では高いトンネル電流を無視できなくなるため、別の材料を考える必要がある。高誘電率材料を用いれば、ゲート誘電体層をさらに薄くすることができ、その結果トンネル電流の問題も解消する。これらのいわゆるＨｉｇｈ−ｋ誘電体膜を、本明細書中では、二酸化シリコンと比べて高誘電率を有する誘電体膜として定義する。典型的には、二酸化シリコンの誘電率は約４であるが、約１０を超える誘電率を有するゲート誘電体材料を用いることが望ましい。
【０００３】
１．５ｎｍ未満の薄さのＳｉＯ２膜は、一般に、高い直接トンネル電流が生じるため、ＣＭＯＳデバイスのゲート誘電体として用いることはできない。現在、ＳｉＯ２をＴｉＯ２およびＴａ２Ｏ５に置き換えるための研究における多大な努力が、最大の関心を呼んでいる。しかしながら、堆積後の高温アニーリングを行うと、該酸化膜とＳｉの反応により界面にＳｉＯ２層が形成される為、１．５ｎｍ未満の等価ＳｉＯ２厚さ（これは、酸化物換算膜厚（ＥＯＴ）としても知られている）の実現を非常に困難にしている。０．０７マイクロメートルデバイス世代では、約１．０ｎｍ（およびこれ以下）のＥＯＴを用いることが予想される。
【０００４】
ハフニウム酸化物（ＨｆＯ２）およびジルコニウム酸化物（ＺｒＯ２）等の材料は、Ｈｉｇｈ−ｋ誘電体材料の主用な候補である。これらの材料の誘電率は、約２０〜２５であり、二酸化シリコンの誘電率の５〜６倍である。このことは、膜全体が、基本的に、Ｈｉｇｈ−ｋ材料から構成されていると仮定した場合、これらの材料の約５〜６ｎｍの厚さを用いれば、約１．０ｎｍのＥＯＴを実現することができるということを意味している。Ｈｉｇｈ−ｋ材料を用いる１つの問題は、低誘電率を有する二酸化シリコン界面層またはシリケート層が、標準のプロセシング時に形成するということである。
【０００５】
原子層堆積法（ＡＬＤ）と四塩化物前駆体とを用いた、ＺｒＯ２またはＨｆＯ２の堆積が報告されている。３００℃〜４００℃まで加熱された基板をＺｒＣｌ４またはＨｆＣｌ４、水蒸気を含んだ別の前駆体に曝して、ＺｒＯ２膜またはＨｆＯ２膜をそれぞれ形成する。しかしながら、水素終端したシリコン表面上に堆積するのは困難である。水素終端したシリコン表面は、標準的な産業の洗浄プロセスによって得られる。これらの標準洗浄プロセスは、ＨＦ最終洗浄と呼ばれる場合が多く、典型的には、ＨＦに一瞬だけ浸漬させて終了する。このプロセスによって、水素終端した表面（水素パッシベーションとも呼ばれる）が生成する。シリコン表面を反応物に十分に曝すことによって、最終的には、堆積を開始することができる。
【０００６】
【発明が解決しようとする課題】
しかしながら、この結果得られる膜は、均一性に欠ける粗い膜である。四塩化物前駆体に伴う別の問題は、膜内に残留する塩化物が入ることである。塩素不純物は、長期間の信頼性および性能の問題となり得る。
【０００７】
他の前駆体として、イソ−プロポキシド、ＴＭＨＤ（２，２，６，６−テトラメチル−３，５−ヘプタンジオネート）等の有機リガンド、または、有機リガンドと塩素とを合わせたものと結合されたＨｆ金属またはＺｒ金属が用いられる。これらの前駆体もまた、水素終端したシリコン表面上への膜堆積の開始問題を有し、膜中に残留する炭素を取り込む。大きなリガンドはまた、立体障害が均一な分子層の堆積を防ぐだけの十分な空間を設けることになり得る。現在まで、ＡＬＤによるＺｒ酸化物およびＨｆ酸化物は、シリコン酸化物およびシリコン酸窒化物の初期層上に堆積するか、または、ＺｒＳｉＯ４またはＨｆＳｉＯ４等の低誘電率シリケート膜の形態で堆積するかのいずれかで達成され得る。これらの初期層は、ＥＯＴ全体に大きく寄与し得る。
【０００８】
【課題を解決するための手段】
本発明による基板上にＨｉｇｈ−ｋ誘電体膜を形成する方法は、ａ）原子層堆積チャンバ内に、水素終端したシリコン表面を有する半導体基板を提供する工程と、ｂ）該半導体基板を１６０〜２００℃の範囲の温度まで加熱する工程と、ｃ）無水ハフニウム硝酸塩を前記原子層堆積チャンバ内に導入する工程と、ｄ）前記原子層堆積チャンバを窒素または不活性ガスでパージする工程と、ｅ）水蒸気、メタノール、または、水素である水和ガスを前記原子層堆積チャンバに導入して、ハフニウム酸化物の分子層を堆積する工程とを包含し、これにより上記目的が達成される。
【００１３】
前記無水ハフニウム硝酸塩を原子層堆積チャンバ内に導入する工程と、前記原子層堆積チャンバをパージする工程と、前記水和ガスを原子層堆積チャンバに導入する工程とを繰り返す工程をさらに包含してもよい。
【００１４】
前記繰り返す工程は、２０オングストローム未満の厚さの酸化物換算膜厚を有するハフニウム酸化物膜が得られるまで繰り返されてもよい。
【００１５】
本発明による基板上にＨｉｇｈ−ｋ誘電体膜を形成する方法は、ａ）原子層堆積チャンバ内に、水素終端したシリコン表面を有する半導体基板を提供する工程と、ｂ）該半導体基板を、１６０〜２００℃の範囲の温度まで加熱する工程と、ｃ）無水ジルコニウム硝酸塩を前記原子層堆積チャンバ内に導入する工程と、ｄ）前記原子層堆積チャンバを窒素でパージする工程と、ｅ）水蒸気、メタノール、または、水素である水和ガスを前記原子層堆積チャンバに導入して、ジルコニウム酸化物の分子層を堆積する工程とを包含し、これにより上記目的が達成される。
【００２０】
前記無水ジルコニウム硝酸塩を原子層堆積チャンバ内に導入する工程と、前記原子層堆積チャンバをパージする工程と、前記水和ガスを原子層堆積チャンバに導入する工程とを繰り返す工程をさらに包含してもよい。
【００２１】
前記繰り返す工程は、２０オングストローム未満の厚さの酸化物換算膜厚を有するジルコニウム酸化物膜が得られるまで繰り返されてもよい。
【００２６】
従って、高誘電率材料（ＺｒＯ２またはＨｆＯ２）を形成する方法を提供する。上記方法は、水素終端したシリコン表面上に高誘電率材料を形成するに適していが、上記方法を種々の基板上にこれらの材料を形成するために用いることも可能である。
【００２７】
基板上にジルコニウム酸化物を形成する方法が提供される。上記方法は、原子層堆積チャンバ内に半導体基板を提供する工程と、上記基板を原子層堆積レジーム内の温度まで加熱する工程と、無水ジルコニウム硝酸塩を上記チャンバ内に導入する工程と、上記チャンバを窒素でパージする工程と、水蒸気を上記チャンバに導入して、ジルコニウム酸化物の分子層を堆積する工程とを包含する。無水ジルコニウム硝酸塩を導入する工程と、チャンバを窒素でパージする工程と、水蒸気を導入する工程とは、必要に応じて繰り返され、所望の厚さのジルコニウム酸化物膜を生成することができる。
【００２８】
基板上にハフニウム酸化物を形成する方法が提供される。上記方法は、原子層堆積チャンバ内に半導体基板を提供する工程と、上記基板を原子層堆積レジーム内の温度まで加熱する工程と、無水ハフニウム硝酸塩を上記チャンバ内に導入する工程と、上記チャンバを窒素でパージする工程と、水蒸気を上記チャンバに導入して、ハフニウム酸化物の分子層を堆積する工程とを包含する。無水ハフニウム硝酸塩を導入する工程と、チャンバを窒素でパージする工程と、水蒸気を導入する工程とは、必要に応じて繰り返され、所望の厚さのハフニウム酸化物膜を生成することができる。
【００２９】
ハフニウム酸化物とジルコニウム酸化物とを含むナノ積層を形成する方法が提供される。上記方法は、ジルコニウム酸化物を形成する方法について上述した上記工程を繰り返す工程と、ハフニウム酸化物を形成する方法について上述した上記工程を繰り返す工程と、所望ならば、上記工程を交互に行って、ＨｆＯ２／ＺｒＯ２／ＨｆＯ２／ＺｒＯ２等のナノ積層を生成する工程とを包含する。
【００３０】
【発明の実施の形態】
図１は、ＨｆＯ２膜またはＺｒＯ２膜を堆積するプロセスの工程を示すフローチャートを示す。工程１１０において、ＡＬＤチャンバ内に半導体基板を提供する。市販のＡＬＤツールが入手可能である。ＦｉｎｌａｎｄのＭｉｃｒｏｃｈｅｍｉｓｔｒｙ．Ｌｔｄ（現在は、ＡＳＭ部）がＡＬＤツール（Ｍｏｄｅｌ Ｆ１２０）を製造している。このＡＬＤツールは、本明細書中に記載のプロセスとともに用いられ得る。好適な実施形態において、半導体基板は、水素終端したシリコン表面を有する。本明細書中に記載のプロセスは、水素終端したシリコン表面にＨｆＯ２またはＺｒＯ２を堆積する工程に関する問題の解決に適しているが、このプロセスを用いて、二酸化シリコン、シリコン酸窒化物、シリコンゲルマニウムを含む他の表面上、および、ＺｒＳｉＯ４およびＨｆＳｉＯ４等のシリケート上にＨｆＯ２またはＺｒＯ２を堆積することが、もっぱら可能である。
【００３１】
原子層堆積レジームの温度まで半導体基板を加熱する。例えば、約１６０〜２００℃の温度で無水ハフニウム硝酸塩を用いた場合、原子層堆積レジーム内において水素パッシベーションシリコン表面が得られた。
【００３２】
工程１２０において、無水ハフニウム硝酸塩（Ｈｆ（ＮＯ３）４）または無水ジルコニウム硝酸塩（Ｚｒ（ＮＯ３）４）をＡＬＤチャンバ内に導入する。ハフニウム硝酸塩またはジルコニウム硝酸塩は、半導体基板のシリコン表面が水素終端されている場合であっても、その基板表面上に吸着する。
【００３３】
無水ハフニウム硝酸塩および無水ジルコニウム硝酸塩は、現在市販されていないが、これらの材料の合成法および精製法は公知である。ジルコニウム硝酸塩の合成については、１９６２年に報告されている。ハフニウムとジルコニウムとが類似しているため、ハフニウム硝酸塩もまた、同様の合成法によって単離することができる。ハフニウム硝酸塩は、３０℃の五酸化二窒素中で四塩化ハフニウムを還流することによって調製され得、その後、そのハフニウム硝酸塩を１００℃／０．１ｍｍＨｇで昇華して精製し得る。ジルコニウム硝酸塩も同様に、９５℃／０．１ｍｍＨｇで精製され得る。
【００３４】
工程１３０において、ＡＬＤチャンバを窒素ガスまたは不活性ガス（アルゴン、ヘリウムまたはネオン）でパージして、過剰な無水ハフニウム硝酸塩または無水ジルコニウム硝酸塩、あるいは、不要な反応物を少なくするか、または、除去する。
【００３５】
工程１４０において、ＡＬＤチャンバ内に水和ガスを導入する。水和ガスは、水素を提供して、硝酸塩および二酸化窒素を含む窒化物の除去を促進する。水和ガスは、ハフニウム酸化物膜またはジルコニウム酸化物膜を形成するために用いられる、ＮＯ３または酸素原子を伴ったＮＯ２の形態のいずれかであるＮＯ３リガンドの除去を促進する。水和ガスは、水蒸気、メタノール、または、水素であり得る。正確な化学メカニズムは、完全には理解されておらず、特許請求の範囲を限定するものではない。
【００３６】
工程１４５において、ＡＬＤチャンバを窒素または不活性ガスでパージして、チャンバ内の水和ガスおよび恐らく不要となり得る反応物を少なくするか、または、除去する。
【００３７】
工程１５０において、工程１２０、１３０、１４０および１４５を繰り返し、所望の厚さの膜を生成する。ＡＬＤプロセスは、適切にパージした状態で、硝酸塩、ハフニウム硝酸塩またはジルコニウム硝酸塩、および、水和ガスに交互に曝すサイクル数によって制限された固有の成長速度を有する。
【００３８】
工程１６０において、所望のサイクル数だけ繰り返した後に、膜をアニーリングして、その膜と界面とを調整する。
【００３９】
例えば、基板を１０ミリトール（ｍＴｏｒｒ）のＡＬＤチャンバ内に配置し、約１８０℃まで加熱することによって、ハフニウム酸化物膜は、表面が水素終端したシリコン基板上に形成される。基板は、ＡＬＤサイクルを複数回行って処理された。各ＡＬＤサイクルには、無水ハフニウム硝酸塩を導入する工程と、窒素でパージする工程と、水蒸気を導入する工程とが含まれる。各ＡＬＤサイクルを約７回、１３回、１７回および４００回行ってサンプルを生成した。
【００４０】
分光エリプソメータを用いて各サンプルの厚さを測定した。４００サイクルのサンプルの厚さは、１２８．１ｎｍであった。これは、約３．２Å／サイクルの堆積速度に相当する。より薄いサンプルでは、堆積速度は、３．６Å／サイクルであった。ハフニウム酸化物のバルク密度が９．６８ｇ／ｃｍ３と記載されていることを考慮すれば、１モル相当の換算膜厚は３６．１Åであり、１分子層は、約３．３Å厚であると予想される。従って、３．２Å／サイクル〜３．６Å／サイクルの堆積速度は、１サイクル当りの１分子層の堆積に匹敵する。また、堆積速度は温度によっても影響を受けることが分かった。１７０℃で生成されたサンプルの堆積速度は、２．８Å／サイクルであった。
【００４１】
次に、ハフニウム酸化物層およびジルコニウム酸化物層を含むナノ積層または多層膜を生成するためのフローチャートを図２に示す。工程２１０において、ＡＬＤチャンバ内に半導体基板を提供する。半導体基板を原子層堆積レジームの温度まで加熱する。
【００４２】
工程２２０において、無水ハフニウム硝酸塩（Ｈｆ（ＮＯ３）４）または無水ジルコニウム硝酸塩（Ｚｒ（ＮＯ３）４）のいずれか（第１の硝酸塩）をＡＬＤチャンバ内に導入する。この工程２２０で導入されたハフニウム硝酸塩またはジルコニウム硝酸塩は半導体基板の表面に吸着する。
【００４３】
工程２３０において、ＡＬＤチャンバを窒素ガスまたは不活性ガスでパージして、過剰な無水ハフニウム硝酸塩または無水ジルコニウム硝酸塩、あるいは、不要な反応物を少なくするか、または、除去する。
【００４４】
工程２４０において、水和ガスをＡＬＤチャンバ内に導入する。水和ガスは、ハフニウム酸化物膜またはジルコニウム酸化物膜を形成するために用いられる、ＮＯ３または酸素原子を伴ったＮＯ２の形態のいずれかであるＮＯ３リガンドの除去を促進する。
【００４５】
工程２４５は、ＡＬＤチャンバを窒素ガスまたは不活性ガスでパージして、チャンバ内の水和ガスおよび恐らく不要となり得る反応物を少なくするか、または、除去する。
【００４６】
工程２５０において、工程２２０、２３０、２４０および２４５を繰り返して、第１の硝酸塩の所望の厚さの材料層（ハフニウム酸化物またはジルコニウム酸化物のいずれかの層）を生成する。ＡＬＤプロセスは、適切にパージした状態で、硝酸塩、ハフニウム硝酸塩またはジルコニウム硝酸塩、および、水和ガスに交互に曝すサイクル数によって制限された固有の成長速度を有する。工程２５０によって示されるサイクルを繰り返して、各層がハフニウム酸化物またはジルコニウム酸化物のいずれかの材料からなり、所望の厚さを有した層を形成することができる。
【００４７】
工程３２０において、工程２２０で導入しなかった無水ハフニウム硝酸塩（Ｈｆ（ＮＯ３）４）または無水ジルコニウム硝酸塩（Ｚｒ（ＮＯ３）４）（第２の硝酸塩）をＡＬＤチャンバに導入する。この工程３２０で導入されるハフニウム硝酸塩またはジルコニウム硝酸塩は、半導体基板の表面に吸着する。
【００４８】
工程３３０において、ＡＬＤチャンバを窒素ガスまたは不活性ガスでパージして、過剰の無水ハフニウム硝酸塩または無水ジルコニウム硝酸塩、あるいは、不要な反応物を少なくするか、または、除去する。
【００４９】
工程３４０において、ＡＬＤチャンバ内に水和ガスを導入する。水和ガスは、工程２４０で形成されたなかったハフニウム酸化物膜またはジルコニウム酸化物膜のいずれかを形成するために用いられる、ＮＯ３または酸素原子を伴ったＮＯ２の形態のいずれかであるＮＯ３リガンドの除去を促進する。
【００５０】
工程３４５において、ＡＬＤチャンバを窒素ガスまたは不活性ガスでパージして、チャンバ内の水和ガスおよび恐らく不要となり得る反応物を少なくするか、または、除去する。
【００５１】
工程３５０において、工程３２０、３３０、３４０および３４５を繰り返して、所望の厚さのハフニウム酸化物またはジルコニウム酸化物のいずれかの材料の層を生成する。さらに、工程３５０では、再度、工程２２０から上述の工程を繰り返す工程を包含する。これにより、複数の交互層を有する膜、例えば、ＨｆＯ２／ＺｒＯ２／ＨｆＯ２／ＺｒＯ２、または、ＺｒＯ２／ＨｆＯ２／ＺｒＯ２／ＨｆＯ２／ＺｒＯ２が形成され得る。この場合、個々の層の厚さを別々に測定してもよいし、全体の厚さを測定してもよい。
【００５２】
工程３６０において、所望のサイクル数および所望のサブサイクル数を行った後、膜をアニーリングして、その膜と材料層間の界面とを調整する。
【００５３】
上述してきたように、本発明によれば、ハフニウム酸化物を形成する方法、ジルコニウム酸化物を形成する方法、および、ハフニウム酸化物とジルコニウム酸化物とのナノ積層を形成する方法が提供される。これらの方法は、ハフニウム硝酸塩およびジルコニウム硝酸塩等の硝酸塩を用いた前駆体を取り入れた原子層堆積法を利用する。これらの硝酸塩を用いた前駆体の使用は、水素パッシベーションシリコン表面上に高誘電率材料を形成するに適している。
【００５４】
【発明の効果】
本発明による基板上にＨｉｇｈ−ｋ誘電体膜を形成する方法は、ａ）原子層堆積チャンバ内に半導体基板を提供する工程と、ｂ）基板を原子層堆積レジーム内の温度まで加熱する工程と、ｃ）無水ハフニウム硝酸塩を原子層堆積チャンバ内に導入する工程とを包含する。上記工程によって、ハフニウム酸化物ソースである無水ハフニウム硝酸塩が半導体基板に吸着する。上記方法は、さらに、ｄ）原子層堆積チャンバを窒素または不活性ガスでパージする工程と、ｅ）水和ガスを原子層堆積チャンバに導入して、ハフニウム酸化物の分子層を堆積する工程とを包含する。上記窒素または不活性ガスで原子層堆積チャンバをパージすることによって、過剰な無水ハフニウム硝酸塩が除去される。上記水和ガスを原子層堆積チャンバに導入することによって、窒化物の除去を促進し、不純物のないＨｉｇｈ−ｋ誘電体膜（ハフニウム酸化物膜）が得られる。
【図面の簡単な説明】
【図１】図１は、ＨｆＯ２およびＺｒＯ２を堆積するプロセスのフローチャートである。
【図２】図２は、ＨｆＯ２およびＺｒＯ２のナノ積層を堆積するプロセスのフローチャートである。

Claims (6)

  1. 基板上にＨｉｇｈ−ｋ誘電体膜を形成する方法であって、
    ａ）原子層堆積チャンバ内に、水素終端したシリコン表面を有する半導体基板を提供する工程と、
    ｂ）該半導体基板を１６０〜２００℃の範囲の温度まで加熱する工程と、
    ｃ）無水ハフニウム硝酸塩を前記原子層堆積チャンバ内に導入する工程と、
    ｄ）前記原子層堆積チャンバを窒素または不活性ガスでパージする工程と、
    ｅ）水蒸気、メタノール、または、水素である水和ガスを前記原子層堆積チャンバに導入して、ハフニウム酸化物の分子層を堆積する工程と
    を包含する、方法。
  2. 前記無水ハフニウム硝酸塩を原子層堆積チャンバ内に導入する工程と、前記原子層堆積チャンバをパージする工程と、前記水和ガスを原子層堆積チャンバに導入する工程とを繰り返す工程をさらに包含する、請求項１に記載の方法。
  3. 前記繰り返す工程は、２０オングストローム未満の厚さの酸化物換算膜厚を有するハフニウム酸化物膜が得られるまで繰り返される、請求項２に記載の方法。
  4. 基板上にＨｉｇｈ−ｋ誘電体膜を形成する方法であって、
    ａ）原子層堆積チャンバ内に、水素終端したシリコン表面を有する半導体基板を提供する工程と、
    ｂ）該半導体基板を、１６０〜２００℃の範囲の温度まで加熱する工程と、
    ｃ）無水ジルコニウム硝酸塩を前記原子層堆積チャンバ内に導入する工程と、
    ｄ）前記原子層堆積チャンバを窒素でパージする工程と、
    ｅ）水蒸気、メタノール、または、水素である水和ガスを前記原子層堆積チャンバに導入して、ジルコニウム酸化物の分子層を堆積する工程と
    を包含する、方法。
  5. 前記無水ジルコニウム硝酸塩を原子層堆積チャンバ内に導入する工程と、前記原子層堆積チャンバをパージする工程と、前記水和ガスを原子層堆積チャンバに導入する工程とを繰り返す工程をさらに包含する、請求項４に記載の方法。
  6. 前記繰り返す工程は、２０オングストローム未満の厚さの酸化物換算膜厚を有するジルコニウム酸化物膜が得られるまで繰り返される、請求項５に記載の方法。
JP2002180523A 2001-06-28 2002-06-20 原子層堆積法を用いて基板上に高誘電率材料を堆積する方法 Expired - Lifetime JP4055941B2 (ja)

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