JP4133659B2 - ＣＭＯＳアプリケーション用の多重高κゲート誘電体を堆積する方法 - Google Patents

ＣＭＯＳアプリケーション用の多重高κゲート誘電体を堆積する方法 Download PDF

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JP4133659B2
JP4133659B2 JP2003275027A JP2003275027A JP4133659B2 JP 4133659 B2 JP4133659 B2 JP 4133659B2 JP 2003275027 A JP2003275027 A JP 2003275027A JP 2003275027 A JP2003275027 A JP 2003275027A JP 4133659 B2 JP4133659 B2 JP 4133659B2
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metal oxide
depositing
layer
ald
oxide layer
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JP2004153238A (ja
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エフ． コネリー ジュニア ジョン
芳睦 大野
ソランキ レジェンダー
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Sharp Corp
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Description

本発明は、集積回路製造、具体的には、トランジスタゲートをソース領域とドレイン領域との間のチャネルから分離するＭＯＳゲート誘電体を製造する方法に関する。
シリコン上の熱成長したＳｉＯ２は、ＭＯＳ技術の「心臓」と呼ばれてきた。Ｓｉ／ＳｉＯ２インターフェースは、低い界面およびバルクトラッピング、熱安定性、高い分解などの優良な半導体性質を有する。しかし、ミクロ電子部品技術の連続する世代のそれぞれにおいて、ゲート誘電体の厚さは、スケーリング、例えば、より薄くされる。厚さが、１．５ｎｍ未満にスケーリングされる場合、例えば、直接的なトンネル効果からの漏れに起因する過剰な電力消費、ホウ素貫入、信頼性についての懸念などの問題が生じる。これらの問題により、近い将来、２００５年における８０ｎｍノードと同じくらい早くに、ゲート誘電体としてＳｉＯ２の優勢が衰え、最終的には終わる可能性がある。ＳｉＯ２は、任意の所与のキャパシタンスについて厚さがより厚く、より高い誘電率（κ）の材料にとってかわられる可能性が高い。
Ｃｏｎｌｅｙ，Ｊｒ．らによる「Ａｔｏｍｉｃ Ｌａｙｅｒ Ｄｅｐｏｓｉｔｉｏｎ ｏｆ Ｈａｆｎｉｕｍ Ｏｘｉｄｅ Ｕｓｉｎｇ Ａｎｈｙｄｒｏｕｓ Ｈａｆｎｉｕｍ Ｎｉｔｒａｔｅ」（Ｅｌｅｃｔｒｏｃｈｅｍ．ａｎｄ Ｓｏｌ．Ｓｔａｔｅ Ｌｅｔｔ．５（５）２００２年５月）
ＳｉＯ２の代用物に対するこのやむにやまれぬ近々の需要にも関わらず、適切な代替品は、依然として発見されていない。この代替的な材料の要件には、低い漏れ電流、低い界面トラップ、低いトラップされた電荷、良好な信頼性、良好な熱安定性、等角な堆積などが含まれる。有望な候補材料には、ＨｆＯ２、ＺｒＯ２などの金属酸化物、および他の金属酸化物が含まれる。
高κ膜を堆積する場合、低κ界面層を避けることが重要である。なぜなら、非常に薄い低κ界面層でさえ、上に重ねられる高κ材料の利点の殆どを打ち消し得るからである。従って、高κ材料を、Ｈ終端シリコン層の上に直接堆積することが重要である。
正角性および厚さの制御に対する要件のため、原子層堆積（ＡＬＤ）は、高κ材料の最も有望な堆積技術のうちの１つとして発生した。この技術において、誘電材料は、自己制御式の様態で、層ごとに構築される。すなわち、１つの化学種の単一層のみが所与の表面上に吸着する、堆積現象である。現在では、金属酸化物を堆積するための主要なＡＬＤ前駆物質は、ハロゲン化金属および有機金属である。また、いくつかの実験においては、高κ誘電体前駆物質として無水硝酸金属が用いられてきた。
塩化金属前駆物質、例えば、ＺｒＣｌ４などを用いて堆積されたＺｒＯ２の膜は、高κ誘電率および低い漏れ電流を含む良好な絶縁性質を示してきた。しかし、ＺｒＣｌ４の主な欠点は、Ｈ終端シリコン上に直接滑らかに堆積されないこと、いくつかの「育成」サイクルが必要であること、および均一に開始するためにＳｉＯ２の薄層が必要であることである。これらの問題は、塩化金属前駆物質が製造において用いられ得る前に解決される必要がある。
有機金属前駆物質の欠点は、有機的汚染の可能性があることである。Ｈｆ（ＮＯ３）４は、実行可能なＡＬＤ前駆物質であることが示されてきたが、「Ｍｅｔｈｏｄ ｔｏ Ｉｎｉｔｉａｔｅ ｔｈｅ Ａｔｏｍｉｃ Ｌａｙｅｒ Ｄｅｐｏｓｉｔｉｏｎ ｏｆ ａ Ｈｉｇｈ Ｄｉｅｌｅｃｔｒｉｃ Ｃｏｎｓｔａｎｔ Ｍａｔｅｒｉａｌ Ｄｉｒｅｃｔｌｙ ｏｎ ａ Ｓｉｌｉｃｏｎ Ｓｕｂｓｔｒａｔｅ」という名称の２００１年６月２８日に出願された米国特許出願第０９／８９４，９４１号、および、Ｃｏｎｌｅｙ，Ｊｒ．らによる「Ａｔｏｍｉｃ Ｌａｙｅｒ Ｄｅｐｏｓｉｔｉｏｎ ｏｆ Ｈａｆｎｉｕｍ Ｏｘｉｄｅ Ｕｓｉｎｇ Ａｎｈｙｄｒｏｕｓ Ｈａｆｎｉｕｍ Ｎｉｔｒａｔｅ」（Ｅｌｅｃｔｒｏｃｈｅｍ．ａｎｄ Ｓｏｌ．Ｓｔａｔｅ Ｌｅｔｔ．５（５）２００２年５月）において特定されているように、Ｈｆ（ＮＯ３）４の主な利点は、Ｈ終端シリコン上で直接堆積を開始することを可能にし、均一な薄層が得られることである。この方法は、低κ界面層を避ける可能性を有する。しかし、実験作業によって、Ｈｆ（ＮＯ３）４のＡＬＤを介して堆積されるＨｆＯ２膜は、誘電率が予測されるよりも低いことが示された。これは、恐らくは、酸素が豊富であるという膜の性質のためである。得られる膜の「バルク」誘電性質は、硝酸金属前駆物質が、幅広く用いられるようになるまえに改善される必要がある。
本発明の方法は、集積回路において高κ誘電材料の層を形成する方法であって、シリコン基板を準備する工程と、硝酸金属前駆物質を用いるＡＬＤを用いて第１の金属酸化物の層を堆積する工程と、塩化金属前駆物質を用いるＡＬＤを用いて他の金属酸化物の層を堆積する工程と、該集積回路を完成させる工程とを包含し、それによって上記目的を達成する。
前記準備する工程は、前記シリコン基板のＨ終端表面を形成する工程を含んでもよい。
前記形成する工程は、前記シリコン表面をＨＦにより露出させる工程を含んでもよい。
前記第１の金属酸化物の層を堆積する工程は、１〜５回のＡＬＤサイクルを用いて、金属酸化物の層を堆積する工程を含んでもよい。
前記他の金属酸化物の層を堆積する工程は、複数のＡＬＤサイクルを用いて、金属酸化物の層を堆積して、所望の金属酸化物層厚を得る工程を含んでもよい。
ＨｆＯ２、ＺｒＯ２、Ｇｄ２Ｏ３、Ｌａ２Ｏ３、ＣｅＯ２、ＴｉＯ２、Ｙ２Ｏ３、Ｔａ２Ｏ５、およびＡｌ２Ｏ３からなる金属酸化物の群から選択される、前記シリコン基板上に堆積される金属酸化物を選択する工程を含んでもよい。
前記第１の金属酸化物の層を堆積する工程は、約０．１ｎｍ〜１．５ｎｍの間の厚さの最初の金属酸化物の層を堆積する工程を含んでもよい。
前記他の金属酸化物の層を堆積する工程は、約３ｎｍ〜１０ｎｍの間の厚さの金属酸化物の層を堆積する工程を含んでもよい。
本発明の方法は、集積回路において高κ誘電ゲート酸化物の層を形成する方法であって、シリコン基板を準備する工程であって、該シリコン基板のＨ終端表面を形成する工程を含む、工程と、硝酸金属前駆物質を用いるＡＬＤを１〜５回用いて第１の金属酸化物の層を堆積して、所望の金属酸化物層厚を得る工程と、塩化金属前駆物質を用いるＡＬＤを複数回用いて他の金属酸化物の層を堆積する工程と、該集積回路を完成させる工程とを包含し、それにより上記目的を達成する。
前記形成する工程は、前記シリコン表面をＨＦにより露出させる工程を含んでもよい。
ＨｆＯ２、ＺｒＯ２、Ｇｄ２Ｏ３、Ｌａ２Ｏ３、ＣｅＯ２、ＴｉＯ２、Ｙ２Ｏ３、Ｔａ２Ｏ５、およびＡｌ２Ｏ３からなる金属酸化物の群から選択される、前記シリコン基板上に堆積される金属酸化物を選択する工程を含んでもよい。
前記第１の金属酸化物の層を堆積する工程は、約０．１ｎｍ〜１．５ｎｍの間の厚さの最初の金属酸化物の層を堆積する工程を含んでもよい。
前記他の金属酸化物の層を堆積する工程は、約３ｎｍ〜１０ｎｍの間の厚さの金属酸化物の層を堆積する工程を含んでもよい。
本発明の方法は、集積回路においてＨｆＯ２高κ誘電ゲート酸化物の層を形成する方法であって、シリコン基板を準備する工程であって、該シリコン基板のＨ終端表面を形成する工程を含む、工程と、Ｈｆ（ＮＯ３）４前駆物質を用いるＡＬＤを１〜５回用いて第１のＨｆＯ２金属酸化物の層を堆積して、所望の金属酸化物層厚を得る工程と、ＨｆＣｌ４前駆物質を用いるＡＬＤを複数回用いて他のＨｆＯ２の層を堆積する工程と、該集積回路を完成させる工程とを包含し、それにより上記目的を達成する。
前記形成する工程は、前記シリコン表面をＨＦにより露出させる工程を含んでもよい。
前記第１の金属酸化物の層を堆積する工程は、約０．１ｎｍ〜１．５ｎｍの間の厚さの最初の金属酸化物の層を堆積する工程を含んでもよい。
前記他の金属酸化物の層を堆積する工程は、約３ｎｍ〜１０ｎｍの間の厚さの金属酸化物の層を堆積する工程を含んでもよい。
集積回路において、高κ誘電材料の層を形成する方法は、シリコン基板を準備する工程と、硝酸金属前駆物質を用いるＡＬＤを用いて第１の金属酸化物の層を堆積する工程と、塩化金属前駆物質を用いるＡＬＤを用いて他の金属酸化物の層を堆積する工程と、集積回路を完成させる工程とを含む。
本発明の目的は、シリコン基板上に金属酸化物高κ層を堆積することである。
本発明の他の目的は、シリコン基板上に低κ界面層を形成することを必要とせずに、シリコン基板上に金属酸化物高κ層を堆積することである。
本発明の他の目的は、漏れ電流が低い性質を有する高κ層を提供することである。
本発明のこの要旨および目的は、本発明の性質を短時間で理解することを可能にするために提供されている。本発明のより完全な理解は、以下の本発明の好適な実施形態の詳細な説明を、図面とともに参照することによって得ることができる。
本発明の方法は、Ｈｆ（ＮＯ３）４の１回、または１〜５回までのサイクルで、Ｈ終端シリコン上のＡＬＤ堆積を開始し、その後、ＨｆＣｌ４のような他の前駆物質を用いて、所望の厚さまで、残りの膜のＡＬＤ堆積が続く。本発明の方法によって、最初の低κ界面層が必要なくなるが、依然として、高誘電率の「バルク」膜が達成されるようになる。
本出願は、「Ｍｅｔｈｏｄ ｔｏ Ｉｎｉｔｉａｔｅ ｔｈｅ Ａｔｏｍｉｃ Ｌａｙｅｒ Ｄｅｐｏｓｉｔｉｏｎ ｏｆ ａ Ｈｉｇｈ Ｄｉｅｌｅｃｔｒｉｃ Ｃｏｎｓｔａｎｔ Ｍａｔｅｒｉａｌ Ｄｉｒｅｃｔｌｙ ｏｎ ａ Ｓｉｌｉｃｏｎ Ｓｕｂｓｔｒａｔｅ」という名称の２００１年６月２８日に出願された米国特許出願第０９／８９４，９４１号に関連する。
ゲート形成の最新技術は、高温でのシリコンの酸化を必要とする。ＳｉＯ２が酸化金属、例えば、ＨｆＯ２、ＺｒＯ２などによって代用される可能性が高い。高κ堆積方法が未だ確立されていないにも関わらず、主要な技術は、原子層堆積（ＡＬＤ）である。ＡＬＤは、典型的には、単一の前駆物質、例えば、四塩化金属、有機金属、または無水硝酸金属を用いて行われる。上述したように、これらの前駆物質は、全て、大きな欠点を有する。
金属酸化物のＡＬＤについて現在利用可能な主要な前駆物質は、重大な欠点を有するので、本発明の方法は、得られる金属酸化物の膜の質を改善する前駆物質の組合せを含む。前駆物質の組合せは、各前駆物質の利点を利用し、前駆物質の使用に関連する欠点を最小にする。本発明の方法は、Ｈｆ（ＮＯ３）４の１回、または１〜５回までのサイクルで、Ｈ終端シリコン上のＡＬＤ堆積を開始し、その後、ＨｆＣｌ４のような他の前駆物質を用いて、所望の厚さまで、残りの膜のＡＬＤ堆積が続く。本発明の方法によって、最初の低κ界面層が必要なくなるが、依然として、高誘電率の「バルク」膜が達成されるようになる。
本発明の方法は、個々の前駆物質の強度を、組合せで、組み込み、Ｈ終端シリコン上に直接高κ膜を堆積することを達成する。Ｈｆ（ＮＯ３）４前駆物質は、Ｈ終端シリコン上で直接開始することを提供し、ＨｆＣｌ４の前駆物質を用いてさらなるＡＬＤのためのベース層を提供する。
別の前駆物質を用いることは上述されたが、このような別の前駆物質を用いることは、異なる前駆物質を用いて異なる金属酸化物、例えば、ＨｆＯ２−ＺｒＯ２、Ｔａ２Ｏ５−ＨｆＯ２などを挟んで、Ｈ．Ｚｈａｎｇらによる「Ｈｉｇｈ Ｐｅｒｍｉｔｔｉｖｉｔｙ Ｔｈｉｎ Ｆｉｌｍ Ｎａｎｏｌａｍｉｎａｔｅｓ」（Ｊ．Ａｐｐｌ．Ｐｈｙｓ．８７，１９２１（２０００））に記載されているようなナノラミネートを作成することを意味する。複数の堆積サイクルを用いて同じ金属酸化物を堆積する異なる前駆物質の組合せが報告されたということは確認されていない。
本発明の方法は、ＡＬＤを用いるゲート酸化物堆積の方法を説明する。１回目、または１〜５回目までのＡＬＤ堆積サイクルは、無水硝酸ハフニウム（Ｈｆ（ＮＯ３）４）を前駆物質として用い、残りのサイクルは、前駆物質として、四塩ハフニウム（ＨｆＣｌ４）を用いる。１回のＡＬＤ堆積サイクルは、前駆物質、すなわち、硝酸ハフニウムまたは四塩ハフニウムのパルス、続く窒素パージ、その後の水蒸気のパルス、最終的には、もう１つの窒素パージを含む。
図１を参照すると、ゲート酸化物の堆積前の構造は、任意の最新技術による方法によって形成される。このような方法には、シリコン基板１０およびフィールド酸化物領域１２および１４を準備する工程が含まれる。以下の図に示す例は、ゲート処理の代用である。ゲート酸化物の形成前の最後の工程は、シリコン表面をＨＦにより露出させて、Ｈ終端シリコン表面１６を準備することである。
図２に、Ｈｆ（ＮＯ３）４前駆物質を用いるＡＬＤを介して堆積されたＨｆＯ２の最初、または第１の層１８を示す。この工程の目的は、「育成」期間またはＳｉＯ２薄層を必要とせずに、Ｈ終端シリコン上に直接堆積を開始することである。最初の層は、約０．１〜１．５ｎｍの間の厚さで形成される。
図３に、ＨｆＣｌ４前駆物質を用いて所望の厚さまで堆積された、他のＨｆＯ２「バルク」層２０を示す。この所望の厚さは、好適な実施形態においては、約３〜１０ｎｍの間の厚さである。この工程の目的は、予測される高誘電率の「バルク」ＨｆＯ２膜を作成することである。
本発明のこの方法の製造プロセスは、エッチングプロセスまたはＣＭＰのいずれかが続く、ゲート材料、例えば、ゲート金属の堆積を進める。残りの工程は、当業者にとって周知の従来の製造プロセスである。本発明の方法は、最初の低κ界面層の必要性をなくし、依然として、高誘電率の膜を達成する。
ＨｆＯ２膜Ａが、Ｈｆ（ＮＯ３）４前駆物質を用いるＡＬＤの１回のサイクルを介して堆積され、その後、ＨｆＣｌ４前駆物質を用いるＡＬＤの４０回のサイクルが続いた。比較として、ＨｆＯ２膜Ｂが、１回のサイクルのＨｆ（ＮＯ３）４前駆物質を用いるＡＬＤ工程（ＡＬＤ硝酸工程）なしに、ＨｆＣｌ４前駆物質を用いるＡＬＤの４０回のサイクルのみを用いて堆積された。分光楕円偏光計測定によって、最初のＡＬＤ硝酸工程を用いて堆積されたＨｆＯ２膜Ａは、平均の厚さが８．０ｎｍであり、標準偏差が０．５ｎｍであったことが明らかにされた。ＡＬＤ硝酸工程なしで堆積されたＨｆＯ２膜Ｂは、平均の厚さが４．２ｎｍであり、標準偏差が１．８ｎｍであった。ＨｆＯ２膜ＡがＨｆＯ２膜Ｂよりも滑らかであり、厚いという事実は、本発明の方法の有用性を示している。すなわち、Ｈｆ（ＮＯ３）４前駆物質を用いるＡＬＤの１サイクルによって、後のＨｆＣｌ４前駆物質を用いるＡＬＤの開始層が有効に提供される。ＨｆＯ２膜Ａがより厚いという事実は、ＨｆＣｌ４ＡＬＤの典型的な「育成」期間が必要ないということを示す。
Ｈｆ（ＮＯ３）４を用いる、１回、または１〜５回までのＡＬＤサイクルで堆積された層は、他の前駆物質、例えば、ＭＩ４、ＭＢｒ４などのハロゲン化金属（Ｍは金属元素を表す）、または、アルコキシド、アセチルアセトネート、ｔ−ブトキシド、エトキシドなどの有機金属を用いるＡＬＤの開始層として用いられ得る。本明細書中に記載のＨｆＯ２処理に加えて、他の金属酸化物、例えば、ＺｒＯ２、Ｇｄ２Ｏ３、Ｌａ２Ｏ３、ＣｅＯ２、ＴｉＯ２、Ｙ２Ｏ３、Ｔａ２Ｏ５、Ａｌ２Ｏ３などが堆積され得る。
集積回路において、高κ誘電材料の層を形成する方法は、シリコン基板を準備する工程と、硝酸金属前駆物質を用いるＡＬＤを用いて第１の金属酸化物の層を堆積する工程と、塩化金属前駆物質を用いるＡＬＤを用いて他の金属酸化物の層を堆積する工程と、集積回路を完成させる工程とを含む。 上記のように、ＣＭＯＳアプリケーション用の多重高κゲート誘電体を堆積する方法が開示されてきた。この方法のさらなる変形および改変が、添付の特許請求の範囲に記載の発明の範囲内で行われ得ることが理解される。
本発明の方法は、Ｈｆ（ＮＯ３）４の１回、または１〜５回までのサイクルで、Ｈ終端シリコン上のＡＬＤ堆積を開始し、その後、ＨｆＣｌ４のような他の前駆物質を用いて、所望の厚さまで、残りの膜のＡＬＤ堆積が続く。本発明の方法によって、最初の低κ界面層が必要なくなるが、依然として、高誘電率の「バルク」膜が達成されるようになる。
図１は、Ｈ終端シリコン表面を有するシリコン基板を表す図である。 図２は、最初のＨｆＯ２層の堆積後の基板を表す図である。 図３は、第２および最後のＨｆＯ２層の堆積後の構造を表す図である。
符号の説明
１０ シリコン基板
１２ フィールド酸化物領域
１４ フィールド酸化物領域
１６ Ｈ終端シリコン表面

Claims (17)

  1. 集積回路において高κ誘電材料の層を形成する方法であって、
    シリコン基板を準備する工程と、
    硝酸金属前駆物質を用いるＡＬＤを用いて第１の金属酸化物の層を堆積する工程と、
    塩化金属前駆物質を用いるＡＬＤを用いて他の金属酸化物の層を堆積する工程と、
    該集積回路を完成させる工程と
    を包含する、方法。
  2. 前記準備する工程は、前記シリコン基板のＨ終端表面を形成する工程を含む、請求項１に記載の方法。
  3. 前記形成する工程は、前記シリコン表面をＨＦにより露出させる工程を含む、請求項２に記載の方法。
  4. 前記第１の金属酸化物の層を堆積する工程は、１〜５回のＡＬＤサイクルを用いて、金属酸化物の層を堆積する工程を含む、請求項１に記載の方法。
  5. 前記他の金属酸化物の層を堆積する工程は、複数のＡＬＤサイクルを用いて、金属酸化物の層を堆積して、所望の金属酸化物層厚を得る工程を含む、請求項１に記載の方法。
  6. ＨｆＯ２、ＺｒＯ２、Ｇｄ２Ｏ３、Ｌａ２Ｏ３、ＣｅＯ２、ＴｉＯ２、Ｙ２Ｏ３、Ｔａ２Ｏ５、およびＡｌ２Ｏ３からなる金属酸化物の群から選択される、前記シリコン基板上に堆積される金属酸化物を選択する工程を含む、請求項１に記載の方法。
  7. 前記第１の金属酸化物の層を堆積する工程は、０．１ｎｍ〜１．５ｎｍの間の厚さの最初の金属酸化物の層を堆積する工程を含む、請求項１に記載の方法。
  8. 前記他の金属酸化物の層を堆積する工程は、３ｎｍ〜１０ｎｍの間の厚さの金属酸化物の層を堆積する工程を含む、請求項１に記載の方法。
  9. 集積回路において高κ誘電ゲート酸化物の層を形成する方法であって、
    シリコン基板を準備する工程であって、該シリコン基板のＨ終端表面を形成する工程を含む、工程と、
    硝酸金属前駆物質を用いるＡＬＤを１〜５回用いて第１の金属酸化物の層を堆積して、所望の金属酸化物層厚を得る工程と、
    塩化金属前駆物質を用いるＡＬＤを複数回用いて他の金属酸化物の層を堆積する工程と、
    該集積回路を完成させる工程と
    を包含する、方法。
  10. 前記形成する工程は、前記シリコン表面をＨＦにより露出させる工程を含む、請求項９に記載の方法。
  11. ＨｆＯ２、ＺｒＯ２、Ｇｄ２Ｏ３、Ｌａ２Ｏ３、ＣｅＯ２、ＴｉＯ２、Ｙ２Ｏ３、Ｔａ２Ｏ５、およびＡｌ２Ｏ３からなる金属酸化物の群から選択される、前記シリコン基板上に堆積される金属酸化物を選択する工程を含む、請求項９に記載の方法。
  12. 前記第１の金属酸化物の層を堆積する工程は、０．１ｎｍ〜１．５ｎｍの間の厚さの最初の金属酸化物の層を堆積する工程を含む、請求項９に記載の方法。
  13. 前記他の金属酸化物の層を堆積する工程は、３ｎｍ〜１０ｎｍの間の厚さの金属酸化物の層を堆積する工程を含む、請求項９に記載の方法。
  14. 集積回路においてＨｆＯ２高κ誘電ゲート酸化物の層を形成する方法であって、
    シリコン基板を準備する工程であって、該シリコン基板のＨ終端表面を形成する工程を含む、工程と、
    Ｈｆ（ＮＯ３）４前駆物質を用いるＡＬＤを１〜５回用いて第１のＨｆＯ２金属酸化物の層を堆積して、所望の金属酸化物層厚を得る工程と、
    ＨｆＣｌ４前駆物質を用いるＡＬＤを複数回用いて他のＨｆＯ２の層を堆積する工程と、
    該集積回路を完成させる工程と
    を包含する、方法。
  15. 前記形成する工程は、前記シリコン表面をＨＦに露出させる工程を含む、請求項１４に記載の方法。
  16. 前記第１の金属酸化物の層を堆積する工程は、０．１ｎｍ〜１．５ｎｍの間の厚さの最初の金属酸化物の層を堆積する工程を含む、請求項１４に記載の方法。
  17. 前記他の金属酸化物の層を堆積する工程は、３ｎｍ〜１０ｎｍの間の厚さの金属酸化物の層を堆積する工程を含む、請求項１４に記載の方法。
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KR100538677B1 (ko) 2005-12-23
TW200406883A (en) 2004-05-01

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