JP4746269B2 - 低温度におけるゲートスタック製造方法 - Google Patents
低温度におけるゲートスタック製造方法 Download PDFInfo
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- JP4746269B2 JP4746269B2 JP2003543069A JP2003543069A JP4746269B2 JP 4746269 B2 JP4746269 B2 JP 4746269B2 JP 2003543069 A JP2003543069 A JP 2003543069A JP 2003543069 A JP2003543069 A JP 2003543069A JP 4746269 B2 JP4746269 B2 JP 4746269B2
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- silicon
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- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Ceramic Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Formation Of Insulating Films (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Chemical Vapour Deposition (AREA)
Description
Hu他、「Thin Gate Oxides Promise High Reliability」、SEMICONDUCTOR INTERNATIONAL(1998年7月)、215〜222頁 T.Suntra、Handbook of Crystal Growth 3、Thin Films and Epitaxy、Part B:Growth Mechanisms and Dynamics、Chapter 14、Atomic Layer Epitaxy、601〜663頁、Elsevier Science B.V.1994 Ritala他、Science 288:319〜321(2000) Yang他、Humantech Thesis Prize、Samsung Electronics(1999) Kim他、「Ultra Thin(<3nm)High Quality Nitride/Oxide Stack Gate Dielectrics Fabricated by In−Situ Rapid Thermal Processing」、IEDM 97(1997)、463〜466頁
・(CH3)3Alパルス
・N2パージ
・H2Oパルス
・N2パージ
例示的な酸化アルミニウム堆積サイクルを表Iに要約している。
Claims (4)
- 半導体基板上にゲート誘電体を形成する方法であって、
熱的酸化及び窒化によって、前記基板上に界面誘電体酸窒化物層を成長させるステップと、
高k層を堆積する間、前記界面誘電体酸窒化物層の厚さが約15Å未満だけ増加するような条件下での方法によって前記界面誘電体酸窒化物層を覆って前記高k層を堆積するステップと
を含み、
前記高k層が、酸素の不在下における揮発性の無水硝酸塩の直接堆積により堆積される方法。 - 前記熱的酸化及び窒化において、水蒸気が酸化剤として使用される、請求項1に記載の方法。
- 前記界面誘電体酸窒化物層がSiOxNyを含む、請求項1に記載の方法。
- 前記揮発性の無水硝酸塩は、前記高k層の堆積の間使用される唯一の反応物である、請求項1に記載の方法。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US31656201P | 2001-08-31 | 2001-08-31 | |
US60/316,562 | 2001-08-31 | ||
US10/227,475 | 2002-08-22 | ||
US10/227,475 US6806145B2 (en) | 2001-08-31 | 2002-08-22 | Low temperature method of forming a gate stack with a high k layer deposited over an interfacial oxide layer |
PCT/US2002/027230 WO2003041124A2 (en) | 2001-08-31 | 2002-08-26 | Method of fabricating a gate stack at low temperature |
Publications (3)
Publication Number | Publication Date |
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JP2005509287A JP2005509287A (ja) | 2005-04-07 |
JP2005509287A5 JP2005509287A5 (ja) | 2006-01-05 |
JP4746269B2 true JP4746269B2 (ja) | 2011-08-10 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2003543069A Expired - Lifetime JP4746269B2 (ja) | 2001-08-31 | 2002-08-26 | 低温度におけるゲートスタック製造方法 |
Country Status (4)
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US (1) | US6806145B2 (ja) |
JP (1) | JP4746269B2 (ja) |
AU (1) | AU2002363358A1 (ja) |
WO (1) | WO2003041124A2 (ja) |
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- 2002-08-26 WO PCT/US2002/027230 patent/WO2003041124A2/en active Application Filing
- 2002-08-26 AU AU2002363358A patent/AU2002363358A1/en not_active Abandoned
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Patent Citations (7)
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JP2001152339A (ja) * | 1999-10-06 | 2001-06-05 | Samsung Electronics Co Ltd | 原子層蒸着法を用いた薄膜形成方法 |
JP2001200363A (ja) * | 1999-12-03 | 2001-07-24 | Asm Microchemistry Oy | テクスチャ加工されたキャパシタ電極上のコンフォーマル薄膜 |
WO2001069665A1 (fr) * | 2000-03-13 | 2001-09-20 | Tadahiro Ohmi | Procede de formation de pellicule dielectrique |
WO2002023614A1 (fr) * | 2000-09-18 | 2002-03-21 | Tokyo Electron Limited | Procede de formation d'un film d'isolant de grille, appareil pour la formation d'un film d'isolant de grille et outil combine |
JP2002314072A (ja) * | 2001-04-19 | 2002-10-25 | Nec Corp | 高誘電体薄膜を備えた半導体装置及びその製造方法並びに誘電体膜の成膜装置 |
JP2002343790A (ja) * | 2001-05-21 | 2002-11-29 | Nec Corp | 金属化合物薄膜の気相堆積方法及び半導体装置の製造方法 |
JP2003069011A (ja) * | 2001-08-27 | 2003-03-07 | Hitachi Ltd | 半導体装置とその製造方法 |
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JP2005509287A (ja) | 2005-04-07 |
US20030049942A1 (en) | 2003-03-13 |
US6806145B2 (en) | 2004-10-19 |
WO2003041124A2 (en) | 2003-05-15 |
WO2003041124A3 (en) | 2003-11-20 |
AU2002363358A1 (en) | 2003-05-19 |
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