JP2005509287A - 低温度におけるゲートスタック製造方法 - Google Patents
低温度におけるゲートスタック製造方法 Download PDFInfo
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- JP2005509287A JP2005509287A JP2003543069A JP2003543069A JP2005509287A JP 2005509287 A JP2005509287 A JP 2005509287A JP 2003543069 A JP2003543069 A JP 2003543069A JP 2003543069 A JP2003543069 A JP 2003543069A JP 2005509287 A JP2005509287 A JP 2005509287A
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract
Description
Hu他、「Thin Gate Oxides Promise High Reliability」、SEMICONDUCTOR INTERNATIONAL(1998年7月)、215〜222頁 T.Suntra、Handbook of Crystal Growth 3、Thin Films and Epitaxy、Part B:Growth Mechanisms and Dynamics、Chapter 14、Atomic Layer Epitaxy、601〜663頁、Elsevier Science B.V.1994 Ritala他、Science 288:319〜321(2000) Yang他、Humantech Thesis Prize、Samsung Electronics(1999) Kim他、「Ultra Thin(<3nm)High Quality Nitride/Oxide Stack Gate Dielectrics Fabricated by In−Situ Rapid Thermal Processing」、IEDM 97(1997)、463〜466頁
・(CH3)3Alパルス
・N2パージ
・H2Oパルス
・N2パージ
例示的な酸化アルミニウム堆積サイクルを表Iに要約している。
Claims (43)
- 半導体基板上にゲート誘電体を形成する方法であって、
前記基板上に界面誘電体酸化物層を形成するステップと、
高k層を堆積する間、前記界面誘電体層の厚さが実質的に増加しないような条件下で、前記界面誘電体層を覆って前記高k材料を堆積するステップと
を含む方法。 - 前記高k層を堆積する温度が300℃以下である、請求項1に記載の方法。
- 堆積するステップが、酸素源として前記基板にH2Oを提供するステップを含む、請求項2に記載の方法。
- 前記界面層の前記厚さが約15Å未満である、請求項1に記載の方法。
- 前記界面層の前記厚さが約10Å未満である、請求項4に記載の方法。
- 前記界面層の前記厚さが約5Å未満である、請求項5に記載の方法。
- 前記界面誘電体酸化物層がSiO2である、請求項1に記載の方法。
- 前記界面誘電体層が、前記基板の熱的酸化によって生成される、請求項7に記載の方法。
- 熱的酸化が、酸化の穏やかな表面末端部を経由した酸化を含む、請求項8に記載の方法。
- 堆積するステップが、原子層堆積(ALD)方法を含む、請求項1に記載の方法。
- 前記ALD方法が複数のサイクルを含み、各サイクルが、
反応チャンバにおいて基板を第1の反応物と接触させるステップと、
前記未反応の第1の反応物を前記反応チャンバから除去するステップと、
前記基板を第2の反応物と接触させるステップと、
前記未反応の第2の反応物を前記反応チャンバから除去するステップと
を含む、請求項10に記載の方法。 - 前記第2の反応物が水蒸気である、請求項11に記載の方法。
- 前記ALD方法が300℃未満で実行される、請求項12に記載の方法。
- 前記高k層がAl2O3を含む、請求項13に記載の方法。
- 前記第1の反応物がトリメチルアルミニウム(TMA)であり、前記第2の反応物がH2Oである、請求項14に記載の方法。
- 前記高k層がZrO2を含む、請求項13に記載の方法。
- 前記第1の反応物がZrCl4であり、前記第2の反応物がH2Oである、請求項16に記載の方法。
- 基板の表面上に複合誘電体層を形成する方法であって、厚さ約15Å未満の酸化物層を形成するステップと、前記酸化物層をさらに成長させることなく、前記酸化物層の上面上に高k材料を堆積するステップとを含む方法。
- 前記酸化物層が厚さ約10Å未満である、請求項18に記載の方法。
- 前記酸化物層が厚さ約5Å未満である、請求項19に記載の方法。
- 前記酸化物層を形成するステップの前に、前記基板を清浄にするステップをさらに含む、請求項18に記載の方法。
- 前記基板がシリコンである、請求項18に記載の方法。
- 前記酸化物層が、前記シリコン基板の熱的酸化によって形成される、請求項22に記載の方法。
- 前記基板が、順次かつ交互に第1の金属含有化合物および第2の酸化性化合物に曝露される、順次表面反応を含むALD型方法によって、前記高k材料が堆積される、請求項18に記載の方法。
- 前記第2の酸化性化合物が金属有機化合物である、請求項24に記載の方法。
- 前記第1の金属含有化合物が金属ハロゲン化物であり、前記第2の酸化性化合物が金属アルコキシドである、請求項24に記載の方法。
- 前記第1の金属含有化合物および前記第2の酸化性化合物が、共に金属アルコキシドである、請求項24に記載の方法。
- 前記金属含有化合物が、ZrO2、HfO2、Ta2O5、TiO2、BST、ST、SBT、Al2O3、Nb2O5、およびLa2O3からなる群から選択される、請求項24に記載の方法。
- 前記酸化性化合物が水蒸気である、請求項24に記載の方法。
- 前記温度が300℃未満である、請求項24に記載の方法。
- 前記高k材料が、金属源化合物の直接分解により堆積される、請求項18に記載の方法。
- 前記高k材料が、CVDおよびMOCVDからなる群から選択される方法により堆積される、請求項18に記載の方法。
- 前記温度が300℃未満である、請求項32に記載の方法。
- 酸化剤として水蒸気が使用される、請求項32に記載の方法。
- 前記酸化物層がSiO2を含む、請求項18に記載の方法。
- 前記酸化物層が追加的に窒素を含む、請求項35に記載の方法。
- 前記高k材料を堆積するステップの前に、前記酸化物層上の任意の表面末端部を改質するステップを追加的に含む、請求項18に記載の方法。
- シリコン基板上に誘電体層を形成する方法であって、
前記基板上に、厚さが約15Å未満の酸化ケイ素界面層を成長させるステップと、
前記界面層の上面に、高k材料を堆積するステップと
を含み、
堆積するステップが、約300℃未満の温度に前記基板を維持するステップ、および酸化剤として水蒸気を供給するステップを含む方法。 - 堆積するステップが、ALD方法を含む、請求項38に記載の方法。
- 前記ALD方法が複数のサイクルを含み、各サイクルが、
前記基板を第1の反応物と接触させるステップと、
前記未反応の第1の反応物を反応チャンバから除去するステップと、
前記基板を水蒸気と接触させるステップと、
前記未反応の水蒸気を前記反応チャンバから除去するステップと
を含む、請求項39に記載の方法。 - 前記高k材料の堆積の間、前記界面層が約15Å未満だけ成長する、請求項38に記載の方法。
- 前記界面層が約10Å未満だけ成長する、請求項41に記載の方法。
- 前記界面層が約5Å未満だけ成長する、請求項42に記載の方法。
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US10/227,475 | 2002-08-22 | ||
US10/227,475 US6806145B2 (en) | 2001-08-31 | 2002-08-22 | Low temperature method of forming a gate stack with a high k layer deposited over an interfacial oxide layer |
PCT/US2002/027230 WO2003041124A2 (en) | 2001-08-31 | 2002-08-26 | Method of fabricating a gate stack at low temperature |
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AU2002363358A1 (en) | 2003-05-19 |
US20030049942A1 (en) | 2003-03-13 |
WO2003041124A3 (en) | 2003-11-20 |
US6806145B2 (en) | 2004-10-19 |
JP4746269B2 (ja) | 2011-08-10 |
WO2003041124A2 (en) | 2003-05-15 |
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