JP4000256B2 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

Info

Publication number
JP4000256B2
JP4000256B2 JP2001377623A JP2001377623A JP4000256B2 JP 4000256 B2 JP4000256 B2 JP 4000256B2 JP 2001377623 A JP2001377623 A JP 2001377623A JP 2001377623 A JP2001377623 A JP 2001377623A JP 4000256 B2 JP4000256 B2 JP 4000256B2
Authority
JP
Japan
Prior art keywords
semiconductor film
region
film
semiconductor
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2001377623A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003179056A (ja
JP2003179056A5 (enExample
Inventor
一幸 粂野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2001377623A priority Critical patent/JP4000256B2/ja
Priority to US10/101,974 priority patent/US6781207B2/en
Priority to TW091105611A priority patent/TW577146B/zh
Priority to KR1020020021255A priority patent/KR100815379B1/ko
Priority to EP02252913A priority patent/EP1320130B1/en
Priority to DE60220762T priority patent/DE60220762T2/de
Priority to CNB02119775XA priority patent/CN100386878C/zh
Publication of JP2003179056A publication Critical patent/JP2003179056A/ja
Publication of JP2003179056A5 publication Critical patent/JP2003179056A5/ja
Application granted granted Critical
Publication of JP4000256B2 publication Critical patent/JP4000256B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • H10D84/0119—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs the components including complementary BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0177—Manufacturing their gate conductors the gate conductors having different materials or different implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0186—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2001377623A 2001-12-11 2001-12-11 半導体装置及びその製造方法 Expired - Fee Related JP4000256B2 (ja)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP2001377623A JP4000256B2 (ja) 2001-12-11 2001-12-11 半導体装置及びその製造方法
US10/101,974 US6781207B2 (en) 2001-12-11 2002-03-21 Semiconductor device and manufacturing method thereof
TW091105611A TW577146B (en) 2001-12-11 2002-03-22 Semiconductor device and manufacturing method thereof
KR1020020021255A KR100815379B1 (ko) 2001-12-11 2002-04-18 반도체 장치 및 그 제조 방법
EP02252913A EP1320130B1 (en) 2001-12-11 2002-04-25 Semiconductor device and manufcaturing method thereof
DE60220762T DE60220762T2 (de) 2001-12-11 2002-04-25 Halbleiterbauelement und zugehöriges Herstellungsverfahren
CNB02119775XA CN100386878C (zh) 2001-12-11 2002-05-16 半导体器件及其制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001377623A JP4000256B2 (ja) 2001-12-11 2001-12-11 半導体装置及びその製造方法

Publications (3)

Publication Number Publication Date
JP2003179056A JP2003179056A (ja) 2003-06-27
JP2003179056A5 JP2003179056A5 (enExample) 2005-06-16
JP4000256B2 true JP4000256B2 (ja) 2007-10-31

Family

ID=19185541

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001377623A Expired - Fee Related JP4000256B2 (ja) 2001-12-11 2001-12-11 半導体装置及びその製造方法

Country Status (7)

Country Link
US (1) US6781207B2 (enExample)
EP (1) EP1320130B1 (enExample)
JP (1) JP4000256B2 (enExample)
KR (1) KR100815379B1 (enExample)
CN (1) CN100386878C (enExample)
DE (1) DE60220762T2 (enExample)
TW (1) TW577146B (enExample)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004342821A (ja) * 2003-05-15 2004-12-02 Renesas Technology Corp 半導体装置
US7197896B2 (en) 2003-09-05 2007-04-03 3M Innovative Properties Company Methods of making Al2O3-SiO2 ceramics
JP2005203436A (ja) * 2004-01-13 2005-07-28 Seiko Epson Corp 半導体装置の製造方法及び半導体装置
JP2005322730A (ja) * 2004-05-07 2005-11-17 Renesas Technology Corp 半導体装置及びその製造方法
JP4268569B2 (ja) * 2004-06-16 2009-05-27 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法
KR100647882B1 (ko) * 2004-07-09 2006-11-24 주식회사 마루스 접속력 향상구조를 갖는 전기접속기용 커넥터
JP4969779B2 (ja) * 2004-12-28 2012-07-04 株式会社東芝 半導体装置の製造方法
JP2006202860A (ja) * 2005-01-19 2006-08-03 Toshiba Corp 半導体装置及びその製造方法
KR100811267B1 (ko) * 2005-12-22 2008-03-07 주식회사 하이닉스반도체 반도체소자의 듀얼게이트 형성방법
JP5190189B2 (ja) * 2006-08-09 2013-04-24 パナソニック株式会社 半導体装置及びその製造方法
CN101577286B (zh) * 2008-05-05 2012-01-11 联华电子股份有限公司 复合式转移栅极及其制造方法
US11193634B2 (en) * 2012-07-03 2021-12-07 Tseng-Lu Chien LED and/or laser light source or bulb for light device
JP5559567B2 (ja) * 2010-02-24 2014-07-23 パナソニック株式会社 半導体装置
WO2012131818A1 (ja) 2011-03-25 2012-10-04 パナソニック株式会社 半導体装置及びその製造方法
FR2981503A1 (fr) * 2011-10-13 2013-04-19 St Microelectronics Rousset Transistor mos non sujet a l'effet hump
US9196624B2 (en) * 2012-07-10 2015-11-24 Cypress Semiconductor Corporation Leakage reducing writeline charge protection circuit
CN105206528A (zh) * 2014-06-17 2015-12-30 北大方正集团有限公司 平面vdmos器件的制造方法
JP6382025B2 (ja) * 2014-08-22 2018-08-29 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP2015188103A (ja) * 2015-06-03 2015-10-29 ラピスセミコンダクタ株式会社 半導体装置の製造方法
US10446567B2 (en) * 2017-03-31 2019-10-15 Asahi Kasei Microdevices Corporation Nonvolatile storage element and reference voltage generation circuit
US10734489B2 (en) * 2018-07-31 2020-08-04 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming semiconductor device structure with metal silicide layer

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2895166B2 (ja) * 1990-05-31 1999-05-24 キヤノン株式会社 半導体装置の製造方法
JPH06244369A (ja) 1993-02-19 1994-09-02 Sony Corp Ｃｍｏｓトランジスタおよびそのゲート電極との接続孔とその製造方法
JP3039200B2 (ja) * 1993-06-07 2000-05-08 日本電気株式会社 Ｍｏｓトランジスタおよびその製造方法
JPH0786421A (ja) 1993-09-13 1995-03-31 Fujitsu Ltd 相補型ｍｏｓトランジスタ及びその製造方法
JP3249292B2 (ja) 1994-04-28 2002-01-21 株式会社リコー デュアルゲート構造の相補形ｍｉｓ半導体装置
JPH098040A (ja) * 1995-06-16 1997-01-10 Sony Corp 配線及びその形成方法
JPH0974195A (ja) * 1995-07-06 1997-03-18 Mitsubishi Electric Corp 半導体装置および半導体装置の製造方法
JPH0927555A (ja) * 1995-07-10 1997-01-28 Ricoh Co Ltd 半導体装置とその製造方法
JPH0992823A (ja) * 1995-09-26 1997-04-04 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP3393249B2 (ja) * 1995-12-27 2003-04-07 ソニー株式会社 デュアルゲート構造を有する半導体装置およびその製造方法
JPH09205152A (ja) * 1996-01-25 1997-08-05 Sony Corp ２層ゲート電極構造を有するｃｍｏｓ半導体装置及びその製造方法
TW322591B (enExample) * 1996-02-09 1997-12-11 Handotai Energy Kenkyusho Kk
JPH09246541A (ja) 1996-03-07 1997-09-19 Sony Corp 半導体装置の製造方法
EP0798785B1 (en) * 1996-03-29 2003-12-03 STMicroelectronics S.r.l. High-voltage-resistant MOS transistor, and corresponding manufacturing process
JP2910839B2 (ja) 1996-06-25 1999-06-23 日本電気株式会社 半導体装置とその製造方法
JP4142753B2 (ja) * 1996-12-26 2008-09-03 株式会社東芝 スパッタターゲット、スパッタ装置、半導体装置およびその製造方法
EP0923116A1 (en) * 1997-12-12 1999-06-16 STMicroelectronics S.r.l. Process for manufacturing integrated multi-crystal silicon resistors in MOS technology and integrated MOS device comprising multi-crystal silicon resistors
KR100255134B1 (ko) * 1997-12-31 2000-05-01 윤종용 반도체 장치 및 그 제조 방법
JP3737914B2 (ja) 1999-09-02 2006-01-25 松下電器産業株式会社 半導体装置及びその製造方法
US6191460B1 (en) * 1999-09-07 2001-02-20 Integrated Device Technology, Inc. Identical gate conductivity type static random access memory cell
JP2001156290A (ja) * 1999-11-30 2001-06-08 Nec Corp 半導体装置
KR20010066122A (ko) * 1999-12-31 2001-07-11 박종섭 반도체 소자의 폴리사이드 듀얼 게이트 형성 방법
JP2001210725A (ja) 2000-01-25 2001-08-03 Matsushita Electric Ind Co Ltd 半導体装置
JP2001332630A (ja) * 2000-05-19 2001-11-30 Sharp Corp 半導体装置の製造方法
JP2002217310A (ja) * 2001-01-18 2002-08-02 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6894356B2 (en) * 2002-03-15 2005-05-17 Integrated Device Technology, Inc. SRAM system having very lightly doped SRAM load transistors for improving SRAM cell stability and method for making the same

Also Published As

Publication number Publication date
KR100815379B1 (ko) 2008-03-20
TW577146B (en) 2004-02-21
US6781207B2 (en) 2004-08-24
US20030107090A1 (en) 2003-06-12
CN1426110A (zh) 2003-06-25
CN100386878C (zh) 2008-05-07
EP1320130B1 (en) 2007-06-20
DE60220762D1 (de) 2007-08-02
KR20030047660A (ko) 2003-06-18
JP2003179056A (ja) 2003-06-27
DE60220762T2 (de) 2007-10-11
EP1320130A2 (en) 2003-06-18
EP1320130A3 (en) 2005-05-11

Similar Documents

Publication Publication Date Title
JP4000256B2 (ja) 半導体装置及びその製造方法
US8058120B2 (en) Integration scheme for strained source/drain CMOS using oxide hard mask
US7183613B1 (en) Method and structure for enhancing both NMOSFET and PMOSFET performance with a stressed film
JP2010502015A (ja) 相補型シリコン・オン・インシュレータ（ｓｏｉ）接合型電界効果トランジスタ、及びその製造方法
JP2003142601A (ja) 半導体素子のｃｍｏｓ及びその製造方法
US20090309163A1 (en) Method and structure for enhancing both nmosfet and pmosfet performance with a stressed film and discontinuity extending to underlying layer
US7737495B2 (en) Semiconductor device having inter-layers with stress levels corresponding to the transistor type
US7820500B2 (en) Single mask scheme method and structure for integrating PMOS and NMOS transistors using strained silicon
JP2009526409A (ja) 絶縁体上に半導体が設けられた構造（ｓｏｉ）を有するボディコンタクト素子の形成方法及び装置
US6633069B2 (en) Semiconductor device
US6593631B2 (en) Method of fabricating semiconductor device
US8216907B2 (en) Process to fabricate a metal high-K transistor having first and second silicon sidewalls for reduced parasitic capacitance
TW594887B (en) Process for producing semiconductor device and semiconductor device
US20060134874A1 (en) Manufacture method of MOS semiconductor device having extension and pocket
US6958279B2 (en) Method for manufacturing semiconductor device
US7271414B2 (en) Semiconductor device and method for fabricating the same
US7253039B2 (en) Method of manufacturing CMOS transistor by using SOI substrate
KR100717503B1 (ko) 반도체 소자 및 그 제조 방법
KR100552859B1 (ko) 반도체 소자의 제조 방법
US20080145990A1 (en) Method and structure for fabricating mos devices with a salicided gate and source/drain combined with a non-silicide source drain regions
KR100881494B1 (ko) 반도체 소자의 제조방법
JPH10189952A (ja) 半導体装置およびその製造方法
WO2006109221A2 (en) Lateral bipolar transistor
JP2004039681A (ja) 半導体装置およびその製造方法
JPH08288509A (ja) 半導体装置及びその製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040915

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040915

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060328

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060522

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20070724

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20070813

R150 Certificate of patent or registration of utility model

Ref document number: 4000256

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100817

Year of fee payment: 3

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100817

Year of fee payment: 3

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110817

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110817

Year of fee payment: 4

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110817

Year of fee payment: 4

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110817

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120817

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130817

Year of fee payment: 6

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees